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This commit is contained in:
antoniovillena 2016-12-16 13:45:12 +01:00
parent 25572db652
commit a24ec4713f
11 changed files with 311 additions and 487 deletions
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310
cores/BBCMicro/src/multiboot_v4.v Normal file
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@ -0,0 +1,310 @@
module multiboot (
input wire clk_icap,
input wire REBOOT
);
reg [23:0] spi_addr = 24'h058000; // default: SPI address of second core as defined by the SPI memory map
reg [4:0] q = 5'b00000;
reg reboot_ff = 1'b0;
always @(posedge clk_icap) begin
q[0] <= REBOOT;
q[1] <= q[0];
q[2] <= q[1];
q[3] <= q[2];
q[4] <= q[3];
reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
end
multiboot_spartan6 hacer_multiboot (
.CLK(clk_icap),
.MBT_RESET(1'b0),
.MBT_REBOOT(reboot_ff),
.spi_addr(spi_addr)
);
endmodule
module multiboot_spartan6 (
input wire CLK,
input wire MBT_RESET,
input wire MBT_REBOOT,
input wire [23:0] spi_addr
);
reg [15:0] icap_din;
reg icap_ce;
reg icap_wr;
reg [15:0] ff_icap_din_reversed;
reg ff_icap_ce;
reg ff_icap_wr;
ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
.CE (ff_icap_ce), // Clock enable input
.CLK (CLK), // Clock input
.I (ff_icap_din_reversed), // 16-bit data input
.WRITE (ff_icap_wr) // Write input
);
// -------------------------------------------------
// -- State Machine for ICAP_SPARTAN6 MultiBoot --
// -------------------------------------------------
parameter IDLE = 0,
SYNC_H = 1,
SYNC_L = 2,
CWD_H = 3,
CWD_L = 4,
GEN1_H = 5,
GEN1_L = 6,
GEN2_H = 7,
GEN2_L = 8,
GEN3_H = 9,
GEN3_L = 10,
GEN4_H = 11,
GEN4_L = 12,
GEN5_H = 13,
GEN5_L = 14,
NUL_H = 15,
NUL_L = 16,
MOD_H = 17,
MOD_L = 18,
HCO_H = 19,
HCO_L = 20,
RBT_H = 21,
RBT_L = 22,
NOOP_0 = 23,
NOOP_1 = 24,
NOOP_2 = 25,
NOOP_3 = 26;
reg [4:0] state;
reg [4:0] next_state;
always @*
begin: COMB
case (state)
IDLE:
begin
if (MBT_REBOOT)
begin
next_state = SYNC_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'hAA99; // Sync word 1
end
else
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'hFFFF; // Null
end
end
SYNC_H:
begin
next_state = SYNC_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h5566; // Sync word 2
end
SYNC_L:
begin
next_state = NUL_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
NUL_H:
begin
// next_state = NUL_L;
next_state = GEN1_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h0000; // Null Command issued.... value = 0x0000
end
//Q
GEN1_H:
begin
next_state = GEN1_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3261; // Escritura a reg GENERAL_1 (bit boot en caliente)
end
GEN1_L:
begin
next_state = GEN2_H;
icap_ce = 0;
icap_wr = 0;
icap_din = spi_addr[15:0]; //16'hC000; // dreccion SPI BAJA
end
GEN2_H:
begin
next_state = GEN2_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3281; // Escritura a reg GENERAL_2
end
GEN2_L:
begin
next_state = MOD_H;
icap_ce = 0;
icap_wr = 0;
icap_din = {8'h6B, spi_addr[23:16]}; // 16'h030A; // 03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
end
/////// Registro MODE (para carga a 4x tras reboot)
MOD_H:
begin
next_state = MOD_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3301; // Escritura a reg MODE
end
MOD_L:
begin
next_state = NUL_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
end
/////
NUL_L:
begin
next_state = RBT_H;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h30A1; // Write to Command Register....
end
RBT_H:
begin
next_state = RBT_L;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h000E; // REBOOT Command 0x000E
end
//--------------------
RBT_L:
begin
next_state = NOOP_0;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_0:
begin
next_state = NOOP_1;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_1:
begin
next_state = NOOP_2;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
NOOP_2:
begin
next_state = NOOP_3;
icap_ce = 0;
icap_wr = 0;
icap_din = 16'h2000; // NOOP
end
//--------------------
NOOP_3:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // NULL value
end
default:
begin
next_state = IDLE;
icap_ce = 1;
icap_wr = 1;
icap_din = 16'h1111; // 16'h1111"
end
endcase
end
always @(posedge CLK)
begin: SEQ
if (MBT_RESET)
state <= IDLE;
else
state <= next_state;
end
always @(posedge CLK)
begin: ICAP_FF
ff_icap_din_reversed[0] <= icap_din[7]; //need to reverse bits to ICAP module since D0 bit is read first
ff_icap_din_reversed[1] <= icap_din[6];
ff_icap_din_reversed[2] <= icap_din[5];
ff_icap_din_reversed[3] <= icap_din[4];
ff_icap_din_reversed[4] <= icap_din[3];
ff_icap_din_reversed[5] <= icap_din[2];
ff_icap_din_reversed[6] <= icap_din[1];
ff_icap_din_reversed[7] <= icap_din[0];
ff_icap_din_reversed[8] <= icap_din[15];
ff_icap_din_reversed[9] <= icap_din[14];
ff_icap_din_reversed[10] <= icap_din[13];
ff_icap_din_reversed[11] <= icap_din[12];
ff_icap_din_reversed[12] <= icap_din[11];
ff_icap_din_reversed[13] <= icap_din[10];
ff_icap_din_reversed[14] <= icap_din[9];
ff_icap_din_reversed[15] <= icap_din[8];
ff_icap_ce <= icap_ce;
ff_icap_wr <= icap_wr;
end
endmodule

274
cores/BBCMicro/src/scandoubler/rgb2vga.vhd
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@ -1,274 +0,0 @@
--
-- Copyright (C) 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rgb2vga is
port (
-- 32MHz pixel clock from BBC Micro
clock : in std_logic;
-- 16MHz clock enable BBC Micro
clken : in std_logic;
-- 25MHz VGA clock
clk25 : in std_logic;
-- Input 15.625kHz RGB signals
rgbi_in : in std_logic_vector(3 downto 0);
hSync_in : in std_logic;
vSync_in : in std_logic;
-- Output 31.250kHz VGA signals
rgbi_out : out std_logic_vector(3 downto 0);
hSync_out : out std_logic;
vSync_out : out std_logic
);
end entity;
architecture rtl of rgb2vga is
-- Config parameters
constant SAMPLE_OFFSET : integer := 240;
constant SAMPLE_WIDTH : integer := 656;
-- -- original values
-- constant width25 : integer := 10;
-- constant HORIZ_RT : integer := 96;
-- constant HORIZ_BP : integer := 30;
-- constant HORIZ_DISP : integer := 656;
-- constant HORIZ_FP : integer := 18;
-- -- Values for 1170x584 (total 1480x624) with 46.2MHz clock
-- constant width25 : integer := 11;
-- constant HORIZ_RT : integer := 176;
-- constant HORIZ_BP : integer := 404;
-- constant HORIZ_DISP : integer := 656;
-- constant HORIZ_FP : integer := 244;
-- Values for 720x576p (total 864x625) with 27MHz clock
-- worked quite well on Belina and on LG
-- ModeLine "720x576" 27.00 720 732 796 864 576 581 586 625 -HSync -VSync
constant width25 : integer := 10;
constant HORIZ_RT : integer := 64;
constant HORIZ_BP : integer := 68 + 32;
constant HORIZ_DISP : integer := 656;
constant HORIZ_FP : integer := 12 + 32;
-- -- Values for 800x600 (total 1056x625) with 33.032MHz clock
-- constant width25 : integer := 11;
-- constant HORIZ_RT : integer := 96;
-- constant HORIZ_BP : integer := 152;
-- constant HORIZ_DISP : integer := 656;
-- constant HORIZ_FP : integer := 152;
-- -- Values for 800x600 (total 1024x625) with 32.000MHz clock
-- constant width25 : integer := 11;
-- constant HORIZ_RT : integer := 128;
-- constant HORIZ_BP : integer := 160;
-- constant HORIZ_DISP : integer := 656;
-- constant HORIZ_FP : integer := 80;
-- -- Values for 800x600 (total 960x625) with 30.000MHz clock
-- -- Modeline "800x600@50" 30 800 814 884 960 600 601 606 625 +hsync +vsync
-- constant width25 : integer := 10;
-- constant HORIZ_RT : integer := 70;
-- constant HORIZ_BP : integer := 76 + 72;
-- constant HORIZ_DISP : integer := 656;
-- constant HORIZ_FP : integer := 14 + 72;
-- VSYNC state-machine
type VType is (
S_WAIT_VSYNC,
S_EXTRA1,
S_EXTRA2,
S_NOEXTRA,
S_ASSERT_VSYNC
);
-- Registers in the 16MHz clock domain:
signal state : VType := S_WAIT_VSYNC;
signal state_next : VType;
signal hSync_s16 : std_logic;
signal vSync_s16 : std_logic;
signal hSyncStart : std_logic;
signal vSyncStart : std_logic;
signal hCount16 : unsigned(9 downto 0) := (others => '0');
signal hCount16_next : unsigned(9 downto 0);
signal lineToggle : std_logic := '1';
signal lineToggle_next : std_logic;
-- Registers in the 25MHz clock domain:
signal hSync_s25a : std_logic;
signal hSync_s25b : std_logic;
signal hCount25 : unsigned(width25 - 1 downto 0) := to_unsigned(HORIZ_DISP + HORIZ_FP, width25);
signal hCount25_next : unsigned(width25 - 1 downto 0);
-- Signals on the write side of the RAMs:
signal writeEn0 : std_logic;
signal writeEn1 : std_logic;
-- Signals on the read side of the RAMs:
signal ram0Data : std_logic_vector(3 downto 0);
signal ram1Data : std_logic_vector(3 downto 0);
begin
-- Two RAM blocks, each straddling the 16MHz and 25MHz clock domains, for storing pixel lines;
-- whilst we're reading from one at 25MHz, we're writing to the other at 16MHz. Their roles
-- swap every incoming 64us scanline.
--
ram0: entity work.rgb2vga_dpram
port map(
-- Write port
wrclock => clock,
wraddress => std_logic_vector(hCount16),
wren => writeEn0,
data => rgbi_in,
-- Read port
rdclock => clk25,
rdaddress => std_logic_vector(hCount25(9 downto 0)),
q => ram0data
);
ram1: entity work.rgb2vga_dpram
port map(
-- Write port
wrclock => clock,
wraddress => std_logic_vector(hCount16),
wren => writeEn1,
data => rgbi_in,
-- Read port
rdclock => clk25,
rdaddress => std_logic_vector(hCount25(9 downto 0)),
q => ram1data
);
-- 16MHz clock domain ---------------------------------------------------------------------------
process(clock)
begin
if rising_edge(clock) then
if clken = '1' then
hSync_s16 <= hSync_in;
vSync_s16 <= vSync_in;
hCount16 <= hCount16_next;
lineToggle <= lineToggle_next;
state <= state_next;
end if;
end if;
end process;
-- Pulses representing the start of incoming HSYNC & VSYNC
hSyncStart <=
'1' when hSync_s16 = '0' and hSync_in = '1'
else '0';
vSyncStart <=
'1' when vSync_s16 = '0' and vSync_in = '1'
else '0';
-- Create horizontal count, aligned to incoming HSYNC
hCount16_next <=
to_unsigned(2**10 - SAMPLE_OFFSET + 1, 10) when hSyncStart = '1'
else hCount16 + 1;
-- Toggle every incoming HSYNC
lineToggle_next <=
not(lineToggle) when hSyncStart = '1'
else lineToggle;
-- Generate interleaved write signals for dual-port RAMs
writeEn0 <=
'1' when hCount16 < SAMPLE_WIDTH and lineToggle = '0' and clken = '1'
else '0';
writeEn1 <=
'1' when hCount16 < SAMPLE_WIDTH and lineToggle = '1' and clken = '1'
else '0';
-- Interleave output of dual-port RAMs
rgbi_out <=
ram0Data when lineToggle = '1'
else ram1Data;
-- State machine to generate VGA VSYNC
process(state, vSyncStart, hSyncStart, hCount16(9))
begin
state_next <= state;
case state is
-- Wait for VSYNC start
when S_WAIT_VSYNC =>
vSync_out <= '1';
if ( vSyncStart = '1' ) then
if ( hCount16(9) = '0' ) then
state_next <= S_EXTRA1;
else
state_next <= S_NOEXTRA;
end if;
end if;
-- Insert an extra 64us scanline
when S_EXTRA1 =>
vSync_out <= '1';
if ( hSyncStart = '1' ) then
state_next <= S_EXTRA2; -- 0.5 lines after VSYNC
end if;
when S_EXTRA2 =>
vSync_out <= '1';
if ( hSyncStart = '1' ) then
state_next <= S_ASSERT_VSYNC; -- 1.5 lines after VSYNC
end if;
-- Don't insert an extra 64us scanline
when S_NOEXTRA =>
vSync_out <= '1';
if ( hSyncStart = '1' ) then
state_next <= S_ASSERT_VSYNC; -- 0.5 lines after VSYNC
end if;
-- Assert VGA VSYNC for 64us
when S_ASSERT_VSYNC =>
vSync_out <= '0';
if ( hSyncStart = '1' ) then
state_next <= S_WAIT_VSYNC;
end if;
end case;
end process;
-- 25MHz clock domain ---------------------------------------------------------------------------
process(clk25)
begin
if ( rising_edge(clk25) ) then
hCount25 <= hCount25_next;
hSync_s25a <= hSync_in;
hSync_s25b <= hSync_s25a;
end if;
end process;
-- Generate 25MHz hCount
hCount25_next <=
to_unsigned(2**width25 - HORIZ_RT - HORIZ_BP, width25) when
(hSync_s25a = '1' and hSync_s25b = '0') or
(hCount25 = HORIZ_DISP + HORIZ_FP - 1)
else hCount25 + 1;
-- Generate VGA HSYNC
hSync_out <=
'0' when hCount25 >= to_unsigned(2**width25 - HORIZ_RT - HORIZ_BP, width25) and hCount25 < to_unsigned(2**width25 - HORIZ_BP, width25)
else '1';
end architecture;

58
cores/BBCMicro/src/scandoubler/rgb2vga_dcm.vhd
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@ -1,58 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity rgb2vga_dcm is
port (CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic);
end rgb2vga_dcm;
architecture BEHAVIORAL of rgb2vga_dcm is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
signal CLK0 : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLKFX_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 27,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => CLK0,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => CLK0,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;

41
cores/BBCMicro/src/scandoubler/rgb2vga_dpram.vhd
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@ -1,41 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rgb2vga_dpram is
port (
wrclock : in std_logic;
wren : in std_logic;
wraddress : in std_logic_vector(9 downto 0);
data : in std_logic_vector(3 downto 0);
rdclock : in std_logic;
rdaddress : in std_logic_vector(9 downto 0);
q : out std_logic_vector(3 downto 0)
);
end;
architecture behavioral of rgb2vga_dpram is
type ram_type is array (1023 downto 0) of std_logic_vector (3 downto 0);
shared variable RAM : ram_type;
begin
process (wrclock)
begin
if rising_edge(wrclock) then
if (wren = '1') then
RAM(conv_integer(wraddress)) := data;
end if;
end if;
end process;
process (rdclock)
begin
if rising_edge(rdclock) then
q <= RAM(conv_integer(rdaddress));
end if;
end process;
end behavioral;

14
cores/BBCMicro/src/sn76489-1.0/sn76489_attenuator-c.vhd
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@ -1,14 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_attenuator-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_attenuator_rtl_c0 of sn76489_attenuator is
for rtl
end for;
end sn76489_attenuator_rtl_c0;

14
cores/BBCMicro/src/sn76489-1.0/sn76489_clock_div-c.vhd
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@ -1,14 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_clock_div-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_clock_div_rtl_c0 of sn76489_clock_div is
for rtl
end for;
end sn76489_clock_div_rtl_c0;

14
cores/BBCMicro/src/sn76489-1.0/sn76489_latch_ctrl-c.vhd
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@ -1,14 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_latch_ctrl-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_latch_ctrl_rtl_c0 of sn76489_latch_ctrl is
for rtl
end for;
end sn76489_latch_ctrl_rtl_c0;

19
cores/BBCMicro/src/sn76489-1.0/sn76489_noise-c.vhd
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@ -1,19 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_noise-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_noise_rtl_c0 of sn76489_noise is
for rtl
for attenuator_b : sn76489_attenuator
use configuration work.sn76489_attenuator_rtl_c0;
end for;
end for;
end sn76489_noise_rtl_c0;

19
cores/BBCMicro/src/sn76489-1.0/sn76489_tone-c.vhd
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@ -1,19 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_tone-c.vhd,v 1.2 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_tone_rtl_c0 of sn76489_tone is
for rtl
for attenuator_b : sn76489_attenuator
use configuration work.sn76489_attenuator_rtl_c0;
end for;
end for;
end sn76489_tone_rtl_c0;

31
cores/BBCMicro/src/sn76489-1.0/sn76489_top-c.vhd
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@ -1,31 +0,0 @@
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_top-c.vhd,v 1.3 2005/10/10 22:12:38 arnim Exp $
--
-------------------------------------------------------------------------------
configuration sn76489_top_struct_c0 of sn76489_top is
for struct
for clock_div_b : sn76489_clock_div
use configuration work.sn76489_clock_div_rtl_c0;
end for;
for latch_ctrl_b : sn76489_latch_ctrl
use configuration work.sn76489_latch_ctrl_rtl_c0;
end for;
for all : sn76489_tone
use configuration work.sn76489_tone_rtl_c0;
end for;
for noise_b : sn76489_noise
use configuration work.sn76489_noise_rtl_c0;
end for;
end for;
end sn76489_top_struct_c0;

4
cores/BBCMicro/working/bbc_micro.prj
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@ -7,19 +7,17 @@ vhdl work "../src/sn76489-1.0/sn76489_tone.vhd"
vhdl work "../src/sn76489-1.0/sn76489_noise.vhd"
vhdl work "../src/sn76489-1.0/sn76489_latch_ctrl.vhd"
vhdl work "../src/sn76489-1.0/sn76489_clock_div.vhd"
vhdl work "../src/scandoubler/rgb2vga_dpram.vhd"
vhdl work "../src/saa5050_rom_dual_port.vhd"
vhdl work "../src/ps2_intf.vhd"
vhdl work "../src/vidproc.vhd"
vhdl work "../src/T65/T65.vhd"
vhdl work "../src/sn76489-1.0/sn76489_top.vhd"
vhdl work "../src/scandoubler/rgb2vga_dcm.vhd"
vhdl work "../src/scandoubler/rgb2vga.vhd"
verilog work "../src/scandoubler/mist_scandoubler.v"
vhdl work "../src/saa5050.vhd"
vhdl work "../src/rom_image.vhd"
vhdl work "../src/relojes.vhd"
vhdl work "../src/pmw_sddac.vhd"
verilog work "../src/multiboot_v4.v"
vhdl work "../src/mc6845.vhd"
vhdl work "../src/m6522.vhd"
vhdl work "../src/keyboard.vhd"