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Pequeñas mejoras en Pentagon

This commit is contained in:
antoniovillena 2016-08-03 00:29:37 +02:00
parent 74bf3152d5
commit a4d0fb4e5f
3 changed files with 32 additions and 19 deletions
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6
cores/Spectrum/coreid.v
View File

@ -39,10 +39,10 @@ module coreid (
text[ 1] = "2"; text[ 1] = "2";
text[ 2] = "2"; text[ 2] = "2";
text[ 3] = "-"; text[ 3] = "-";
text[ 4] = "1"; text[ 4] = "0";
text[ 5] = "4"; text[ 5] = "1";
text[ 6] = "0"; text[ 6] = "0";
text[ 7] = "7"; text[ 7] = "8";
text[ 8] = "2"; text[ 8] = "2";
text[ 9] = "0"; text[ 9] = "0";
text[10] = "1"; text[10] = "1";

4
cores/Spectrum/pal_sync_generator.v
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@ -120,8 +120,8 @@ module pal_sync_generator (
end_vsync <= 9'd255; // 9'd243; end_vsync <= 9'd255; // 9'd243;
begin_vcint <= 9'd239; begin_vcint <= 9'd239;
end_vcint <= 9'd239; end_vcint <= 9'd239;
begin_hcint <= 9'd320; // 9'd318; begin_hcint <= 9'd323; // 9'd320;
end_hcint <= 9'd391; //9'd389; end_hcint <= 9'd391; //9'd391;
end end
endcase endcase
end end

41
cores/Spectrum/ula_radas.v
View File

@ -85,6 +85,12 @@ module ula_radas (
EVPIXEL = 191, EVPIXEL = 191,
BVSYNC = 248; BVSYNC = 248;
parameter
ULA48K = 2'b00,
ULA128K = 2'b01,
PENTAGON = 2'b10,
RESERVED = 2'b11;
// RGB inputs to sync module // RGB inputs to sync module
reg [2:0] ri; reg [2:0] ri;
reg [2:0] gi; reg [2:0] gi;
@ -397,6 +403,14 @@ module ula_radas (
/////////////////////////////////////////////// ///////////////////////////////////////////////
// control data flow from VRAM to RGB output // control data flow from VRAM to RGB output
reg Border_n;
always @* begin
if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
Border_n = 1;
else
Border_n = 0;
end
always @* begin always @* begin
BitmapDataLoad = 1'b0; BitmapDataLoad = 1'b0;
AttrDataLoad = 1'b0; AttrDataLoad = 1'b0;
@ -409,18 +423,25 @@ module ula_radas (
if (!RadasEnabled) begin // Control para los modos estándar if (!RadasEnabled) begin // Control para los modos estándar
if (hc[2:0]==3'd4) begin // hc=4,12,20,28,etc
AttrOutputLoad = 1'b1; // updated every 8 pixel clocks
end
if (hc[2:0]==3'd3) begin
CALoad = 1'b1;
end
if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area
VideoEnable = 1'b1; VideoEnable = 1'b1;
if (hc[2:0]==3'd4) begin if (hc[2:0]==3'd4) begin
SerializerLoad = 1'b1; // updated every 8 pixel clocks, if we are in paper area SerializerLoad = 1'b1; // updated every 8 pixel clocks, if we are in paper area
end end
end end
if (mode == PENTAGON) begin
if (hc<(BHPIXEL+8) || hc>(EHPIXEL+12) || vc<BVPIXEL || vc>EVPIXEL)
AttrOutputLoad = 1'b1; // updated every clock for Pentagon border
else if (hc[2:0] == 3'd4) // hc=4,12,20,28,etc
AttrOutputLoad = 1'b1; // updated every 8 pixel clocks for Pentagon paper
end
else begin
if (hc[2:0] == 3'd4) // hc=4,12,20,28,etc
AttrOutputLoad = 1'b1; // updated every 8 pixel clocks
end
if (hc[2:0]==3'd3) begin
CALoad = 1'b1;
end
if (hc>=BHPIXEL && hc<=EHPIXEL && vc>=BVPIXEL && vc<=EVPIXEL) begin if (hc>=BHPIXEL && hc<=EHPIXEL && vc>=BVPIXEL && vc<=EVPIXEL) begin
if (hc[3:0]==4'd8 || hc[3:0]==4'd12) begin if (hc[3:0]==4'd8 || hc[3:0]==4'd12) begin
BitmapAddr = 1'b1; BitmapAddr = 1'b1;
@ -535,14 +556,6 @@ module ula_radas (
wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA); wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA);
wire ioreqall_n = !(iorequlaplus || iorequla); wire ioreqall_n = !(iorequlaplus || iorequla);
reg Border_n;
always @* begin
if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
Border_n = 1;
else
Border_n = 0;
end
/////////////////////////////////// ///////////////////////////////////
// CPU CLOCK GENERATION (Altwasser method) // CPU CLOCK GENERATION (Altwasser method)
/////////////////////////////////// ///////////////////////////////////