mirror of https://github.com/zxdos/zxuno.git
Pequeñas mejoras en Pentagon
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@ -39,10 +39,10 @@ module coreid (
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text[ 1] = "2";
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text[ 2] = "2";
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text[ 3] = "-";
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text[ 4] = "1";
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text[ 5] = "4";
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text[ 4] = "0";
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text[ 5] = "1";
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text[ 6] = "0";
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text[ 7] = "7";
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text[ 7] = "8";
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text[ 8] = "2";
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text[ 9] = "0";
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text[10] = "1";
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@ -120,8 +120,8 @@ module pal_sync_generator (
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end_vsync <= 9'd255; // 9'd243;
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begin_vcint <= 9'd239;
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end_vcint <= 9'd239;
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begin_hcint <= 9'd320; // 9'd318;
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end_hcint <= 9'd391; //9'd389;
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begin_hcint <= 9'd323; // 9'd320;
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end_hcint <= 9'd391; //9'd391;
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end
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endcase
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end
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@ -85,6 +85,12 @@ module ula_radas (
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EVPIXEL = 191,
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BVSYNC = 248;
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parameter
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ULA48K = 2'b00,
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ULA128K = 2'b01,
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PENTAGON = 2'b10,
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RESERVED = 2'b11;
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// RGB inputs to sync module
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reg [2:0] ri;
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reg [2:0] gi;
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@ -397,6 +403,14 @@ module ula_radas (
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///////////////////////////////////////////////
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// control data flow from VRAM to RGB output
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reg Border_n;
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always @* begin
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if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
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Border_n = 1;
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else
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Border_n = 0;
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end
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always @* begin
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BitmapDataLoad = 1'b0;
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AttrDataLoad = 1'b0;
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@ -409,18 +423,25 @@ module ula_radas (
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if (!RadasEnabled) begin // Control para los modos estándar
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if (hc[2:0]==3'd4) begin // hc=4,12,20,28,etc
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AttrOutputLoad = 1'b1; // updated every 8 pixel clocks
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end
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if (hc[2:0]==3'd3) begin
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CALoad = 1'b1;
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end
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if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area
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VideoEnable = 1'b1;
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if (hc[2:0]==3'd4) begin
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SerializerLoad = 1'b1; // updated every 8 pixel clocks, if we are in paper area
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end
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end
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if (mode == PENTAGON) begin
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if (hc<(BHPIXEL+8) || hc>(EHPIXEL+12) || vc<BVPIXEL || vc>EVPIXEL)
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AttrOutputLoad = 1'b1; // updated every clock for Pentagon border
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else if (hc[2:0] == 3'd4) // hc=4,12,20,28,etc
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AttrOutputLoad = 1'b1; // updated every 8 pixel clocks for Pentagon paper
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end
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else begin
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if (hc[2:0] == 3'd4) // hc=4,12,20,28,etc
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AttrOutputLoad = 1'b1; // updated every 8 pixel clocks
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end
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if (hc[2:0]==3'd3) begin
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CALoad = 1'b1;
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end
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if (hc>=BHPIXEL && hc<=EHPIXEL && vc>=BVPIXEL && vc<=EVPIXEL) begin
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if (hc[3:0]==4'd8 || hc[3:0]==4'd12) begin
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BitmapAddr = 1'b1;
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@ -535,14 +556,6 @@ module ula_radas (
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wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA);
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wire ioreqall_n = !(iorequlaplus || iorequla);
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reg Border_n;
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always @* begin
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if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
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Border_n = 1;
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else
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Border_n = 0;
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end
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///////////////////////////////////
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// CPU CLOCK GENERATION (Altwasser method)
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///////////////////////////////////
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