diff --git a/cores/Spectrum/audio_management.v b/cores/Spectrum/audio_management.v index 883991a..2055bf4 100644 --- a/cores/Spectrum/audio_management.v +++ b/cores/Spectrum/audio_management.v @@ -77,19 +77,15 @@ module mixer ( ({ear,spk,mic}==3'b110)? 8'd244 : 8'd255; reg [7:0] mezcla; - reg [3:0] cntsamples = 4'd0; reg [1:0] sndsource = 2'd0; always @(posedge clkdac) begin - if (cntsamples == 4'd0) begin // cada 256 cuentas de reloj, cambiamos de fuente de sonido - case (sndsource) - SRC_BEEPER: mezcla <= beeper; - SRC_AY1 : mezcla <= ay1; - SRC_AY2 : mezcla <= ay2; - endcase - sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido - end - cntsamples <= cntsamples + 4'd1; + case (sndsource) + SRC_BEEPER: mezcla <= beeper; + SRC_AY1 : mezcla <= ay1; + SRC_AY2 : mezcla <= ay2; + endcase + sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido end dac audio_dac ( diff --git a/cores/Spectrum/bootloader_hex.txt b/cores/Spectrum/bootloader_hex.txt index ba17a89..fe28cab 100644 --- a/cores/Spectrum/bootloader_hex.txt +++ b/cores/Spectrum/bootloader_hex.txt @@ -1,5 +1,5 @@ 31 -B1 +AE BF 11 61 @@ -10,7 +10,7 @@ D5 ED D5 01 -AE +AB BF 18 2B @@ -49,11 +49,11 @@ FE ED A3 E9 -5A -58 -55 -6E -6F +05 +ED +61 +04 +C9 C3 43 C0 @@ -67,15 +67,18 @@ EF 08 DB 1F -F6 -E7 -3C -28 +E6 +1F +FE +18 28 +27 +EF +0B +80 EF 03 01 -AF EF 03 00 @@ -83,23 +86,20 @@ EF 02 03 ED -79 -39 +61 ED 59 ED -79 +61 +39 ED A2 04 BC 38 FA -05 -ED -61 -04 -C9 +18 +CD C3 40 C0 @@ -128,7 +128,7 @@ C0 02 40 2E -62 +34 E5 3E 0F diff --git a/cores/Spectrum/control_enable_options.v b/cores/Spectrum/control_enable_options.v index d1f3be9..a12437d 100644 --- a/cores/Spectrum/control_enable_options.v +++ b/cores/Spectrum/control_enable_options.v @@ -1,4 +1,6 @@ `timescale 1ns / 1ps +`default_nettype none + ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/cores/Spectrum/coreid.v b/cores/Spectrum/coreid.v index 06b5ec3..390643b 100644 --- a/cores/Spectrum/coreid.v +++ b/cores/Spectrum/coreid.v @@ -39,8 +39,8 @@ module coreid ( text[ 1] = "2"; text[ 2] = "1"; text[ 3] = "-"; - text[ 4] = "0"; - text[ 5] = "5"; + text[ 4] = "1"; + text[ 5] = "7"; text[ 6] = "0"; text[ 7] = "5"; text[ 8] = "2"; diff --git a/cores/Spectrum/cuatro_relojes.v b/cores/Spectrum/cuatro_relojes.v index 780f79e..cb043d8 100644 --- a/cores/Spectrum/cuatro_relojes.v +++ b/cores/Spectrum/cuatro_relojes.v @@ -16,10 +16,16 @@ module clock_generator output wire CLK_OUT4, output wire cpuclk ); + + wire clkin1_buffered; + IBUFG BUFG_IN ( + .O(clkin1_buffered), + .I(CLK_IN1) + ); reg [2:0] pll_option_stored = 3'b000; reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot - always @(posedge CLK_IN1) begin + always @(posedge clkin1_buffered) begin if (pll_option != pll_option_stored) begin pll_option_stored <= pll_option; pulso_reconf <= 8'b00000001; @@ -42,7 +48,7 @@ module clock_generator .RST(1'b0), // CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the // clock for the PLL_DRP module - .CLKIN(CLK_IN1), + .CLKIN(clkin1_buffered), // SRDY pulses for one clock cycle after the PLL_ADV is locked and the // PLL_DRP module is ready to start another re-configuration .SRDY(), @@ -54,58 +60,6 @@ module clock_generator .CLK3OUT(CLK_OUT4) ); -// wire clk28, clk14, clk7, clk3d5, cpuclk_3_2, cpuclk_1_0; -// -// BUFGMUX reloj28_contenido ( -// .O(clk28), -// .I0(CLK_OUT1), -// .I1(1'b1), -// .S(CPUContention) -// ); -// -// BUFGMUX reloj14_contenido ( -// .O(clk14), -// .I0(CLK_OUT2), -// .I1(1'b1), -// .S(CPUContention) -// ); -// -// BUFGMUX reloj7_contenido ( -// .O(clk7), -// .I0(CLK_OUT3), -// .I1(1'b1), -// .S(CPUContention) -// ); -// -// BUFGMUX reloj3d5_contenido ( -// .O(clk3d5), -// .I0(CLK_OUT4), -// .I1(1'b1), -// .S(CPUContention) -// ); -// -// BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU -// .O(cpuclk_3_2), -// .I0(clk14), -// .I1(clk28), -// .S(turbo_enable[0]) -// ); -// -// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU -// .O(cpuclk_1_0), -// .I0(clk3d5), -// .I1(clk7), -// .S(turbo_enable[0]) -// ); -// -// BUFGMUX cpuclk_selector ( -// .O(cpuclk), -// .I0(cpuclk_1_0), -// .I1(cpuclk_3_2), -// .S(turbo_enable[1]) -// ); - - wire cpuclk_selected, cpuclk_3_2, cpuclk_1_0; // BUFGMUX speed_3_and_2 ( // 28MHz and 14MHz for CPU @@ -115,17 +69,43 @@ module clock_generator // .S(turbo_enable[0]) // ); +// BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU +// .O(cpuclk_1_0), +// .I0(CLK_OUT4), +// .I1(CLK_OUT3), +// .S(turbo_enable[0]) +// ); +// +// BUFGMUX cpuclk_selector ( +// .O(cpuclk_selected), +// .I0(cpuclk_1_0), +// .I1(CLK_OUT2), +// .S(turbo_enable[1]) +// ); +// +// BUFGMUX aplicar_contienda ( +// .O(cpuclk), +// .I0(cpuclk_selected), // when no contention, clock is this one +// .I1(1'b1), // during contention, clock is pulled up +// .S(CPUContention) // contention signal +// ); + + + reg [2:0] clkdivider = 3'b000; + always @(posedge CLK_OUT1) + clkdivider <= clkdivider + 3'd1; + BUFGMUX speed_1_and_0 ( // 7MHz and 3.5MHz for CPU .O(cpuclk_1_0), - .I0(CLK_OUT4), - .I1(CLK_OUT3), + .I0(clkdivider[2]), + .I1(clkdivider[1]), .S(turbo_enable[0]) ); BUFGMUX cpuclk_selector ( .O(cpuclk_selected), .I0(cpuclk_1_0), - .I1(CLK_OUT2), + .I1(clkdivider[0]), .S(turbo_enable[1]) ); diff --git a/cores/Spectrum/initial_bootscreen.hex b/cores/Spectrum/initial_bootscreen.hex new file mode 100644 index 0000000..41db425 --- /dev/null +++ b/cores/Spectrum/initial_bootscreen.hex @@ -0,0 +1,6912 @@ +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 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(!a[1] && a[15:14]==2'b01) +`define ADDR_7FFD_SP128 (!a[1] && !a[15]) +`define ADDR_1FFD (!a[1] && a[15:12]==4'b0001) `define ADDR_TIMEX_MMU (a[7:0] == 8'hF4) `define PAGE0 3'b000 @@ -184,7 +186,7 @@ module new_memory ( wire puerto_bloqueado = bank128[5]; wire [2:0] banco_ram = bank128[2:0]; wire vrampage = bank128[3]; - wire [1:0] banco_rom = {bankplus3[2] & ~disable_romsel1f, bank128[4] & ~disable_romsel7f}; + wire [1:0] banco_rom = {bankplus3[2] & (~disable_romsel1f), bank128[4] & (~disable_romsel7f)}; wire amstrad_allram_page_mode = bankplus3[0]; wire [1:0] plus3_memory_arrangement = bankplus3[2:1]; @@ -194,14 +196,18 @@ module new_memory ( bankplus3 <= 8'h00; timex_mmu <= 8'h00; end - else if (!disable_1ffd && !iorq_n && !wr_n && `ADDR_1FFD && !puerto_bloqueado) - bankplus3 <= din; - else if (!disable_7ffd && disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_SP128 && !puerto_bloqueado) - bank128 <= din; - else if (!disable_7ffd && !disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_PLUS2A && !puerto_bloqueado) - bank128 <= din; - else if (enable_timexmmu && !iorq_n && !wr_n && `ADDR_TIMEX_MMU) - timex_mmu <= din; + else begin + if (!disable_1ffd && !disable_7ffd) begin + if (!iorq_n && !wr_n && `ADDR_1FFD && !puerto_bloqueado) + bankplus3 <= din; + if (!iorq_n && !wr_n && `ADDR_7FFD_PLUS2A && !puerto_bloqueado) + bank128 <= din; + end + if (!disable_7ffd && disable_1ffd && !iorq_n && !wr_n && `ADDR_7FFD_SP128 && !puerto_bloqueado) + bank128 <= din; + if (enable_timexmmu && !iorq_n && !wr_n && `ADDR_TIMEX_MMU) + timex_mmu <= din; + end end reg [18:0] addr_port2; @@ -444,7 +450,7 @@ module new_memory ( endmodule module sram_and_mirror ( - input wire clk, // 28MHz or higher if possible + input wire clk, // 28MHz input wire [14:0] a1, // to BRAM addr bus input wire [18:0] a2, // to SRAM addr bus input wire we2_n, // to SRAM WE enable @@ -478,6 +484,6 @@ module sram_and_mirror ( assign a = a2; assign we_n = we2_n; assign dout2 = d; - assign d = (we2_n == 1'b0)? din2 : 8'hZZ; + assign d = (we_n == 1'b0)? din2 : 8'hZZ; endmodule diff --git a/cores/Spectrum/pll_drp.v b/cores/Spectrum/pll_drp.v index 9a305bd..41be9f7 100644 --- a/cores/Spectrum/pll_drp.v +++ b/cores/Spectrum/pll_drp.v @@ -29,10 +29,10 @@ // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES // OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR // PURPOSE. -// +// // (c) Copyright 2008 Xilinx, Inc. // All rights reserved. -// +// /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps @@ -46,7 +46,7 @@ module pll_drp // 50 Hz, Salida RGB/VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -59,16 +59,16 @@ module pll_drp parameter S1_CLKFBOUT_MULT = 9, parameter S1_CLKFBOUT_PHASE = 0, - // The bandwidth parameter effects the phase error and the jitter filter + // The bandwidth parameter effects the phase error and the jitter filter // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S1_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S1_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -108,7 +108,7 @@ module pll_drp // State 2 Parameters - These are for the second reconfiguration state. // 51 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -125,12 +125,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S2_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S2_DIVCLK_DIVIDE = 1, - - // The following parameters describe the configuration that each clock + + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -139,21 +139,21 @@ module pll_drp // _PHASE: This is the phase multiplied by 1000. For example if // a phase of 24.567 deg was desired the input value would be // 24567. The range for the phase is from -360000 to 360000 - // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // _DUTY: This is the duty cycle multiplied by 100,000. For example if // a duty cycle of .24567 was desired the input would be // 24567. parameter S2_CLKOUT0_DIVIDE = 14, parameter S2_CLKOUT0_PHASE = 0, parameter S2_CLKOUT0_DUTY = 50000, - + parameter S2_CLKOUT1_DIVIDE = 28, parameter S2_CLKOUT1_PHASE = 0, parameter S2_CLKOUT1_DUTY = 50000, - + parameter S2_CLKOUT2_DIVIDE = 56, parameter S2_CLKOUT2_PHASE = 0, parameter S2_CLKOUT2_DUTY = 50000, - + parameter S2_CLKOUT3_DIVIDE = 112, parameter S2_CLKOUT3_PHASE = 0, parameter S2_CLKOUT3_DUTY = 50000, @@ -170,7 +170,7 @@ module pll_drp // State 3 Parameters - These are for the second reconfiguration state. // 53.50 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -187,12 +187,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S3_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S3_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -232,7 +232,7 @@ module pll_drp // State 4 Parameters - These are for the second reconfiguration state. // 55.80 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -249,12 +249,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S4_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S4_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -294,7 +294,7 @@ module pll_drp // State 5 Parameters - These are for the second reconfiguration state. // 57.39 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -311,12 +311,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S5_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S5_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -356,7 +356,7 @@ module pll_drp // State 6 Parameters - These are for the second reconfiguration state. // 59.52 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -373,12 +373,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S6_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S6_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -418,7 +418,7 @@ module pll_drp // State 7 Parameters - These are for the second reconfiguration state. // 61.8 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -435,12 +435,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S7_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S7_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -480,7 +480,7 @@ module pll_drp // State 8 Parameters - These are for the second reconfiguration state. // 63.77 Hz, Salida VGA //*********************************************************************** - // These parameters have an effect on the feedback path. A change on + // These parameters have an effect on the feedback path. A change on // these parameters will effect all of the clock outputs. // // The paramaters are composed of: @@ -497,12 +497,12 @@ module pll_drp // capability of the MMCM. For more information on this parameter see the // Device user guide. parameter S8_BANDWIDTH = "LOW", - // The divclk parameter allows th einput clock to be divided before it + // The divclk parameter allows th einput clock to be divided before it // reaches the phase and frequency comparitor. This can be set between // 1 and 128. parameter S8_DIVCLK_DIVIDE = 1, - // The following parameters describe the configuration that each clock + // The following parameters describe the configuration that each clock // output should have once the reconfiguration for state one has // completed. // @@ -580,84 +580,84 @@ module pll_drp // Integer used to initialize remainder of unused ROM integer ii; - + // Pass SCLK to DCLK for the PLL assign DCLK = SCLK; // include the PLL reconfiguration functions. This contains the constant // functions that are used in the calculations below. This file is // required. `include "pll_drp_func.h" - + //************************************************************************** // State 1 Calculations //************************************************************************** localparam [22:0] S1_CLKFBOUT = s6_pll_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000); - + localparam [22:0] S1_CLKFBOUT2 = s6_pll_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000); - - localparam [9:0] S1_DIGITAL_FILT = + + localparam [9:0] S1_DIGITAL_FILT = s6_pll_filter_lookup(S1_CLKFBOUT_MULT, S1_BANDWIDTH); - + localparam [39:0] S1_LOCK = s6_pll_lock_lookup(S1_CLKFBOUT_MULT); - - localparam [22:0] S1_DIVCLK = - s6_pll_count_calc(S1_DIVCLK_DIVIDE, 0, 50000); - + + localparam [22:0] S1_DIVCLK = + s6_pll_count_calc(S1_DIVCLK_DIVIDE, 0, 50000); + localparam [22:0] S1_CLKOUT0 = - s6_pll_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, S1_CLKOUT0_DUTY); - - localparam [22:0] S1_CLKOUT1 = - s6_pll_count_calc(S1_CLKOUT1_DIVIDE, S1_CLKOUT1_PHASE, S1_CLKOUT1_DUTY); - - localparam [22:0] S1_CLKOUT2 = - s6_pll_count_calc(S1_CLKOUT2_DIVIDE, S1_CLKOUT2_PHASE, S1_CLKOUT2_DUTY); - - localparam [22:0] S1_CLKOUT3 = - s6_pll_count_calc(S1_CLKOUT3_DIVIDE, S1_CLKOUT3_PHASE, S1_CLKOUT3_DUTY); - - localparam [22:0] S1_CLKOUT4 = - s6_pll_count_calc(S1_CLKOUT4_DIVIDE, S1_CLKOUT4_PHASE, S1_CLKOUT4_DUTY); - - localparam [22:0] S1_CLKOUT5 = - s6_pll_count_calc(S1_CLKOUT5_DIVIDE, S1_CLKOUT5_PHASE, S1_CLKOUT5_DUTY); - + s6_pll_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, S1_CLKOUT0_DUTY); + + localparam [22:0] S1_CLKOUT1 = + s6_pll_count_calc(S1_CLKOUT1_DIVIDE, S1_CLKOUT1_PHASE, S1_CLKOUT1_DUTY); + + localparam [22:0] S1_CLKOUT2 = + s6_pll_count_calc(S1_CLKOUT2_DIVIDE, S1_CLKOUT2_PHASE, S1_CLKOUT2_DUTY); + + localparam [22:0] S1_CLKOUT3 = + s6_pll_count_calc(S1_CLKOUT3_DIVIDE, S1_CLKOUT3_PHASE, S1_CLKOUT3_DUTY); + + localparam [22:0] S1_CLKOUT4 = + s6_pll_count_calc(S1_CLKOUT4_DIVIDE, S1_CLKOUT4_PHASE, S1_CLKOUT4_DUTY); + + localparam [22:0] S1_CLKOUT5 = + s6_pll_count_calc(S1_CLKOUT5_DIVIDE, S1_CLKOUT5_PHASE, S1_CLKOUT5_DUTY); + //************************************************************************** // State 2 Calculations //************************************************************************** - localparam [22:0] S2_CLKFBOUT = + localparam [22:0] S2_CLKFBOUT = s6_pll_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000); - - localparam [22:0] S2_CLKFBOUT2 = + + localparam [22:0] S2_CLKFBOUT2 = s6_pll_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000); - - localparam [9:0] S2_DIGITAL_FILT = + + localparam [9:0] S2_DIGITAL_FILT = s6_pll_filter_lookup(S2_CLKFBOUT_MULT, S2_BANDWIDTH); - - localparam [39:0] S2_LOCK = + + localparam [39:0] S2_LOCK = s6_pll_lock_lookup(S2_CLKFBOUT_MULT); - - localparam [22:0] S2_DIVCLK = + + localparam [22:0] S2_DIVCLK = s6_pll_count_calc(S2_DIVCLK_DIVIDE, 0, 50000); - - localparam [22:0] S2_CLKOUT0 = + + localparam [22:0] S2_CLKOUT0 = s6_pll_count_calc(S2_CLKOUT0_DIVIDE, S2_CLKOUT0_PHASE, S2_CLKOUT0_DUTY); - localparam [22:0] S2_CLKOUT1 = + localparam [22:0] S2_CLKOUT1 = s6_pll_count_calc(S2_CLKOUT1_DIVIDE, S2_CLKOUT1_PHASE, S2_CLKOUT1_DUTY); - - localparam [22:0] S2_CLKOUT2 = + + localparam [22:0] S2_CLKOUT2 = s6_pll_count_calc(S2_CLKOUT2_DIVIDE, S2_CLKOUT2_PHASE, S2_CLKOUT2_DUTY); - - localparam [22:0] S2_CLKOUT3 = + + localparam [22:0] S2_CLKOUT3 = s6_pll_count_calc(S2_CLKOUT3_DIVIDE, S2_CLKOUT3_PHASE, S2_CLKOUT3_DUTY); - - localparam [22:0] S2_CLKOUT4 = + + localparam [22:0] S2_CLKOUT4 = s6_pll_count_calc(S2_CLKOUT4_DIVIDE, S2_CLKOUT4_PHASE, S2_CLKOUT4_DUTY); - - localparam [22:0] S2_CLKOUT5 = + + localparam [22:0] S2_CLKOUT5 = s6_pll_count_calc(S2_CLKOUT5_DIVIDE, S2_CLKOUT5_PHASE, S2_CLKOUT5_DUTY); //************************************************************************** @@ -881,644 +881,644 @@ module pll_drp //*********************************************************************** // State 1 Initialization //*********************************************************************** - + rom[0] = {5'h05, 16'h50FF, S1_CLKOUT0[19], 1'b0, S1_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S1_CLKOUT0[16], S1_CLKOUT0[17], S1_CLKOUT0[15], S1_CLKOUT0[14], 8'h00};//bits 11 downto 0 - - rom[1] = {5'h06, 16'h010B, S1_CLKOUT1[4], S1_CLKOUT1[5], S1_CLKOUT1[3], S1_CLKOUT1[12], //bits 15 down to 12 - S1_CLKOUT1[1], S1_CLKOUT1[2], S1_CLKOUT1[19], 1'b0, S1_CLKOUT1[17], S1_CLKOUT1[16], //bits 11 down to 6 - S1_CLKOUT1[14], S1_CLKOUT1[15], 1'b0, S1_CLKOUT0[13], 2'b00}; //bits 5 down to 0 - - rom[2] = {5'h07, 16'hE02C, 3'b000, S1_CLKOUT1[11], S1_CLKOUT1[9], S1_CLKOUT1[10], //bits 15 down to 10 - S1_CLKOUT1[8], S1_CLKOUT1[7], S1_CLKOUT1[6], S1_CLKOUT1[20], 1'b0, S1_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S1_CLKOUT1[21], S1_CLKOUT1[22]}; //bits 3 down to 0 - - rom[3] = {5'h08, 16'h4001, S1_CLKOUT2[22], 1'b0, S1_CLKOUT2[5], S1_CLKOUT2[21], //bits 15 downto 12 - S1_CLKOUT2[12], S1_CLKOUT2[4], S1_CLKOUT2[3], S1_CLKOUT2[2], S1_CLKOUT2[0], S1_CLKOUT2[19], //bits 11 down to 6 - S1_CLKOUT2[17], S1_CLKOUT2[18], S1_CLKOUT2[15], S1_CLKOUT2[16], S1_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - - rom[4] = {5'h09, 16'h0D03, S1_CLKOUT3[14], S1_CLKOUT3[15], S1_CLKOUT0[21], S1_CLKOUT0[22], 2'b00, S1_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S1_CLKOUT2[9], S1_CLKOUT2[8], S1_CLKOUT2[6], S1_CLKOUT2[7], S1_CLKOUT2[13], S1_CLKOUT2[20], 2'b00}; //bits 7 downto 0 - - rom[5] = {5'h0A, 16'hB001, 1'b0, S1_CLKOUT3[13], 2'b00, S1_CLKOUT3[21], S1_CLKOUT3[22], S1_CLKOUT3[5], S1_CLKOUT3[4], //bits 15 downto 8 - S1_CLKOUT3[12], S1_CLKOUT3[2], S1_CLKOUT3[0], S1_CLKOUT3[1], S1_CLKOUT3[18], S1_CLKOUT3[19], //bits 7 downto 2 - S1_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - - rom[6] = {5'h0B, 16'h0110, S1_CLKOUT0[5], S1_CLKOUT4[19], S1_CLKOUT4[14], S1_CLKOUT4[17], //bits 15 downto 12 - S1_CLKOUT4[15], S1_CLKOUT4[16], S1_CLKOUT0[4], 1'b0, S1_CLKOUT3[11], S1_CLKOUT3[10], //bits 11 downto 6 - S1_CLKOUT3[9], 1'b0, S1_CLKOUT3[7], S1_CLKOUT3[8], S1_CLKOUT3[20], S1_CLKOUT3[6]}; //bits 5 downto 0 - - rom[7] = {5'h0C, 16'h0B00, S1_CLKOUT4[7], S1_CLKOUT4[8], S1_CLKOUT4[20], S1_CLKOUT4[6], 1'b0, S1_CLKOUT4[13], //bits 15 downto 10 - 2'b00, S1_CLKOUT4[22], S1_CLKOUT4[21], S1_CLKOUT4[4], S1_CLKOUT4[5], S1_CLKOUT4[3], //bits 9 downto 3 - S1_CLKOUT4[12], S1_CLKOUT4[1], S1_CLKOUT4[2]}; //bits 2 downto 0 - - rom[8] = {5'h0D, 16'h0008, S1_CLKOUT5[2], S1_CLKOUT5[3], S1_CLKOUT5[0], S1_CLKOUT5[1], S1_CLKOUT5[18], //bits 15 downto 11 - S1_CLKOUT5[19], S1_CLKOUT5[17], S1_CLKOUT5[16], S1_CLKOUT5[15], S1_CLKOUT0[3], //bits 10 downto 6 - S1_CLKOUT0[0], S1_CLKOUT0[2], 1'b0, S1_CLKOUT4[11], S1_CLKOUT4[9], S1_CLKOUT4[10]}; //bits 5 downto 0 - - rom[9] = {5'h0E, 16'h00D0, S1_CLKOUT5[10], S1_CLKOUT5[11], S1_CLKOUT5[8], S1_CLKOUT5[9], S1_CLKOUT5[6], //bits 15 downto 11 - S1_CLKOUT5[7], S1_CLKOUT5[20], S1_CLKOUT5[13], 2'b00, S1_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S1_CLKOUT5[5], S1_CLKOUT5[21], S1_CLKOUT5[12], S1_CLKOUT5[4]}; //bits 3 downto 0 - - rom[10] = {5'h0F, 16'h0003, S1_CLKFBOUT[4], S1_CLKFBOUT[5], S1_CLKFBOUT[3], S1_CLKFBOUT[12], S1_CLKFBOUT[1], //bits 15 downto 11 - S1_CLKFBOUT[2], S1_CLKFBOUT[0], S1_CLKFBOUT[19], S1_CLKFBOUT[18], S1_CLKFBOUT[17], //bits 10 downto 6 - S1_CLKFBOUT[15], S1_CLKFBOUT[16], S1_CLKOUT0[12], S1_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - - rom[11] = {5'h10, 16'h800C, 1'b0, S1_CLKOUT0[9], S1_CLKOUT0[11], S1_CLKOUT0[10], S1_CLKFBOUT[10], S1_CLKFBOUT[11], //bits 15 downto 10 - S1_CLKFBOUT[9], S1_CLKFBOUT[8], S1_CLKFBOUT[7], S1_CLKFBOUT[6], S1_CLKFBOUT[13], //bits 9 downto 5 - S1_CLKFBOUT[20], 2'b00, S1_CLKFBOUT[21], S1_CLKFBOUT[22]}; //bits 4 downto 0 - - rom[12] = {5'h11, 16'hFC00, 6'h00, S1_CLKOUT3[3], S1_CLKOUT3[16], S1_CLKOUT2[11], S1_CLKOUT2[1], S1_CLKOUT1[18], //bits 15 downto 6 - S1_CLKOUT1[0], S1_CLKOUT0[6], S1_CLKOUT0[20], S1_CLKOUT0[8], S1_CLKOUT0[7]}; //bits 5 downto 0 - - rom[13] = {5'h12, 16'hF0FF, 4'h0, S1_CLKOUT5[14], S1_CLKFBOUT[14], S1_CLKOUT4[0], S1_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - - rom[14] = {5'h13, 16'h5120, S1_DIVCLK[11], 1'b0, S1_DIVCLK[10], 1'b0, S1_DIVCLK[7], S1_DIVCLK[8], //bits 15 downto 10 - S1_DIVCLK[0], 1'b0, S1_DIVCLK[5], S1_DIVCLK[2], 1'b0, S1_DIVCLK[13], 4'h0}; //bits 9 downto 0 - - rom[15] = {5'h14, 16'h2FFF, S1_LOCK[1], S1_LOCK[2], 1'b0, S1_LOCK[0], 12'h000}; //bits 15 downto 0 - - rom[16] = {5'h15, 16'hBFF4, 1'b0, S1_DIVCLK[12], 10'h000, S1_LOCK[38], 1'b0, S1_LOCK[32], S1_LOCK[39]}; //bits 15 downto 0 - - rom[17] = {5'h16, 16'h0A55, S1_LOCK[15], S1_LOCK[13], S1_LOCK[27], S1_LOCK[16], 1'b0, S1_LOCK[10], //bits 15 downto 10 - 1'b0, S1_DIVCLK[9], S1_DIVCLK[1], 1'b0, S1_DIVCLK[6], 1'b0, S1_DIVCLK[3], //bits 9 downto 3 - 1'b0, S1_DIVCLK[4], 1'b0}; //bits 2 downto 0 - - rom[18] = {5'h17, 16'hFFD0, 10'h000, S1_LOCK[17], 1'b0, S1_LOCK[8], S1_LOCK[9], S1_LOCK[23], S1_LOCK[22]}; //bits 15 downto 0 - - rom[19] = {5'h18, 16'h1039, S1_DIGITAL_FILT[6], S1_DIGITAL_FILT[7], S1_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S1_DIGITAL_FILT[2], S1_DIGITAL_FILT[1], S1_DIGITAL_FILT[3], S1_DIGITAL_FILT[9], //bits 11 downto 8 - S1_DIGITAL_FILT[8], S1_LOCK[26], 3'h0, S1_LOCK[19], S1_LOCK[18], 1'b0}; //bits 7 downto 0 - - rom[20] = {5'h19, 16'h0000, S1_LOCK[24], S1_LOCK[25], S1_LOCK[21], S1_LOCK[14], S1_LOCK[11], //bits 15 downto 11 - S1_LOCK[12], S1_LOCK[20], S1_LOCK[6], S1_LOCK[35], S1_LOCK[36], //bits 10 downto 6 - S1_LOCK[37], S1_LOCK[3], S1_LOCK[33], S1_LOCK[31], S1_LOCK[34], S1_LOCK[30]}; //bits 5 downto 0 - - rom[21] = {5'h1A, 16'hFFFC, 14'h0000, S1_LOCK[28], S1_LOCK[29]}; //bits 15 downto 0 - - rom[22] = {5'h1D, 16'h2FFF, S1_LOCK[7], S1_LOCK[4], 1'b0, S1_LOCK[5], 12'h000}; //bits 15 downto 0 - + S1_CLKOUT0[16], S1_CLKOUT0[17], S1_CLKOUT0[15], S1_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[1] = {5'h06, 16'h010B, S1_CLKOUT1[4], S1_CLKOUT1[5], S1_CLKOUT1[3], S1_CLKOUT1[12], //bits 15 down to 12 + S1_CLKOUT1[1], S1_CLKOUT1[2], S1_CLKOUT1[19], 1'b0, S1_CLKOUT1[17], S1_CLKOUT1[16], //bits 11 down to 6 + S1_CLKOUT1[14], S1_CLKOUT1[15], 1'b0, S1_CLKOUT0[13], 2'b00}; //bits 5 down to 0 + + rom[2] = {5'h07, 16'hE02C, 3'b000, S1_CLKOUT1[11], S1_CLKOUT1[9], S1_CLKOUT1[10], //bits 15 down to 10 + S1_CLKOUT1[8], S1_CLKOUT1[7], S1_CLKOUT1[6], S1_CLKOUT1[20], 1'b0, S1_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S1_CLKOUT1[21], S1_CLKOUT1[22]}; //bits 3 down to 0 + + rom[3] = {5'h08, 16'h4001, S1_CLKOUT2[22], 1'b0, S1_CLKOUT2[5], S1_CLKOUT2[21], //bits 15 downto 12 + S1_CLKOUT2[12], S1_CLKOUT2[4], S1_CLKOUT2[3], S1_CLKOUT2[2], S1_CLKOUT2[0], S1_CLKOUT2[19], //bits 11 down to 6 + S1_CLKOUT2[17], S1_CLKOUT2[18], S1_CLKOUT2[15], S1_CLKOUT2[16], S1_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[4] = {5'h09, 16'h0D03, S1_CLKOUT3[14], S1_CLKOUT3[15], S1_CLKOUT0[21], S1_CLKOUT0[22], 2'b00, S1_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S1_CLKOUT2[9], S1_CLKOUT2[8], S1_CLKOUT2[6], S1_CLKOUT2[7], S1_CLKOUT2[13], S1_CLKOUT2[20], 2'b00}; //bits 7 downto 0 + + rom[5] = {5'h0A, 16'hB001, 1'b0, S1_CLKOUT3[13], 2'b00, S1_CLKOUT3[21], S1_CLKOUT3[22], S1_CLKOUT3[5], S1_CLKOUT3[4], //bits 15 downto 8 + S1_CLKOUT3[12], S1_CLKOUT3[2], S1_CLKOUT3[0], S1_CLKOUT3[1], S1_CLKOUT3[18], S1_CLKOUT3[19], //bits 7 downto 2 + S1_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[6] = {5'h0B, 16'h0110, S1_CLKOUT0[5], S1_CLKOUT4[19], S1_CLKOUT4[14], S1_CLKOUT4[17], //bits 15 downto 12 + S1_CLKOUT4[15], S1_CLKOUT4[16], S1_CLKOUT0[4], 1'b0, S1_CLKOUT3[11], S1_CLKOUT3[10], //bits 11 downto 6 + S1_CLKOUT3[9], 1'b0, S1_CLKOUT3[7], S1_CLKOUT3[8], S1_CLKOUT3[20], S1_CLKOUT3[6]}; //bits 5 downto 0 + + rom[7] = {5'h0C, 16'h0B00, S1_CLKOUT4[7], S1_CLKOUT4[8], S1_CLKOUT4[20], S1_CLKOUT4[6], 1'b0, S1_CLKOUT4[13], //bits 15 downto 10 + 2'b00, S1_CLKOUT4[22], S1_CLKOUT4[21], S1_CLKOUT4[4], S1_CLKOUT4[5], S1_CLKOUT4[3], //bits 9 downto 3 + S1_CLKOUT4[12], S1_CLKOUT4[1], S1_CLKOUT4[2]}; //bits 2 downto 0 + + rom[8] = {5'h0D, 16'h0008, S1_CLKOUT5[2], S1_CLKOUT5[3], S1_CLKOUT5[0], S1_CLKOUT5[1], S1_CLKOUT5[18], //bits 15 downto 11 + S1_CLKOUT5[19], S1_CLKOUT5[17], S1_CLKOUT5[16], S1_CLKOUT5[15], S1_CLKOUT0[3], //bits 10 downto 6 + S1_CLKOUT0[0], S1_CLKOUT0[2], 1'b0, S1_CLKOUT4[11], S1_CLKOUT4[9], S1_CLKOUT4[10]}; //bits 5 downto 0 + + rom[9] = {5'h0E, 16'h00D0, S1_CLKOUT5[10], S1_CLKOUT5[11], S1_CLKOUT5[8], S1_CLKOUT5[9], S1_CLKOUT5[6], //bits 15 downto 11 + S1_CLKOUT5[7], S1_CLKOUT5[20], S1_CLKOUT5[13], 2'b00, S1_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S1_CLKOUT5[5], S1_CLKOUT5[21], S1_CLKOUT5[12], S1_CLKOUT5[4]}; //bits 3 downto 0 + + rom[10] = {5'h0F, 16'h0003, S1_CLKFBOUT[4], S1_CLKFBOUT[5], S1_CLKFBOUT[3], S1_CLKFBOUT[12], S1_CLKFBOUT[1], //bits 15 downto 11 + S1_CLKFBOUT[2], S1_CLKFBOUT[0], S1_CLKFBOUT[19], S1_CLKFBOUT[18], S1_CLKFBOUT[17], //bits 10 downto 6 + S1_CLKFBOUT[15], S1_CLKFBOUT[16], S1_CLKOUT0[12], S1_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[11] = {5'h10, 16'h800C, 1'b0, S1_CLKOUT0[9], S1_CLKOUT0[11], S1_CLKOUT0[10], S1_CLKFBOUT[10], S1_CLKFBOUT[11], //bits 15 downto 10 + S1_CLKFBOUT[9], S1_CLKFBOUT[8], S1_CLKFBOUT[7], S1_CLKFBOUT[6], S1_CLKFBOUT[13], //bits 9 downto 5 + S1_CLKFBOUT[20], 2'b00, S1_CLKFBOUT[21], S1_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[12] = {5'h11, 16'hFC00, 6'h00, S1_CLKOUT3[3], S1_CLKOUT3[16], S1_CLKOUT2[11], S1_CLKOUT2[1], S1_CLKOUT1[18], //bits 15 downto 6 + S1_CLKOUT1[0], S1_CLKOUT0[6], S1_CLKOUT0[20], S1_CLKOUT0[8], S1_CLKOUT0[7]}; //bits 5 downto 0 + + rom[13] = {5'h12, 16'hF0FF, 4'h0, S1_CLKOUT5[14], S1_CLKFBOUT[14], S1_CLKOUT4[0], S1_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[14] = {5'h13, 16'h5120, S1_DIVCLK[11], 1'b0, S1_DIVCLK[10], 1'b0, S1_DIVCLK[7], S1_DIVCLK[8], //bits 15 downto 10 + S1_DIVCLK[0], 1'b0, S1_DIVCLK[5], S1_DIVCLK[2], 1'b0, S1_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[15] = {5'h14, 16'h2FFF, S1_LOCK[1], S1_LOCK[2], 1'b0, S1_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[16] = {5'h15, 16'hBFF4, 1'b0, S1_DIVCLK[12], 10'h000, S1_LOCK[38], 1'b0, S1_LOCK[32], S1_LOCK[39]}; //bits 15 downto 0 + + rom[17] = {5'h16, 16'h0A55, S1_LOCK[15], S1_LOCK[13], S1_LOCK[27], S1_LOCK[16], 1'b0, S1_LOCK[10], //bits 15 downto 10 + 1'b0, S1_DIVCLK[9], S1_DIVCLK[1], 1'b0, S1_DIVCLK[6], 1'b0, S1_DIVCLK[3], //bits 9 downto 3 + 1'b0, S1_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[18] = {5'h17, 16'hFFD0, 10'h000, S1_LOCK[17], 1'b0, S1_LOCK[8], S1_LOCK[9], S1_LOCK[23], S1_LOCK[22]}; //bits 15 downto 0 + + rom[19] = {5'h18, 16'h1039, S1_DIGITAL_FILT[6], S1_DIGITAL_FILT[7], S1_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S1_DIGITAL_FILT[2], S1_DIGITAL_FILT[1], S1_DIGITAL_FILT[3], S1_DIGITAL_FILT[9], //bits 11 downto 8 + S1_DIGITAL_FILT[8], S1_LOCK[26], 3'h0, S1_LOCK[19], S1_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[20] = {5'h19, 16'h0000, S1_LOCK[24], S1_LOCK[25], S1_LOCK[21], S1_LOCK[14], S1_LOCK[11], //bits 15 downto 11 + S1_LOCK[12], S1_LOCK[20], S1_LOCK[6], S1_LOCK[35], S1_LOCK[36], //bits 10 downto 6 + S1_LOCK[37], S1_LOCK[3], S1_LOCK[33], S1_LOCK[31], S1_LOCK[34], S1_LOCK[30]}; //bits 5 downto 0 + + rom[21] = {5'h1A, 16'hFFFC, 14'h0000, S1_LOCK[28], S1_LOCK[29]}; //bits 15 downto 0 + + rom[22] = {5'h1D, 16'h2FFF, S1_LOCK[7], S1_LOCK[4], 1'b0, S1_LOCK[5], 12'h000}; //bits 15 downto 0 + //*********************************************************************** // State 2 Initialization //*********************************************************************** - + rom[23] = {5'h05, 16'h50FF, S2_CLKOUT0[19], 1'b0, S2_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S2_CLKOUT0[16], S2_CLKOUT0[17], S2_CLKOUT0[15], S2_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S2_CLKOUT0[16], S2_CLKOUT0[17], S2_CLKOUT0[15], S2_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[24] = {5'h06, 16'h010B, S2_CLKOUT1[4], S2_CLKOUT1[5], S2_CLKOUT1[3], S2_CLKOUT1[12], //bits 15 down to 12 + S2_CLKOUT1[1], S2_CLKOUT1[2], S2_CLKOUT1[19], 1'b0, S2_CLKOUT1[17], S2_CLKOUT1[16], //bits 11 down to 6 + S2_CLKOUT1[14], S2_CLKOUT1[15], 1'b0, S2_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[25] = {5'h07, 16'hE02C, 3'h0, S2_CLKOUT1[11], S2_CLKOUT1[9], S2_CLKOUT1[10], //bits 15 down to 10 + S2_CLKOUT1[8], S2_CLKOUT1[7], S2_CLKOUT1[6], S2_CLKOUT1[20], 1'b0, S2_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S2_CLKOUT1[21], S2_CLKOUT1[22]}; //bits 3 down to 0 + + rom[26] = {5'h08, 16'h4001, S2_CLKOUT2[22], 1'b0, S2_CLKOUT2[5], S2_CLKOUT2[21], //bits 15 downto 12 + S2_CLKOUT2[12], S2_CLKOUT2[4], S2_CLKOUT2[3], S2_CLKOUT2[2], S2_CLKOUT2[0], S2_CLKOUT2[19], //bits 11 down to 6 + S2_CLKOUT2[17], S2_CLKOUT2[18], S2_CLKOUT2[15], S2_CLKOUT2[16], S2_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[27] = {5'h09, 16'h0D03, S2_CLKOUT3[14], S2_CLKOUT3[15], S2_CLKOUT0[21], S2_CLKOUT0[22], 2'h0, S2_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S2_CLKOUT2[9], S2_CLKOUT2[8], S2_CLKOUT2[6], S2_CLKOUT2[7], S2_CLKOUT2[13], S2_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[28] = {5'h0A, 16'hB001, 1'b0, S2_CLKOUT3[13], 2'h0, S2_CLKOUT3[21], S2_CLKOUT3[22], S2_CLKOUT3[5], S2_CLKOUT3[4], //bits 15 downto 8 + S2_CLKOUT3[12], S2_CLKOUT3[2], S2_CLKOUT3[0], S2_CLKOUT3[1], S2_CLKOUT3[18], S2_CLKOUT3[19], //bits 7 downto 2 + S2_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[29] = {5'h0B, 16'h0110, S2_CLKOUT0[5], S2_CLKOUT4[19], S2_CLKOUT4[14], S2_CLKOUT4[17], //bits 15 downto 12 + S2_CLKOUT4[15], S2_CLKOUT4[16], S2_CLKOUT0[4], 1'b0, S2_CLKOUT3[11], S2_CLKOUT3[10], //bits 11 downto 6 + S2_CLKOUT3[9], 1'b0, S2_CLKOUT3[7], S2_CLKOUT3[8], S2_CLKOUT3[20], S2_CLKOUT3[6]}; //bits 5 downto 0 + + rom[30] = {5'h0C, 16'h0B00, S2_CLKOUT4[7], S2_CLKOUT4[8], S2_CLKOUT4[20], S2_CLKOUT4[6], 1'b0, S2_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S2_CLKOUT4[22], S2_CLKOUT4[21], S2_CLKOUT4[4], S2_CLKOUT4[5], S2_CLKOUT4[3], //bits 9 downto 3 + S2_CLKOUT4[12], S2_CLKOUT4[1], S2_CLKOUT4[2]}; //bits 2 downto 0 + + rom[31] = {5'h0D, 16'h0008, S2_CLKOUT5[2], S2_CLKOUT5[3], S2_CLKOUT5[0], S2_CLKOUT5[1], S2_CLKOUT5[18], //bits 15 downto 11 + S2_CLKOUT5[19], S2_CLKOUT5[17], S2_CLKOUT5[16], S2_CLKOUT5[15], S2_CLKOUT0[3], //bits 10 downto 6 + S2_CLKOUT0[0], S2_CLKOUT0[2], 1'b0, S2_CLKOUT4[11], S2_CLKOUT4[9], S2_CLKOUT4[10]}; //bits 5 downto 0 + + rom[32] = {5'h0E, 16'h00D0, S2_CLKOUT5[10], S2_CLKOUT5[11], S2_CLKOUT5[8], S2_CLKOUT5[9], S2_CLKOUT5[6], //bits 15 downto 11 + S2_CLKOUT5[7], S2_CLKOUT5[20], S2_CLKOUT5[13], 2'h0, S2_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S2_CLKOUT5[5], S2_CLKOUT5[21], S2_CLKOUT5[12], S2_CLKOUT5[4]}; //bits 3 downto 0 + + rom[33] = {5'h0F, 16'h0003, S2_CLKFBOUT[4], S2_CLKFBOUT[5], S2_CLKFBOUT[3], S2_CLKFBOUT[12], S2_CLKFBOUT[1], //bits 15 downto 11 + S2_CLKFBOUT[2], S2_CLKFBOUT[0], S2_CLKFBOUT[19], S2_CLKFBOUT[18], S2_CLKFBOUT[17], //bits 10 downto 6 + S2_CLKFBOUT[15], S2_CLKFBOUT[16], S2_CLKOUT0[12], S2_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[34] = {5'h10, 16'h800C, 1'b0, S2_CLKOUT0[9], S2_CLKOUT0[11], S2_CLKOUT0[10], S2_CLKFBOUT[10], S2_CLKFBOUT[11], //bits 15 downto 10 + S2_CLKFBOUT[9], S2_CLKFBOUT[8], S2_CLKFBOUT[7], S2_CLKFBOUT[6], S2_CLKFBOUT[13], //bits 9 downto 5 + S2_CLKFBOUT[20], 2'h0, S2_CLKFBOUT[21], S2_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[35] = {5'h11, 16'hFC00, 6'h00, S2_CLKOUT3[3], S2_CLKOUT3[16], S2_CLKOUT2[11], S2_CLKOUT2[1], S2_CLKOUT1[18], //bits 15 downto 6 + S2_CLKOUT1[0], S2_CLKOUT0[6], S2_CLKOUT0[20], S2_CLKOUT0[8], S2_CLKOUT0[7]}; //bits 5 downto 0 + + rom[36] = {5'h12, 16'hF0FF, 4'h0, S2_CLKOUT5[14], S2_CLKFBOUT[14], S2_CLKOUT4[0], S2_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[24] = {5'h06, 16'h010B, S2_CLKOUT1[4], S2_CLKOUT1[5], S2_CLKOUT1[3], S2_CLKOUT1[12], //bits 15 down to 12 - S2_CLKOUT1[1], S2_CLKOUT1[2], S2_CLKOUT1[19], 1'b0, S2_CLKOUT1[17], S2_CLKOUT1[16], //bits 11 down to 6 - S2_CLKOUT1[14], S2_CLKOUT1[15], 1'b0, S2_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[37] = {5'h13, 16'h5120, S2_DIVCLK[11], 1'b0, S2_DIVCLK[10], 1'b0, S2_DIVCLK[7], S2_DIVCLK[8], //bits 15 downto 10 + S2_DIVCLK[0], 1'b0, S2_DIVCLK[5], S2_DIVCLK[2], 1'b0, S2_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[38] = {5'h14, 16'h2FFF, S2_LOCK[1], S2_LOCK[2], 1'b0, S2_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[39] = {5'h15, 16'hBFF4, 1'b0, S2_DIVCLK[12], 10'h000, S2_LOCK[38], 1'b0, S2_LOCK[32], S2_LOCK[39]}; //bits 15 downto 0 + + rom[40] = {5'h16, 16'h0A55, S2_LOCK[15], S2_LOCK[13], S2_LOCK[27], S2_LOCK[16], 1'b0, S2_LOCK[10], //bits 15 downto 10 + 1'b0, S2_DIVCLK[9], S2_DIVCLK[1], 1'b0, S2_DIVCLK[6], 1'b0, S2_DIVCLK[3], //bits 9 downto 3 + 1'b0, S2_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[41] = {5'h17, 16'hFFD0, 10'h000, S2_LOCK[17], 1'b0, S2_LOCK[8], S2_LOCK[9], S2_LOCK[23], S2_LOCK[22]}; //bits 15 downto 0 + + rom[42] = {5'h18, 16'h1039, S2_DIGITAL_FILT[6], S2_DIGITAL_FILT[7], S2_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S2_DIGITAL_FILT[2], S2_DIGITAL_FILT[1], S2_DIGITAL_FILT[3], S2_DIGITAL_FILT[9], //bits 11 downto 8 + S2_DIGITAL_FILT[8], S2_LOCK[26], 3'h0, S2_LOCK[19], S2_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[25] = {5'h07, 16'hE02C, 3'h0, S2_CLKOUT1[11], S2_CLKOUT1[9], S2_CLKOUT1[10], //bits 15 down to 10 - S2_CLKOUT1[8], S2_CLKOUT1[7], S2_CLKOUT1[6], S2_CLKOUT1[20], 1'b0, S2_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S2_CLKOUT1[21], S2_CLKOUT1[22]}; //bits 3 down to 0 + rom[43] = {5'h19, 16'h0000, S2_LOCK[24], S2_LOCK[25], S2_LOCK[21], S2_LOCK[14], S2_LOCK[11], //bits 15 downto 11 + S2_LOCK[12], S2_LOCK[20], S2_LOCK[6], S2_LOCK[35], S2_LOCK[36], //bits 10 downto 6 + S2_LOCK[37], S2_LOCK[3], S2_LOCK[33], S2_LOCK[31], S2_LOCK[34], S2_LOCK[30]}; //bits 5 downto 0 - rom[26] = {5'h08, 16'h4001, S2_CLKOUT2[22], 1'b0, S2_CLKOUT2[5], S2_CLKOUT2[21], //bits 15 downto 12 - S2_CLKOUT2[12], S2_CLKOUT2[4], S2_CLKOUT2[3], S2_CLKOUT2[2], S2_CLKOUT2[0], S2_CLKOUT2[19], //bits 11 down to 6 - S2_CLKOUT2[17], S2_CLKOUT2[18], S2_CLKOUT2[15], S2_CLKOUT2[16], S2_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[44] = {5'h1A, 16'hFFFC, 14'h0000, S2_LOCK[28], S2_LOCK[29]}; //bits 15 downto 0 - rom[27] = {5'h09, 16'h0D03, S2_CLKOUT3[14], S2_CLKOUT3[15], S2_CLKOUT0[21], S2_CLKOUT0[22], 2'h0, S2_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S2_CLKOUT2[9], S2_CLKOUT2[8], S2_CLKOUT2[6], S2_CLKOUT2[7], S2_CLKOUT2[13], S2_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - - rom[28] = {5'h0A, 16'hB001, 1'b0, S2_CLKOUT3[13], 2'h0, S2_CLKOUT3[21], S2_CLKOUT3[22], S2_CLKOUT3[5], S2_CLKOUT3[4], //bits 15 downto 8 - S2_CLKOUT3[12], S2_CLKOUT3[2], S2_CLKOUT3[0], S2_CLKOUT3[1], S2_CLKOUT3[18], S2_CLKOUT3[19], //bits 7 downto 2 - S2_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - - rom[29] = {5'h0B, 16'h0110, S2_CLKOUT0[5], S2_CLKOUT4[19], S2_CLKOUT4[14], S2_CLKOUT4[17], //bits 15 downto 12 - S2_CLKOUT4[15], S2_CLKOUT4[16], S2_CLKOUT0[4], 1'b0, S2_CLKOUT3[11], S2_CLKOUT3[10], //bits 11 downto 6 - S2_CLKOUT3[9], 1'b0, S2_CLKOUT3[7], S2_CLKOUT3[8], S2_CLKOUT3[20], S2_CLKOUT3[6]}; //bits 5 downto 0 - - rom[30] = {5'h0C, 16'h0B00, S2_CLKOUT4[7], S2_CLKOUT4[8], S2_CLKOUT4[20], S2_CLKOUT4[6], 1'b0, S2_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S2_CLKOUT4[22], S2_CLKOUT4[21], S2_CLKOUT4[4], S2_CLKOUT4[5], S2_CLKOUT4[3], //bits 9 downto 3 - S2_CLKOUT4[12], S2_CLKOUT4[1], S2_CLKOUT4[2]}; //bits 2 downto 0 - - rom[31] = {5'h0D, 16'h0008, S2_CLKOUT5[2], S2_CLKOUT5[3], S2_CLKOUT5[0], S2_CLKOUT5[1], S2_CLKOUT5[18], //bits 15 downto 11 - S2_CLKOUT5[19], S2_CLKOUT5[17], S2_CLKOUT5[16], S2_CLKOUT5[15], S2_CLKOUT0[3], //bits 10 downto 6 - S2_CLKOUT0[0], S2_CLKOUT0[2], 1'b0, S2_CLKOUT4[11], S2_CLKOUT4[9], S2_CLKOUT4[10]}; //bits 5 downto 0 - - rom[32] = {5'h0E, 16'h00D0, S2_CLKOUT5[10], S2_CLKOUT5[11], S2_CLKOUT5[8], S2_CLKOUT5[9], S2_CLKOUT5[6], //bits 15 downto 11 - S2_CLKOUT5[7], S2_CLKOUT5[20], S2_CLKOUT5[13], 2'h0, S2_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S2_CLKOUT5[5], S2_CLKOUT5[21], S2_CLKOUT5[12], S2_CLKOUT5[4]}; //bits 3 downto 0 - - rom[33] = {5'h0F, 16'h0003, S2_CLKFBOUT[4], S2_CLKFBOUT[5], S2_CLKFBOUT[3], S2_CLKFBOUT[12], S2_CLKFBOUT[1], //bits 15 downto 11 - S2_CLKFBOUT[2], S2_CLKFBOUT[0], S2_CLKFBOUT[19], S2_CLKFBOUT[18], S2_CLKFBOUT[17], //bits 10 downto 6 - S2_CLKFBOUT[15], S2_CLKFBOUT[16], S2_CLKOUT0[12], S2_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - - rom[34] = {5'h10, 16'h800C, 1'b0, S2_CLKOUT0[9], S2_CLKOUT0[11], S2_CLKOUT0[10], S2_CLKFBOUT[10], S2_CLKFBOUT[11], //bits 15 downto 10 - S2_CLKFBOUT[9], S2_CLKFBOUT[8], S2_CLKFBOUT[7], S2_CLKFBOUT[6], S2_CLKFBOUT[13], //bits 9 downto 5 - S2_CLKFBOUT[20], 2'h0, S2_CLKFBOUT[21], S2_CLKFBOUT[22]}; //bits 4 downto 0 - - rom[35] = {5'h11, 16'hFC00, 6'h00, S2_CLKOUT3[3], S2_CLKOUT3[16], S2_CLKOUT2[11], S2_CLKOUT2[1], S2_CLKOUT1[18], //bits 15 downto 6 - S2_CLKOUT1[0], S2_CLKOUT0[6], S2_CLKOUT0[20], S2_CLKOUT0[8], S2_CLKOUT0[7]}; //bits 5 downto 0 - - rom[36] = {5'h12, 16'hF0FF, 4'h0, S2_CLKOUT5[14], S2_CLKFBOUT[14], S2_CLKOUT4[0], S2_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - - rom[37] = {5'h13, 16'h5120, S2_DIVCLK[11], 1'b0, S2_DIVCLK[10], 1'b0, S2_DIVCLK[7], S2_DIVCLK[8], //bits 15 downto 10 - S2_DIVCLK[0], 1'b0, S2_DIVCLK[5], S2_DIVCLK[2], 1'b0, S2_DIVCLK[13], 4'h0}; //bits 9 downto 0 - - rom[38] = {5'h14, 16'h2FFF, S2_LOCK[1], S2_LOCK[2], 1'b0, S2_LOCK[0], 12'h000}; //bits 15 downto 0 - - rom[39] = {5'h15, 16'hBFF4, 1'b0, S2_DIVCLK[12], 10'h000, S2_LOCK[38], 1'b0, S2_LOCK[32], S2_LOCK[39]}; //bits 15 downto 0 - - rom[40] = {5'h16, 16'h0A55, S2_LOCK[15], S2_LOCK[13], S2_LOCK[27], S2_LOCK[16], 1'b0, S2_LOCK[10], //bits 15 downto 10 - 1'b0, S2_DIVCLK[9], S2_DIVCLK[1], 1'b0, S2_DIVCLK[6], 1'b0, S2_DIVCLK[3], //bits 9 downto 3 - 1'b0, S2_DIVCLK[4], 1'b0}; //bits 2 downto 0 - - rom[41] = {5'h17, 16'hFFD0, 10'h000, S2_LOCK[17], 1'b0, S2_LOCK[8], S2_LOCK[9], S2_LOCK[23], S2_LOCK[22]}; //bits 15 downto 0 - - rom[42] = {5'h18, 16'h1039, S2_DIGITAL_FILT[6], S2_DIGITAL_FILT[7], S2_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S2_DIGITAL_FILT[2], S2_DIGITAL_FILT[1], S2_DIGITAL_FILT[3], S2_DIGITAL_FILT[9], //bits 11 downto 8 - S2_DIGITAL_FILT[8], S2_LOCK[26], 3'h0, S2_LOCK[19], S2_LOCK[18], 1'b0}; //bits 7 downto 0 - - rom[43] = {5'h19, 16'h0000, S2_LOCK[24], S2_LOCK[25], S2_LOCK[21], S2_LOCK[14], S2_LOCK[11], //bits 15 downto 11 - S2_LOCK[12], S2_LOCK[20], S2_LOCK[6], S2_LOCK[35], S2_LOCK[36], //bits 10 downto 6 - S2_LOCK[37], S2_LOCK[3], S2_LOCK[33], S2_LOCK[31], S2_LOCK[34], S2_LOCK[30]}; //bits 5 downto 0 - - rom[44] = {5'h1A, 16'hFFFC, 14'h0000, S2_LOCK[28], S2_LOCK[29]}; //bits 15 downto 0 - - rom[45] = {5'h1D, 16'h2FFF, S2_LOCK[7], S2_LOCK[4], 1'b0, S2_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[45] = {5'h1D, 16'h2FFF, S2_LOCK[7], S2_LOCK[4], 1'b0, S2_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 3 Initialization //*********************************************************************** rom[46] = {5'h05, 16'h50FF, S3_CLKOUT0[19], 1'b0, S3_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S3_CLKOUT0[16], S3_CLKOUT0[17], S3_CLKOUT0[15], S3_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S3_CLKOUT0[16], S3_CLKOUT0[17], S3_CLKOUT0[15], S3_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[47] = {5'h06, 16'h010B, S3_CLKOUT1[4], S3_CLKOUT1[5], S3_CLKOUT1[3], S3_CLKOUT1[12], //bits 15 down to 12 - S3_CLKOUT1[1], S3_CLKOUT1[2], S3_CLKOUT1[19], 1'b0, S3_CLKOUT1[17], S3_CLKOUT1[16], //bits 11 down to 6 - S3_CLKOUT1[14], S3_CLKOUT1[15], 1'b0, S3_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[47] = {5'h06, 16'h010B, S3_CLKOUT1[4], S3_CLKOUT1[5], S3_CLKOUT1[3], S3_CLKOUT1[12], //bits 15 down to 12 + S3_CLKOUT1[1], S3_CLKOUT1[2], S3_CLKOUT1[19], 1'b0, S3_CLKOUT1[17], S3_CLKOUT1[16], //bits 11 down to 6 + S3_CLKOUT1[14], S3_CLKOUT1[15], 1'b0, S3_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[48] = {5'h07, 16'hE02C, 3'h0, S3_CLKOUT1[11], S3_CLKOUT1[9], S3_CLKOUT1[10], //bits 15 down to 10 - S3_CLKOUT1[8], S3_CLKOUT1[7], S3_CLKOUT1[6], S3_CLKOUT1[20], 1'b0, S3_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S3_CLKOUT1[21], S3_CLKOUT1[22]}; //bits 3 down to 0 + rom[48] = {5'h07, 16'hE02C, 3'h0, S3_CLKOUT1[11], S3_CLKOUT1[9], S3_CLKOUT1[10], //bits 15 down to 10 + S3_CLKOUT1[8], S3_CLKOUT1[7], S3_CLKOUT1[6], S3_CLKOUT1[20], 1'b0, S3_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S3_CLKOUT1[21], S3_CLKOUT1[22]}; //bits 3 down to 0 - rom[49] = {5'h08, 16'h4001, S3_CLKOUT2[22], 1'b0, S3_CLKOUT2[5], S3_CLKOUT2[21], //bits 15 downto 12 - S3_CLKOUT2[12], S3_CLKOUT2[4], S3_CLKOUT2[3], S3_CLKOUT2[2], S3_CLKOUT2[0], S3_CLKOUT2[19], //bits 11 down to 6 - S3_CLKOUT2[17], S3_CLKOUT2[18], S3_CLKOUT2[15], S3_CLKOUT2[16], S3_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[49] = {5'h08, 16'h4001, S3_CLKOUT2[22], 1'b0, S3_CLKOUT2[5], S3_CLKOUT2[21], //bits 15 downto 12 + S3_CLKOUT2[12], S3_CLKOUT2[4], S3_CLKOUT2[3], S3_CLKOUT2[2], S3_CLKOUT2[0], S3_CLKOUT2[19], //bits 11 down to 6 + S3_CLKOUT2[17], S3_CLKOUT2[18], S3_CLKOUT2[15], S3_CLKOUT2[16], S3_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[50] = {5'h09, 16'h0D03, S3_CLKOUT3[14], S3_CLKOUT3[15], S3_CLKOUT0[21], S3_CLKOUT0[22], 2'h0, S3_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S3_CLKOUT2[9], S3_CLKOUT2[8], S3_CLKOUT2[6], S3_CLKOUT2[7], S3_CLKOUT2[13], S3_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[50] = {5'h09, 16'h0D03, S3_CLKOUT3[14], S3_CLKOUT3[15], S3_CLKOUT0[21], S3_CLKOUT0[22], 2'h0, S3_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S3_CLKOUT2[9], S3_CLKOUT2[8], S3_CLKOUT2[6], S3_CLKOUT2[7], S3_CLKOUT2[13], S3_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[51] = {5'h0A, 16'hB001, 1'b0, S3_CLKOUT3[13], 2'h0, S3_CLKOUT3[21], S3_CLKOUT3[22], S3_CLKOUT3[5], S3_CLKOUT3[4], //bits 15 downto 8 - S3_CLKOUT3[12], S3_CLKOUT3[2], S3_CLKOUT3[0], S3_CLKOUT3[1], S3_CLKOUT3[18], S3_CLKOUT3[19], //bits 7 downto 2 - S3_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[51] = {5'h0A, 16'hB001, 1'b0, S3_CLKOUT3[13], 2'h0, S3_CLKOUT3[21], S3_CLKOUT3[22], S3_CLKOUT3[5], S3_CLKOUT3[4], //bits 15 downto 8 + S3_CLKOUT3[12], S3_CLKOUT3[2], S3_CLKOUT3[0], S3_CLKOUT3[1], S3_CLKOUT3[18], S3_CLKOUT3[19], //bits 7 downto 2 + S3_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[52] = {5'h0B, 16'h0110, S3_CLKOUT0[5], S3_CLKOUT4[19], S3_CLKOUT4[14], S3_CLKOUT4[17], //bits 15 downto 12 - S3_CLKOUT4[15], S3_CLKOUT4[16], S3_CLKOUT0[4], 1'b0, S3_CLKOUT3[11], S3_CLKOUT3[10], //bits 11 downto 6 - S3_CLKOUT3[9], 1'b0, S3_CLKOUT3[7], S3_CLKOUT3[8], S3_CLKOUT3[20], S3_CLKOUT3[6]}; //bits 5 downto 0 + rom[52] = {5'h0B, 16'h0110, S3_CLKOUT0[5], S3_CLKOUT4[19], S3_CLKOUT4[14], S3_CLKOUT4[17], //bits 15 downto 12 + S3_CLKOUT4[15], S3_CLKOUT4[16], S3_CLKOUT0[4], 1'b0, S3_CLKOUT3[11], S3_CLKOUT3[10], //bits 11 downto 6 + S3_CLKOUT3[9], 1'b0, S3_CLKOUT3[7], S3_CLKOUT3[8], S3_CLKOUT3[20], S3_CLKOUT3[6]}; //bits 5 downto 0 - rom[53] = {5'h0C, 16'h0B00, S3_CLKOUT4[7], S3_CLKOUT4[8], S3_CLKOUT4[20], S3_CLKOUT4[6], 1'b0, S3_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S3_CLKOUT4[22], S3_CLKOUT4[21], S3_CLKOUT4[4], S3_CLKOUT4[5], S3_CLKOUT4[3], //bits 9 downto 3 - S3_CLKOUT4[12], S3_CLKOUT4[1], S3_CLKOUT4[2]}; //bits 2 downto 0 + rom[53] = {5'h0C, 16'h0B00, S3_CLKOUT4[7], S3_CLKOUT4[8], S3_CLKOUT4[20], S3_CLKOUT4[6], 1'b0, S3_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S3_CLKOUT4[22], S3_CLKOUT4[21], S3_CLKOUT4[4], S3_CLKOUT4[5], S3_CLKOUT4[3], //bits 9 downto 3 + S3_CLKOUT4[12], S3_CLKOUT4[1], S3_CLKOUT4[2]}; //bits 2 downto 0 - rom[54] = {5'h0D, 16'h0008, S3_CLKOUT5[2], S3_CLKOUT5[3], S3_CLKOUT5[0], S3_CLKOUT5[1], S3_CLKOUT5[18], //bits 15 downto 11 - S3_CLKOUT5[19], S3_CLKOUT5[17], S3_CLKOUT5[16], S3_CLKOUT5[15], S3_CLKOUT0[3], //bits 10 downto 6 - S3_CLKOUT0[0], S3_CLKOUT0[2], 1'b0, S3_CLKOUT4[11], S3_CLKOUT4[9], S3_CLKOUT4[10]}; //bits 5 downto 0 + rom[54] = {5'h0D, 16'h0008, S3_CLKOUT5[2], S3_CLKOUT5[3], S3_CLKOUT5[0], S3_CLKOUT5[1], S3_CLKOUT5[18], //bits 15 downto 11 + S3_CLKOUT5[19], S3_CLKOUT5[17], S3_CLKOUT5[16], S3_CLKOUT5[15], S3_CLKOUT0[3], //bits 10 downto 6 + S3_CLKOUT0[0], S3_CLKOUT0[2], 1'b0, S3_CLKOUT4[11], S3_CLKOUT4[9], S3_CLKOUT4[10]}; //bits 5 downto 0 - rom[55] = {5'h0E, 16'h00D0, S3_CLKOUT5[10], S3_CLKOUT5[11], S3_CLKOUT5[8], S3_CLKOUT5[9], S3_CLKOUT5[6], //bits 15 downto 11 - S3_CLKOUT5[7], S3_CLKOUT5[20], S3_CLKOUT5[13], 2'h0, S3_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S3_CLKOUT5[5], S3_CLKOUT5[21], S3_CLKOUT5[12], S3_CLKOUT5[4]}; //bits 3 downto 0 + rom[55] = {5'h0E, 16'h00D0, S3_CLKOUT5[10], S3_CLKOUT5[11], S3_CLKOUT5[8], S3_CLKOUT5[9], S3_CLKOUT5[6], //bits 15 downto 11 + S3_CLKOUT5[7], S3_CLKOUT5[20], S3_CLKOUT5[13], 2'h0, S3_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S3_CLKOUT5[5], S3_CLKOUT5[21], S3_CLKOUT5[12], S3_CLKOUT5[4]}; //bits 3 downto 0 - rom[56] = {5'h0F, 16'h0003, S3_CLKFBOUT[4], S3_CLKFBOUT[5], S3_CLKFBOUT[3], S3_CLKFBOUT[12], S3_CLKFBOUT[1], //bits 15 downto 11 - S3_CLKFBOUT[2], S3_CLKFBOUT[0], S3_CLKFBOUT[19], S3_CLKFBOUT[18], S3_CLKFBOUT[17], //bits 10 downto 6 - S3_CLKFBOUT[15], S3_CLKFBOUT[16], S3_CLKOUT0[12], S3_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[56] = {5'h0F, 16'h0003, S3_CLKFBOUT[4], S3_CLKFBOUT[5], S3_CLKFBOUT[3], S3_CLKFBOUT[12], S3_CLKFBOUT[1], //bits 15 downto 11 + S3_CLKFBOUT[2], S3_CLKFBOUT[0], S3_CLKFBOUT[19], S3_CLKFBOUT[18], S3_CLKFBOUT[17], //bits 10 downto 6 + S3_CLKFBOUT[15], S3_CLKFBOUT[16], S3_CLKOUT0[12], S3_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[57] = {5'h10, 16'h800C, 1'b0, S3_CLKOUT0[9], S3_CLKOUT0[11], S3_CLKOUT0[10], S3_CLKFBOUT[10], S3_CLKFBOUT[11], //bits 15 downto 10 - S3_CLKFBOUT[9], S3_CLKFBOUT[8], S3_CLKFBOUT[7], S3_CLKFBOUT[6], S3_CLKFBOUT[13], //bits 9 downto 5 - S3_CLKFBOUT[20], 2'h0, S3_CLKFBOUT[21], S3_CLKFBOUT[22]}; //bits 4 downto 0 + rom[57] = {5'h10, 16'h800C, 1'b0, S3_CLKOUT0[9], S3_CLKOUT0[11], S3_CLKOUT0[10], S3_CLKFBOUT[10], S3_CLKFBOUT[11], //bits 15 downto 10 + S3_CLKFBOUT[9], S3_CLKFBOUT[8], S3_CLKFBOUT[7], S3_CLKFBOUT[6], S3_CLKFBOUT[13], //bits 9 downto 5 + S3_CLKFBOUT[20], 2'h0, S3_CLKFBOUT[21], S3_CLKFBOUT[22]}; //bits 4 downto 0 - rom[58] = {5'h11, 16'hFC00, 6'h00, S3_CLKOUT3[3], S3_CLKOUT3[16], S3_CLKOUT2[11], S3_CLKOUT2[1], S3_CLKOUT1[18], //bits 15 downto 6 - S3_CLKOUT1[0], S3_CLKOUT0[6], S3_CLKOUT0[20], S3_CLKOUT0[8], S3_CLKOUT0[7]}; //bits 5 downto 0 + rom[58] = {5'h11, 16'hFC00, 6'h00, S3_CLKOUT3[3], S3_CLKOUT3[16], S3_CLKOUT2[11], S3_CLKOUT2[1], S3_CLKOUT1[18], //bits 15 downto 6 + S3_CLKOUT1[0], S3_CLKOUT0[6], S3_CLKOUT0[20], S3_CLKOUT0[8], S3_CLKOUT0[7]}; //bits 5 downto 0 - rom[59] = {5'h12, 16'hF0FF, 4'h0, S3_CLKOUT5[14], S3_CLKFBOUT[14], S3_CLKOUT4[0], S3_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[59] = {5'h12, 16'hF0FF, 4'h0, S3_CLKOUT5[14], S3_CLKFBOUT[14], S3_CLKOUT4[0], S3_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[60] = {5'h13, 16'h5120, S3_DIVCLK[11], 1'b0, S3_DIVCLK[10], 1'b0, S3_DIVCLK[7], S3_DIVCLK[8], //bits 15 downto 10 - S3_DIVCLK[0], 1'b0, S3_DIVCLK[5], S3_DIVCLK[2], 1'b0, S3_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[60] = {5'h13, 16'h5120, S3_DIVCLK[11], 1'b0, S3_DIVCLK[10], 1'b0, S3_DIVCLK[7], S3_DIVCLK[8], //bits 15 downto 10 + S3_DIVCLK[0], 1'b0, S3_DIVCLK[5], S3_DIVCLK[2], 1'b0, S3_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[61] = {5'h14, 16'h2FFF, S3_LOCK[1], S3_LOCK[2], 1'b0, S3_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[61] = {5'h14, 16'h2FFF, S3_LOCK[1], S3_LOCK[2], 1'b0, S3_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[62] = {5'h15, 16'hBFF4, 1'b0, S3_DIVCLK[12], 10'h000, S3_LOCK[38], 1'b0, S3_LOCK[32], S3_LOCK[39]}; //bits 15 downto 0 + rom[62] = {5'h15, 16'hBFF4, 1'b0, S3_DIVCLK[12], 10'h000, S3_LOCK[38], 1'b0, S3_LOCK[32], S3_LOCK[39]}; //bits 15 downto 0 - rom[63] = {5'h16, 16'h0A55, S3_LOCK[15], S3_LOCK[13], S3_LOCK[27], S3_LOCK[16], 1'b0, S3_LOCK[10], //bits 15 downto 10 - 1'b0, S3_DIVCLK[9], S3_DIVCLK[1], 1'b0, S3_DIVCLK[6], 1'b0, S3_DIVCLK[3], //bits 9 downto 3 - 1'b0, S3_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[63] = {5'h16, 16'h0A55, S3_LOCK[15], S3_LOCK[13], S3_LOCK[27], S3_LOCK[16], 1'b0, S3_LOCK[10], //bits 15 downto 10 + 1'b0, S3_DIVCLK[9], S3_DIVCLK[1], 1'b0, S3_DIVCLK[6], 1'b0, S3_DIVCLK[3], //bits 9 downto 3 + 1'b0, S3_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[64] = {5'h17, 16'hFFD0, 10'h000, S3_LOCK[17], 1'b0, S3_LOCK[8], S3_LOCK[9], S3_LOCK[23], S3_LOCK[22]}; //bits 15 downto 0 + rom[64] = {5'h17, 16'hFFD0, 10'h000, S3_LOCK[17], 1'b0, S3_LOCK[8], S3_LOCK[9], S3_LOCK[23], S3_LOCK[22]}; //bits 15 downto 0 - rom[65] = {5'h18, 16'h1039, S3_DIGITAL_FILT[6], S3_DIGITAL_FILT[7], S3_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S3_DIGITAL_FILT[2], S3_DIGITAL_FILT[1], S3_DIGITAL_FILT[3], S3_DIGITAL_FILT[9], //bits 11 downto 8 - S3_DIGITAL_FILT[8], S3_LOCK[26], 3'h0, S3_LOCK[19], S3_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[65] = {5'h18, 16'h1039, S3_DIGITAL_FILT[6], S3_DIGITAL_FILT[7], S3_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S3_DIGITAL_FILT[2], S3_DIGITAL_FILT[1], S3_DIGITAL_FILT[3], S3_DIGITAL_FILT[9], //bits 11 downto 8 + S3_DIGITAL_FILT[8], S3_LOCK[26], 3'h0, S3_LOCK[19], S3_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[66] = {5'h19, 16'h0000, S3_LOCK[24], S3_LOCK[25], S3_LOCK[21], S3_LOCK[14], S3_LOCK[11], //bits 15 downto 11 - S3_LOCK[12], S3_LOCK[20], S3_LOCK[6], S3_LOCK[35], S3_LOCK[36], //bits 10 downto 6 - S3_LOCK[37], S3_LOCK[3], S3_LOCK[33], S3_LOCK[31], S3_LOCK[34], S3_LOCK[30]}; //bits 5 downto 0 + rom[66] = {5'h19, 16'h0000, S3_LOCK[24], S3_LOCK[25], S3_LOCK[21], S3_LOCK[14], S3_LOCK[11], //bits 15 downto 11 + S3_LOCK[12], S3_LOCK[20], S3_LOCK[6], S3_LOCK[35], S3_LOCK[36], //bits 10 downto 6 + S3_LOCK[37], S3_LOCK[3], S3_LOCK[33], S3_LOCK[31], S3_LOCK[34], S3_LOCK[30]}; //bits 5 downto 0 - rom[67] = {5'h1A, 16'hFFFC, 14'h0000, S3_LOCK[28], S3_LOCK[29]}; //bits 15 downto 0 + rom[67] = {5'h1A, 16'hFFFC, 14'h0000, S3_LOCK[28], S3_LOCK[29]}; //bits 15 downto 0 - rom[68] = {5'h1D, 16'h2FFF, S3_LOCK[7], S3_LOCK[4], 1'b0, S3_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[68] = {5'h1D, 16'h2FFF, S3_LOCK[7], S3_LOCK[4], 1'b0, S3_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 4 Initialization //*********************************************************************** rom[69] = {5'h05, 16'h50FF, S4_CLKOUT0[19], 1'b0, S4_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S4_CLKOUT0[16], S4_CLKOUT0[17], S4_CLKOUT0[15], S4_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S4_CLKOUT0[16], S4_CLKOUT0[17], S4_CLKOUT0[15], S4_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[70] = {5'h06, 16'h010B, S4_CLKOUT1[4], S4_CLKOUT1[5], S4_CLKOUT1[3], S4_CLKOUT1[12], //bits 15 down to 12 - S4_CLKOUT1[1], S4_CLKOUT1[2], S4_CLKOUT1[19], 1'b0, S4_CLKOUT1[17], S4_CLKOUT1[16], //bits 11 down to 6 - S4_CLKOUT1[14], S4_CLKOUT1[15], 1'b0, S4_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[70] = {5'h06, 16'h010B, S4_CLKOUT1[4], S4_CLKOUT1[5], S4_CLKOUT1[3], S4_CLKOUT1[12], //bits 15 down to 12 + S4_CLKOUT1[1], S4_CLKOUT1[2], S4_CLKOUT1[19], 1'b0, S4_CLKOUT1[17], S4_CLKOUT1[16], //bits 11 down to 6 + S4_CLKOUT1[14], S4_CLKOUT1[15], 1'b0, S4_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[71] = {5'h07, 16'hE02C, 3'h0, S4_CLKOUT1[11], S4_CLKOUT1[9], S4_CLKOUT1[10], //bits 15 down to 10 - S4_CLKOUT1[8], S4_CLKOUT1[7], S4_CLKOUT1[6], S4_CLKOUT1[20], 1'b0, S4_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S4_CLKOUT1[21], S4_CLKOUT1[22]}; //bits 3 down to 0 + rom[71] = {5'h07, 16'hE02C, 3'h0, S4_CLKOUT1[11], S4_CLKOUT1[9], S4_CLKOUT1[10], //bits 15 down to 10 + S4_CLKOUT1[8], S4_CLKOUT1[7], S4_CLKOUT1[6], S4_CLKOUT1[20], 1'b0, S4_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S4_CLKOUT1[21], S4_CLKOUT1[22]}; //bits 3 down to 0 - rom[72] = {5'h08, 16'h4001, S4_CLKOUT2[22], 1'b0, S4_CLKOUT2[5], S4_CLKOUT2[21], //bits 15 downto 12 - S4_CLKOUT2[12], S4_CLKOUT2[4], S4_CLKOUT2[3], S4_CLKOUT2[2], S4_CLKOUT2[0], S4_CLKOUT2[19], //bits 11 down to 6 - S4_CLKOUT2[17], S4_CLKOUT2[18], S4_CLKOUT2[15], S4_CLKOUT2[16], S4_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[72] = {5'h08, 16'h4001, S4_CLKOUT2[22], 1'b0, S4_CLKOUT2[5], S4_CLKOUT2[21], //bits 15 downto 12 + S4_CLKOUT2[12], S4_CLKOUT2[4], S4_CLKOUT2[3], S4_CLKOUT2[2], S4_CLKOUT2[0], S4_CLKOUT2[19], //bits 11 down to 6 + S4_CLKOUT2[17], S4_CLKOUT2[18], S4_CLKOUT2[15], S4_CLKOUT2[16], S4_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[73] = {5'h09, 16'h0D03, S4_CLKOUT3[14], S4_CLKOUT3[15], S4_CLKOUT0[21], S4_CLKOUT0[22], 2'h0, S4_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S4_CLKOUT2[9], S4_CLKOUT2[8], S4_CLKOUT2[6], S4_CLKOUT2[7], S4_CLKOUT2[13], S4_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[73] = {5'h09, 16'h0D03, S4_CLKOUT3[14], S4_CLKOUT3[15], S4_CLKOUT0[21], S4_CLKOUT0[22], 2'h0, S4_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S4_CLKOUT2[9], S4_CLKOUT2[8], S4_CLKOUT2[6], S4_CLKOUT2[7], S4_CLKOUT2[13], S4_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[74] = {5'h0A, 16'hB001, 1'b0, S4_CLKOUT3[13], 2'h0, S4_CLKOUT3[21], S4_CLKOUT3[22], S4_CLKOUT3[5], S4_CLKOUT3[4], //bits 15 downto 8 - S4_CLKOUT3[12], S4_CLKOUT3[2], S4_CLKOUT3[0], S4_CLKOUT3[1], S4_CLKOUT3[18], S4_CLKOUT3[19], //bits 7 downto 2 - S4_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[74] = {5'h0A, 16'hB001, 1'b0, S4_CLKOUT3[13], 2'h0, S4_CLKOUT3[21], S4_CLKOUT3[22], S4_CLKOUT3[5], S4_CLKOUT3[4], //bits 15 downto 8 + S4_CLKOUT3[12], S4_CLKOUT3[2], S4_CLKOUT3[0], S4_CLKOUT3[1], S4_CLKOUT3[18], S4_CLKOUT3[19], //bits 7 downto 2 + S4_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[75] = {5'h0B, 16'h0110, S4_CLKOUT0[5], S4_CLKOUT4[19], S4_CLKOUT4[14], S4_CLKOUT4[17], //bits 15 downto 12 - S4_CLKOUT4[15], S4_CLKOUT4[16], S4_CLKOUT0[4], 1'b0, S4_CLKOUT3[11], S4_CLKOUT3[10], //bits 11 downto 6 - S4_CLKOUT3[9], 1'b0, S4_CLKOUT3[7], S4_CLKOUT3[8], S4_CLKOUT3[20], S4_CLKOUT3[6]}; //bits 5 downto 0 + rom[75] = {5'h0B, 16'h0110, S4_CLKOUT0[5], S4_CLKOUT4[19], S4_CLKOUT4[14], S4_CLKOUT4[17], //bits 15 downto 12 + S4_CLKOUT4[15], S4_CLKOUT4[16], S4_CLKOUT0[4], 1'b0, S4_CLKOUT3[11], S4_CLKOUT3[10], //bits 11 downto 6 + S4_CLKOUT3[9], 1'b0, S4_CLKOUT3[7], S4_CLKOUT3[8], S4_CLKOUT3[20], S4_CLKOUT3[6]}; //bits 5 downto 0 - rom[76] = {5'h0C, 16'h0B00, S4_CLKOUT4[7], S4_CLKOUT4[8], S4_CLKOUT4[20], S4_CLKOUT4[6], 1'b0, S4_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S4_CLKOUT4[22], S4_CLKOUT4[21], S4_CLKOUT4[4], S4_CLKOUT4[5], S4_CLKOUT4[3], //bits 9 downto 3 - S4_CLKOUT4[12], S4_CLKOUT4[1], S4_CLKOUT4[2]}; //bits 2 downto 0 + rom[76] = {5'h0C, 16'h0B00, S4_CLKOUT4[7], S4_CLKOUT4[8], S4_CLKOUT4[20], S4_CLKOUT4[6], 1'b0, S4_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S4_CLKOUT4[22], S4_CLKOUT4[21], S4_CLKOUT4[4], S4_CLKOUT4[5], S4_CLKOUT4[3], //bits 9 downto 3 + S4_CLKOUT4[12], S4_CLKOUT4[1], S4_CLKOUT4[2]}; //bits 2 downto 0 - rom[77] = {5'h0D, 16'h0008, S4_CLKOUT5[2], S4_CLKOUT5[3], S4_CLKOUT5[0], S4_CLKOUT5[1], S4_CLKOUT5[18], //bits 15 downto 11 - S4_CLKOUT5[19], S4_CLKOUT5[17], S4_CLKOUT5[16], S4_CLKOUT5[15], S4_CLKOUT0[3], //bits 10 downto 6 - S4_CLKOUT0[0], S4_CLKOUT0[2], 1'b0, S4_CLKOUT4[11], S4_CLKOUT4[9], S4_CLKOUT4[10]}; //bits 5 downto 0 + rom[77] = {5'h0D, 16'h0008, S4_CLKOUT5[2], S4_CLKOUT5[3], S4_CLKOUT5[0], S4_CLKOUT5[1], S4_CLKOUT5[18], //bits 15 downto 11 + S4_CLKOUT5[19], S4_CLKOUT5[17], S4_CLKOUT5[16], S4_CLKOUT5[15], S4_CLKOUT0[3], //bits 10 downto 6 + S4_CLKOUT0[0], S4_CLKOUT0[2], 1'b0, S4_CLKOUT4[11], S4_CLKOUT4[9], S4_CLKOUT4[10]}; //bits 5 downto 0 - rom[78] = {5'h0E, 16'h00D0, S4_CLKOUT5[10], S4_CLKOUT5[11], S4_CLKOUT5[8], S4_CLKOUT5[9], S4_CLKOUT5[6], //bits 15 downto 11 - S4_CLKOUT5[7], S4_CLKOUT5[20], S4_CLKOUT5[13], 2'h0, S4_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S4_CLKOUT5[5], S4_CLKOUT5[21], S4_CLKOUT5[12], S4_CLKOUT5[4]}; //bits 3 downto 0 + rom[78] = {5'h0E, 16'h00D0, S4_CLKOUT5[10], S4_CLKOUT5[11], S4_CLKOUT5[8], S4_CLKOUT5[9], S4_CLKOUT5[6], //bits 15 downto 11 + S4_CLKOUT5[7], S4_CLKOUT5[20], S4_CLKOUT5[13], 2'h0, S4_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S4_CLKOUT5[5], S4_CLKOUT5[21], S4_CLKOUT5[12], S4_CLKOUT5[4]}; //bits 3 downto 0 - rom[79] = {5'h0F, 16'h0003, S4_CLKFBOUT[4], S4_CLKFBOUT[5], S4_CLKFBOUT[3], S4_CLKFBOUT[12], S4_CLKFBOUT[1], //bits 15 downto 11 - S4_CLKFBOUT[2], S4_CLKFBOUT[0], S4_CLKFBOUT[19], S4_CLKFBOUT[18], S4_CLKFBOUT[17], //bits 10 downto 6 - S4_CLKFBOUT[15], S4_CLKFBOUT[16], S4_CLKOUT0[12], S4_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[79] = {5'h0F, 16'h0003, S4_CLKFBOUT[4], S4_CLKFBOUT[5], S4_CLKFBOUT[3], S4_CLKFBOUT[12], S4_CLKFBOUT[1], //bits 15 downto 11 + S4_CLKFBOUT[2], S4_CLKFBOUT[0], S4_CLKFBOUT[19], S4_CLKFBOUT[18], S4_CLKFBOUT[17], //bits 10 downto 6 + S4_CLKFBOUT[15], S4_CLKFBOUT[16], S4_CLKOUT0[12], S4_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[80] = {5'h10, 16'h800C, 1'b0, S4_CLKOUT0[9], S4_CLKOUT0[11], S4_CLKOUT0[10], S4_CLKFBOUT[10], S4_CLKFBOUT[11], //bits 15 downto 10 - S4_CLKFBOUT[9], S4_CLKFBOUT[8], S4_CLKFBOUT[7], S4_CLKFBOUT[6], S4_CLKFBOUT[13], //bits 9 downto 5 - S4_CLKFBOUT[20], 2'h0, S4_CLKFBOUT[21], S4_CLKFBOUT[22]}; //bits 4 downto 0 + rom[80] = {5'h10, 16'h800C, 1'b0, S4_CLKOUT0[9], S4_CLKOUT0[11], S4_CLKOUT0[10], S4_CLKFBOUT[10], S4_CLKFBOUT[11], //bits 15 downto 10 + S4_CLKFBOUT[9], S4_CLKFBOUT[8], S4_CLKFBOUT[7], S4_CLKFBOUT[6], S4_CLKFBOUT[13], //bits 9 downto 5 + S4_CLKFBOUT[20], 2'h0, S4_CLKFBOUT[21], S4_CLKFBOUT[22]}; //bits 4 downto 0 - rom[81] = {5'h11, 16'hFC00, 6'h00, S4_CLKOUT3[3], S4_CLKOUT3[16], S4_CLKOUT2[11], S4_CLKOUT2[1], S4_CLKOUT1[18], //bits 15 downto 6 - S4_CLKOUT1[0], S4_CLKOUT0[6], S4_CLKOUT0[20], S4_CLKOUT0[8], S4_CLKOUT0[7]}; //bits 5 downto 0 + rom[81] = {5'h11, 16'hFC00, 6'h00, S4_CLKOUT3[3], S4_CLKOUT3[16], S4_CLKOUT2[11], S4_CLKOUT2[1], S4_CLKOUT1[18], //bits 15 downto 6 + S4_CLKOUT1[0], S4_CLKOUT0[6], S4_CLKOUT0[20], S4_CLKOUT0[8], S4_CLKOUT0[7]}; //bits 5 downto 0 - rom[82] = {5'h12, 16'hF0FF, 4'h0, S4_CLKOUT5[14], S4_CLKFBOUT[14], S4_CLKOUT4[0], S4_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[82] = {5'h12, 16'hF0FF, 4'h0, S4_CLKOUT5[14], S4_CLKFBOUT[14], S4_CLKOUT4[0], S4_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[83] = {5'h13, 16'h5120, S4_DIVCLK[11], 1'b0, S4_DIVCLK[10], 1'b0, S4_DIVCLK[7], S4_DIVCLK[8], //bits 15 downto 10 - S4_DIVCLK[0], 1'b0, S4_DIVCLK[5], S4_DIVCLK[2], 1'b0, S4_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[83] = {5'h13, 16'h5120, S4_DIVCLK[11], 1'b0, S4_DIVCLK[10], 1'b0, S4_DIVCLK[7], S4_DIVCLK[8], //bits 15 downto 10 + S4_DIVCLK[0], 1'b0, S4_DIVCLK[5], S4_DIVCLK[2], 1'b0, S4_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[84] = {5'h14, 16'h2FFF, S4_LOCK[1], S4_LOCK[2], 1'b0, S4_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[84] = {5'h14, 16'h2FFF, S4_LOCK[1], S4_LOCK[2], 1'b0, S4_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[85] = {5'h15, 16'hBFF4, 1'b0, S4_DIVCLK[12], 10'h000, S4_LOCK[38], 1'b0, S4_LOCK[32], S4_LOCK[39]}; //bits 15 downto 0 + rom[85] = {5'h15, 16'hBFF4, 1'b0, S4_DIVCLK[12], 10'h000, S4_LOCK[38], 1'b0, S4_LOCK[32], S4_LOCK[39]}; //bits 15 downto 0 - rom[86] = {5'h16, 16'h0A55, S4_LOCK[15], S4_LOCK[13], S4_LOCK[27], S4_LOCK[16], 1'b0, S4_LOCK[10], //bits 15 downto 10 - 1'b0, S4_DIVCLK[9], S4_DIVCLK[1], 1'b0, S4_DIVCLK[6], 1'b0, S4_DIVCLK[3], //bits 9 downto 3 - 1'b0, S4_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[86] = {5'h16, 16'h0A55, S4_LOCK[15], S4_LOCK[13], S4_LOCK[27], S4_LOCK[16], 1'b0, S4_LOCK[10], //bits 15 downto 10 + 1'b0, S4_DIVCLK[9], S4_DIVCLK[1], 1'b0, S4_DIVCLK[6], 1'b0, S4_DIVCLK[3], //bits 9 downto 3 + 1'b0, S4_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[87] = {5'h17, 16'hFFD0, 10'h000, S4_LOCK[17], 1'b0, S4_LOCK[8], S4_LOCK[9], S4_LOCK[23], S4_LOCK[22]}; //bits 15 downto 0 + rom[87] = {5'h17, 16'hFFD0, 10'h000, S4_LOCK[17], 1'b0, S4_LOCK[8], S4_LOCK[9], S4_LOCK[23], S4_LOCK[22]}; //bits 15 downto 0 - rom[88] = {5'h18, 16'h1039, S4_DIGITAL_FILT[6], S4_DIGITAL_FILT[7], S4_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S4_DIGITAL_FILT[2], S4_DIGITAL_FILT[1], S4_DIGITAL_FILT[3], S4_DIGITAL_FILT[9], //bits 11 downto 8 - S4_DIGITAL_FILT[8], S4_LOCK[26], 3'h0, S4_LOCK[19], S4_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[88] = {5'h18, 16'h1039, S4_DIGITAL_FILT[6], S4_DIGITAL_FILT[7], S4_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S4_DIGITAL_FILT[2], S4_DIGITAL_FILT[1], S4_DIGITAL_FILT[3], S4_DIGITAL_FILT[9], //bits 11 downto 8 + S4_DIGITAL_FILT[8], S4_LOCK[26], 3'h0, S4_LOCK[19], S4_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[89] = {5'h19, 16'h0000, S4_LOCK[24], S4_LOCK[25], S4_LOCK[21], S4_LOCK[14], S4_LOCK[11], //bits 15 downto 11 - S4_LOCK[12], S4_LOCK[20], S4_LOCK[6], S4_LOCK[35], S4_LOCK[36], //bits 10 downto 6 - S4_LOCK[37], S4_LOCK[3], S4_LOCK[33], S4_LOCK[31], S4_LOCK[34], S4_LOCK[30]}; //bits 5 downto 0 + rom[89] = {5'h19, 16'h0000, S4_LOCK[24], S4_LOCK[25], S4_LOCK[21], S4_LOCK[14], S4_LOCK[11], //bits 15 downto 11 + S4_LOCK[12], S4_LOCK[20], S4_LOCK[6], S4_LOCK[35], S4_LOCK[36], //bits 10 downto 6 + S4_LOCK[37], S4_LOCK[3], S4_LOCK[33], S4_LOCK[31], S4_LOCK[34], S4_LOCK[30]}; //bits 5 downto 0 - rom[90] = {5'h1A, 16'hFFFC, 14'h0000, S4_LOCK[28], S4_LOCK[29]}; //bits 15 downto 0 + rom[90] = {5'h1A, 16'hFFFC, 14'h0000, S4_LOCK[28], S4_LOCK[29]}; //bits 15 downto 0 - rom[91] = {5'h1D, 16'h2FFF, S4_LOCK[7], S4_LOCK[4], 1'b0, S4_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[91] = {5'h1D, 16'h2FFF, S4_LOCK[7], S4_LOCK[4], 1'b0, S4_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 5 Initialization //*********************************************************************** rom[92] = {5'h05, 16'h50FF, S5_CLKOUT0[19], 1'b0, S5_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S5_CLKOUT0[16], S5_CLKOUT0[17], S5_CLKOUT0[15], S5_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S5_CLKOUT0[16], S5_CLKOUT0[17], S5_CLKOUT0[15], S5_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[93] = {5'h06, 16'h010B, S5_CLKOUT1[4], S5_CLKOUT1[5], S5_CLKOUT1[3], S5_CLKOUT1[12], //bits 15 down to 12 - S5_CLKOUT1[1], S5_CLKOUT1[2], S5_CLKOUT1[19], 1'b0, S5_CLKOUT1[17], S5_CLKOUT1[16], //bits 11 down to 6 - S5_CLKOUT1[14], S5_CLKOUT1[15], 1'b0, S5_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[93] = {5'h06, 16'h010B, S5_CLKOUT1[4], S5_CLKOUT1[5], S5_CLKOUT1[3], S5_CLKOUT1[12], //bits 15 down to 12 + S5_CLKOUT1[1], S5_CLKOUT1[2], S5_CLKOUT1[19], 1'b0, S5_CLKOUT1[17], S5_CLKOUT1[16], //bits 11 down to 6 + S5_CLKOUT1[14], S5_CLKOUT1[15], 1'b0, S5_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[94] = {5'h07, 16'hE02C, 3'h0, S5_CLKOUT1[11], S5_CLKOUT1[9], S5_CLKOUT1[10], //bits 15 down to 10 - S5_CLKOUT1[8], S5_CLKOUT1[7], S5_CLKOUT1[6], S5_CLKOUT1[20], 1'b0, S5_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S5_CLKOUT1[21], S5_CLKOUT1[22]}; //bits 3 down to 0 + rom[94] = {5'h07, 16'hE02C, 3'h0, S5_CLKOUT1[11], S5_CLKOUT1[9], S5_CLKOUT1[10], //bits 15 down to 10 + S5_CLKOUT1[8], S5_CLKOUT1[7], S5_CLKOUT1[6], S5_CLKOUT1[20], 1'b0, S5_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S5_CLKOUT1[21], S5_CLKOUT1[22]}; //bits 3 down to 0 - rom[95] = {5'h08, 16'h4001, S5_CLKOUT2[22], 1'b0, S5_CLKOUT2[5], S5_CLKOUT2[21], //bits 15 downto 12 - S5_CLKOUT2[12], S5_CLKOUT2[4], S5_CLKOUT2[3], S5_CLKOUT2[2], S5_CLKOUT2[0], S5_CLKOUT2[19], //bits 11 down to 6 - S5_CLKOUT2[17], S5_CLKOUT2[18], S5_CLKOUT2[15], S5_CLKOUT2[16], S5_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[95] = {5'h08, 16'h4001, S5_CLKOUT2[22], 1'b0, S5_CLKOUT2[5], S5_CLKOUT2[21], //bits 15 downto 12 + S5_CLKOUT2[12], S5_CLKOUT2[4], S5_CLKOUT2[3], S5_CLKOUT2[2], S5_CLKOUT2[0], S5_CLKOUT2[19], //bits 11 down to 6 + S5_CLKOUT2[17], S5_CLKOUT2[18], S5_CLKOUT2[15], S5_CLKOUT2[16], S5_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[96] = {5'h09, 16'h0D03, S5_CLKOUT3[14], S5_CLKOUT3[15], S5_CLKOUT0[21], S5_CLKOUT0[22], 2'h0, S5_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S5_CLKOUT2[9], S5_CLKOUT2[8], S5_CLKOUT2[6], S5_CLKOUT2[7], S5_CLKOUT2[13], S5_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[96] = {5'h09, 16'h0D03, S5_CLKOUT3[14], S5_CLKOUT3[15], S5_CLKOUT0[21], S5_CLKOUT0[22], 2'h0, S5_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S5_CLKOUT2[9], S5_CLKOUT2[8], S5_CLKOUT2[6], S5_CLKOUT2[7], S5_CLKOUT2[13], S5_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[97] = {5'h0A, 16'hB001, 1'b0, S5_CLKOUT3[13], 2'h0, S5_CLKOUT3[21], S5_CLKOUT3[22], S5_CLKOUT3[5], S5_CLKOUT3[4], //bits 15 downto 8 - S5_CLKOUT3[12], S5_CLKOUT3[2], S5_CLKOUT3[0], S5_CLKOUT3[1], S5_CLKOUT3[18], S5_CLKOUT3[19], //bits 7 downto 2 - S5_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[97] = {5'h0A, 16'hB001, 1'b0, S5_CLKOUT3[13], 2'h0, S5_CLKOUT3[21], S5_CLKOUT3[22], S5_CLKOUT3[5], S5_CLKOUT3[4], //bits 15 downto 8 + S5_CLKOUT3[12], S5_CLKOUT3[2], S5_CLKOUT3[0], S5_CLKOUT3[1], S5_CLKOUT3[18], S5_CLKOUT3[19], //bits 7 downto 2 + S5_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[98] = {5'h0B, 16'h0110, S5_CLKOUT0[5], S5_CLKOUT4[19], S5_CLKOUT4[14], S5_CLKOUT4[17], //bits 15 downto 12 - S5_CLKOUT4[15], S5_CLKOUT4[16], S5_CLKOUT0[4], 1'b0, S5_CLKOUT3[11], S5_CLKOUT3[10], //bits 11 downto 6 - S5_CLKOUT3[9], 1'b0, S5_CLKOUT3[7], S5_CLKOUT3[8], S5_CLKOUT3[20], S5_CLKOUT3[6]}; //bits 5 downto 0 + rom[98] = {5'h0B, 16'h0110, S5_CLKOUT0[5], S5_CLKOUT4[19], S5_CLKOUT4[14], S5_CLKOUT4[17], //bits 15 downto 12 + S5_CLKOUT4[15], S5_CLKOUT4[16], S5_CLKOUT0[4], 1'b0, S5_CLKOUT3[11], S5_CLKOUT3[10], //bits 11 downto 6 + S5_CLKOUT3[9], 1'b0, S5_CLKOUT3[7], S5_CLKOUT3[8], S5_CLKOUT3[20], S5_CLKOUT3[6]}; //bits 5 downto 0 - rom[99] = {5'h0C, 16'h0B00, S5_CLKOUT4[7], S5_CLKOUT4[8], S5_CLKOUT4[20], S5_CLKOUT4[6], 1'b0, S5_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S5_CLKOUT4[22], S5_CLKOUT4[21], S5_CLKOUT4[4], S5_CLKOUT4[5], S5_CLKOUT4[3], //bits 9 downto 3 - S5_CLKOUT4[12], S5_CLKOUT4[1], S5_CLKOUT4[2]}; //bits 2 downto 0 + rom[99] = {5'h0C, 16'h0B00, S5_CLKOUT4[7], S5_CLKOUT4[8], S5_CLKOUT4[20], S5_CLKOUT4[6], 1'b0, S5_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S5_CLKOUT4[22], S5_CLKOUT4[21], S5_CLKOUT4[4], S5_CLKOUT4[5], S5_CLKOUT4[3], //bits 9 downto 3 + S5_CLKOUT4[12], S5_CLKOUT4[1], S5_CLKOUT4[2]}; //bits 2 downto 0 - rom[100] = {5'h0D, 16'h0008, S5_CLKOUT5[2], S5_CLKOUT5[3], S5_CLKOUT5[0], S5_CLKOUT5[1], S5_CLKOUT5[18], //bits 15 downto 11 - S5_CLKOUT5[19], S5_CLKOUT5[17], S5_CLKOUT5[16], S5_CLKOUT5[15], S5_CLKOUT0[3], //bits 10 downto 6 - S5_CLKOUT0[0], S5_CLKOUT0[2], 1'b0, S5_CLKOUT4[11], S5_CLKOUT4[9], S5_CLKOUT4[10]}; //bits 5 downto 0 + rom[100] = {5'h0D, 16'h0008, S5_CLKOUT5[2], S5_CLKOUT5[3], S5_CLKOUT5[0], S5_CLKOUT5[1], S5_CLKOUT5[18], //bits 15 downto 11 + S5_CLKOUT5[19], S5_CLKOUT5[17], S5_CLKOUT5[16], S5_CLKOUT5[15], S5_CLKOUT0[3], //bits 10 downto 6 + S5_CLKOUT0[0], S5_CLKOUT0[2], 1'b0, S5_CLKOUT4[11], S5_CLKOUT4[9], S5_CLKOUT4[10]}; //bits 5 downto 0 - rom[101] = {5'h0E, 16'h00D0, S5_CLKOUT5[10], S5_CLKOUT5[11], S5_CLKOUT5[8], S5_CLKOUT5[9], S5_CLKOUT5[6], //bits 15 downto 11 - S5_CLKOUT5[7], S5_CLKOUT5[20], S5_CLKOUT5[13], 2'h0, S5_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S5_CLKOUT5[5], S5_CLKOUT5[21], S5_CLKOUT5[12], S5_CLKOUT5[4]}; //bits 3 downto 0 + rom[101] = {5'h0E, 16'h00D0, S5_CLKOUT5[10], S5_CLKOUT5[11], S5_CLKOUT5[8], S5_CLKOUT5[9], S5_CLKOUT5[6], //bits 15 downto 11 + S5_CLKOUT5[7], S5_CLKOUT5[20], S5_CLKOUT5[13], 2'h0, S5_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S5_CLKOUT5[5], S5_CLKOUT5[21], S5_CLKOUT5[12], S5_CLKOUT5[4]}; //bits 3 downto 0 - rom[102] = {5'h0F, 16'h0003, S5_CLKFBOUT[4], S5_CLKFBOUT[5], S5_CLKFBOUT[3], S5_CLKFBOUT[12], S5_CLKFBOUT[1], //bits 15 downto 11 - S5_CLKFBOUT[2], S5_CLKFBOUT[0], S5_CLKFBOUT[19], S5_CLKFBOUT[18], S5_CLKFBOUT[17], //bits 10 downto 6 - S5_CLKFBOUT[15], S5_CLKFBOUT[16], S5_CLKOUT0[12], S5_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[102] = {5'h0F, 16'h0003, S5_CLKFBOUT[4], S5_CLKFBOUT[5], S5_CLKFBOUT[3], S5_CLKFBOUT[12], S5_CLKFBOUT[1], //bits 15 downto 11 + S5_CLKFBOUT[2], S5_CLKFBOUT[0], S5_CLKFBOUT[19], S5_CLKFBOUT[18], S5_CLKFBOUT[17], //bits 10 downto 6 + S5_CLKFBOUT[15], S5_CLKFBOUT[16], S5_CLKOUT0[12], S5_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[103] = {5'h10, 16'h800C, 1'b0, S5_CLKOUT0[9], S5_CLKOUT0[11], S5_CLKOUT0[10], S5_CLKFBOUT[10], S5_CLKFBOUT[11], //bits 15 downto 10 - S5_CLKFBOUT[9], S5_CLKFBOUT[8], S5_CLKFBOUT[7], S5_CLKFBOUT[6], S5_CLKFBOUT[13], //bits 9 downto 5 - S5_CLKFBOUT[20], 2'h0, S5_CLKFBOUT[21], S5_CLKFBOUT[22]}; //bits 4 downto 0 + rom[103] = {5'h10, 16'h800C, 1'b0, S5_CLKOUT0[9], S5_CLKOUT0[11], S5_CLKOUT0[10], S5_CLKFBOUT[10], S5_CLKFBOUT[11], //bits 15 downto 10 + S5_CLKFBOUT[9], S5_CLKFBOUT[8], S5_CLKFBOUT[7], S5_CLKFBOUT[6], S5_CLKFBOUT[13], //bits 9 downto 5 + S5_CLKFBOUT[20], 2'h0, S5_CLKFBOUT[21], S5_CLKFBOUT[22]}; //bits 4 downto 0 - rom[104] = {5'h11, 16'hFC00, 6'h00, S5_CLKOUT3[3], S5_CLKOUT3[16], S5_CLKOUT2[11], S5_CLKOUT2[1], S5_CLKOUT1[18], //bits 15 downto 6 - S5_CLKOUT1[0], S5_CLKOUT0[6], S5_CLKOUT0[20], S5_CLKOUT0[8], S5_CLKOUT0[7]}; //bits 5 downto 0 + rom[104] = {5'h11, 16'hFC00, 6'h00, S5_CLKOUT3[3], S5_CLKOUT3[16], S5_CLKOUT2[11], S5_CLKOUT2[1], S5_CLKOUT1[18], //bits 15 downto 6 + S5_CLKOUT1[0], S5_CLKOUT0[6], S5_CLKOUT0[20], S5_CLKOUT0[8], S5_CLKOUT0[7]}; //bits 5 downto 0 - rom[105] = {5'h12, 16'hF0FF, 4'h0, S5_CLKOUT5[14], S5_CLKFBOUT[14], S5_CLKOUT4[0], S5_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[105] = {5'h12, 16'hF0FF, 4'h0, S5_CLKOUT5[14], S5_CLKFBOUT[14], S5_CLKOUT4[0], S5_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[106] = {5'h13, 16'h5120, S5_DIVCLK[11], 1'b0, S5_DIVCLK[10], 1'b0, S5_DIVCLK[7], S5_DIVCLK[8], //bits 15 downto 10 - S5_DIVCLK[0], 1'b0, S5_DIVCLK[5], S5_DIVCLK[2], 1'b0, S5_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[106] = {5'h13, 16'h5120, S5_DIVCLK[11], 1'b0, S5_DIVCLK[10], 1'b0, S5_DIVCLK[7], S5_DIVCLK[8], //bits 15 downto 10 + S5_DIVCLK[0], 1'b0, S5_DIVCLK[5], S5_DIVCLK[2], 1'b0, S5_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[107] = {5'h14, 16'h2FFF, S5_LOCK[1], S5_LOCK[2], 1'b0, S5_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[107] = {5'h14, 16'h2FFF, S5_LOCK[1], S5_LOCK[2], 1'b0, S5_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[108] = {5'h15, 16'hBFF4, 1'b0, S5_DIVCLK[12], 10'h000, S5_LOCK[38], 1'b0, S5_LOCK[32], S5_LOCK[39]}; //bits 15 downto 0 + rom[108] = {5'h15, 16'hBFF4, 1'b0, S5_DIVCLK[12], 10'h000, S5_LOCK[38], 1'b0, S5_LOCK[32], S5_LOCK[39]}; //bits 15 downto 0 - rom[109] = {5'h16, 16'h0A55, S5_LOCK[15], S5_LOCK[13], S5_LOCK[27], S5_LOCK[16], 1'b0, S5_LOCK[10], //bits 15 downto 10 - 1'b0, S5_DIVCLK[9], S5_DIVCLK[1], 1'b0, S5_DIVCLK[6], 1'b0, S5_DIVCLK[3], //bits 9 downto 3 - 1'b0, S5_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[109] = {5'h16, 16'h0A55, S5_LOCK[15], S5_LOCK[13], S5_LOCK[27], S5_LOCK[16], 1'b0, S5_LOCK[10], //bits 15 downto 10 + 1'b0, S5_DIVCLK[9], S5_DIVCLK[1], 1'b0, S5_DIVCLK[6], 1'b0, S5_DIVCLK[3], //bits 9 downto 3 + 1'b0, S5_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[110] = {5'h17, 16'hFFD0, 10'h000, S5_LOCK[17], 1'b0, S5_LOCK[8], S5_LOCK[9], S5_LOCK[23], S5_LOCK[22]}; //bits 15 downto 0 + rom[110] = {5'h17, 16'hFFD0, 10'h000, S5_LOCK[17], 1'b0, S5_LOCK[8], S5_LOCK[9], S5_LOCK[23], S5_LOCK[22]}; //bits 15 downto 0 - rom[111] = {5'h18, 16'h1039, S5_DIGITAL_FILT[6], S5_DIGITAL_FILT[7], S5_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S5_DIGITAL_FILT[2], S5_DIGITAL_FILT[1], S5_DIGITAL_FILT[3], S5_DIGITAL_FILT[9], //bits 11 downto 8 - S5_DIGITAL_FILT[8], S5_LOCK[26], 3'h0, S5_LOCK[19], S5_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[111] = {5'h18, 16'h1039, S5_DIGITAL_FILT[6], S5_DIGITAL_FILT[7], S5_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S5_DIGITAL_FILT[2], S5_DIGITAL_FILT[1], S5_DIGITAL_FILT[3], S5_DIGITAL_FILT[9], //bits 11 downto 8 + S5_DIGITAL_FILT[8], S5_LOCK[26], 3'h0, S5_LOCK[19], S5_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[112] = {5'h19, 16'h0000, S5_LOCK[24], S5_LOCK[25], S5_LOCK[21], S5_LOCK[14], S5_LOCK[11], //bits 15 downto 11 - S5_LOCK[12], S5_LOCK[20], S5_LOCK[6], S5_LOCK[35], S5_LOCK[36], //bits 10 downto 6 - S5_LOCK[37], S5_LOCK[3], S5_LOCK[33], S5_LOCK[31], S5_LOCK[34], S5_LOCK[30]}; //bits 5 downto 0 + rom[112] = {5'h19, 16'h0000, S5_LOCK[24], S5_LOCK[25], S5_LOCK[21], S5_LOCK[14], S5_LOCK[11], //bits 15 downto 11 + S5_LOCK[12], S5_LOCK[20], S5_LOCK[6], S5_LOCK[35], S5_LOCK[36], //bits 10 downto 6 + S5_LOCK[37], S5_LOCK[3], S5_LOCK[33], S5_LOCK[31], S5_LOCK[34], S5_LOCK[30]}; //bits 5 downto 0 - rom[113] = {5'h1A, 16'hFFFC, 14'h0000, S5_LOCK[28], S5_LOCK[29]}; //bits 15 downto 0 + rom[113] = {5'h1A, 16'hFFFC, 14'h0000, S5_LOCK[28], S5_LOCK[29]}; //bits 15 downto 0 - rom[114] = {5'h1D, 16'h2FFF, S5_LOCK[7], S5_LOCK[4], 1'b0, S5_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[114] = {5'h1D, 16'h2FFF, S5_LOCK[7], S5_LOCK[4], 1'b0, S5_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 6 Initialization //*********************************************************************** rom[115] = {5'h05, 16'h50FF, S6_CLKOUT0[19], 1'b0, S6_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S6_CLKOUT0[16], S6_CLKOUT0[17], S6_CLKOUT0[15], S6_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S6_CLKOUT0[16], S6_CLKOUT0[17], S6_CLKOUT0[15], S6_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[116] = {5'h06, 16'h010B, S6_CLKOUT1[4], S6_CLKOUT1[5], S6_CLKOUT1[3], S6_CLKOUT1[12], //bits 15 down to 12 - S6_CLKOUT1[1], S6_CLKOUT1[2], S6_CLKOUT1[19], 1'b0, S6_CLKOUT1[17], S6_CLKOUT1[16], //bits 11 down to 6 - S6_CLKOUT1[14], S6_CLKOUT1[15], 1'b0, S6_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[116] = {5'h06, 16'h010B, S6_CLKOUT1[4], S6_CLKOUT1[5], S6_CLKOUT1[3], S6_CLKOUT1[12], //bits 15 down to 12 + S6_CLKOUT1[1], S6_CLKOUT1[2], S6_CLKOUT1[19], 1'b0, S6_CLKOUT1[17], S6_CLKOUT1[16], //bits 11 down to 6 + S6_CLKOUT1[14], S6_CLKOUT1[15], 1'b0, S6_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[117] = {5'h07, 16'hE02C, 3'h0, S6_CLKOUT1[11], S6_CLKOUT1[9], S6_CLKOUT1[10], //bits 15 down to 10 - S6_CLKOUT1[8], S6_CLKOUT1[7], S6_CLKOUT1[6], S6_CLKOUT1[20], 1'b0, S6_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S6_CLKOUT1[21], S6_CLKOUT1[22]}; //bits 3 down to 0 + rom[117] = {5'h07, 16'hE02C, 3'h0, S6_CLKOUT1[11], S6_CLKOUT1[9], S6_CLKOUT1[10], //bits 15 down to 10 + S6_CLKOUT1[8], S6_CLKOUT1[7], S6_CLKOUT1[6], S6_CLKOUT1[20], 1'b0, S6_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S6_CLKOUT1[21], S6_CLKOUT1[22]}; //bits 3 down to 0 - rom[118] = {5'h08, 16'h4001, S6_CLKOUT2[22], 1'b0, S6_CLKOUT2[5], S6_CLKOUT2[21], //bits 15 downto 12 - S6_CLKOUT2[12], S6_CLKOUT2[4], S6_CLKOUT2[3], S6_CLKOUT2[2], S6_CLKOUT2[0], S6_CLKOUT2[19], //bits 11 down to 6 - S6_CLKOUT2[17], S6_CLKOUT2[18], S6_CLKOUT2[15], S6_CLKOUT2[16], S6_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[118] = {5'h08, 16'h4001, S6_CLKOUT2[22], 1'b0, S6_CLKOUT2[5], S6_CLKOUT2[21], //bits 15 downto 12 + S6_CLKOUT2[12], S6_CLKOUT2[4], S6_CLKOUT2[3], S6_CLKOUT2[2], S6_CLKOUT2[0], S6_CLKOUT2[19], //bits 11 down to 6 + S6_CLKOUT2[17], S6_CLKOUT2[18], S6_CLKOUT2[15], S6_CLKOUT2[16], S6_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[119] = {5'h09, 16'h0D03, S6_CLKOUT3[14], S6_CLKOUT3[15], S6_CLKOUT0[21], S6_CLKOUT0[22], 2'h0, S6_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S6_CLKOUT2[9], S6_CLKOUT2[8], S6_CLKOUT2[6], S6_CLKOUT2[7], S6_CLKOUT2[13], S6_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[119] = {5'h09, 16'h0D03, S6_CLKOUT3[14], S6_CLKOUT3[15], S6_CLKOUT0[21], S6_CLKOUT0[22], 2'h0, S6_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S6_CLKOUT2[9], S6_CLKOUT2[8], S6_CLKOUT2[6], S6_CLKOUT2[7], S6_CLKOUT2[13], S6_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[120] = {5'h0A, 16'hB001, 1'b0, S6_CLKOUT3[13], 2'h0, S6_CLKOUT3[21], S6_CLKOUT3[22], S6_CLKOUT3[5], S6_CLKOUT3[4], //bits 15 downto 8 - S6_CLKOUT3[12], S6_CLKOUT3[2], S6_CLKOUT3[0], S6_CLKOUT3[1], S6_CLKOUT3[18], S6_CLKOUT3[19], //bits 7 downto 2 - S6_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[120] = {5'h0A, 16'hB001, 1'b0, S6_CLKOUT3[13], 2'h0, S6_CLKOUT3[21], S6_CLKOUT3[22], S6_CLKOUT3[5], S6_CLKOUT3[4], //bits 15 downto 8 + S6_CLKOUT3[12], S6_CLKOUT3[2], S6_CLKOUT3[0], S6_CLKOUT3[1], S6_CLKOUT3[18], S6_CLKOUT3[19], //bits 7 downto 2 + S6_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[121] = {5'h0B, 16'h0110, S6_CLKOUT0[5], S6_CLKOUT4[19], S6_CLKOUT4[14], S6_CLKOUT4[17], //bits 15 downto 12 - S6_CLKOUT4[15], S6_CLKOUT4[16], S6_CLKOUT0[4], 1'b0, S6_CLKOUT3[11], S6_CLKOUT3[10], //bits 11 downto 6 - S6_CLKOUT3[9], 1'b0, S6_CLKOUT3[7], S6_CLKOUT3[8], S6_CLKOUT3[20], S6_CLKOUT3[6]}; //bits 5 downto 0 + rom[121] = {5'h0B, 16'h0110, S6_CLKOUT0[5], S6_CLKOUT4[19], S6_CLKOUT4[14], S6_CLKOUT4[17], //bits 15 downto 12 + S6_CLKOUT4[15], S6_CLKOUT4[16], S6_CLKOUT0[4], 1'b0, S6_CLKOUT3[11], S6_CLKOUT3[10], //bits 11 downto 6 + S6_CLKOUT3[9], 1'b0, S6_CLKOUT3[7], S6_CLKOUT3[8], S6_CLKOUT3[20], S6_CLKOUT3[6]}; //bits 5 downto 0 - rom[122] = {5'h0C, 16'h0B00, S6_CLKOUT4[7], S6_CLKOUT4[8], S6_CLKOUT4[20], S6_CLKOUT4[6], 1'b0, S6_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S6_CLKOUT4[22], S6_CLKOUT4[21], S6_CLKOUT4[4], S6_CLKOUT4[5], S6_CLKOUT4[3], //bits 9 downto 3 - S6_CLKOUT4[12], S6_CLKOUT4[1], S6_CLKOUT4[2]}; //bits 2 downto 0 + rom[122] = {5'h0C, 16'h0B00, S6_CLKOUT4[7], S6_CLKOUT4[8], S6_CLKOUT4[20], S6_CLKOUT4[6], 1'b0, S6_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S6_CLKOUT4[22], S6_CLKOUT4[21], S6_CLKOUT4[4], S6_CLKOUT4[5], S6_CLKOUT4[3], //bits 9 downto 3 + S6_CLKOUT4[12], S6_CLKOUT4[1], S6_CLKOUT4[2]}; //bits 2 downto 0 - rom[123] = {5'h0D, 16'h0008, S6_CLKOUT5[2], S6_CLKOUT5[3], S6_CLKOUT5[0], S6_CLKOUT5[1], S6_CLKOUT5[18], //bits 15 downto 11 - S6_CLKOUT5[19], S6_CLKOUT5[17], S6_CLKOUT5[16], S6_CLKOUT5[15], S6_CLKOUT0[3], //bits 10 downto 6 - S6_CLKOUT0[0], S6_CLKOUT0[2], 1'b0, S6_CLKOUT4[11], S6_CLKOUT4[9], S6_CLKOUT4[10]}; //bits 5 downto 0 + rom[123] = {5'h0D, 16'h0008, S6_CLKOUT5[2], S6_CLKOUT5[3], S6_CLKOUT5[0], S6_CLKOUT5[1], S6_CLKOUT5[18], //bits 15 downto 11 + S6_CLKOUT5[19], S6_CLKOUT5[17], S6_CLKOUT5[16], S6_CLKOUT5[15], S6_CLKOUT0[3], //bits 10 downto 6 + S6_CLKOUT0[0], S6_CLKOUT0[2], 1'b0, S6_CLKOUT4[11], S6_CLKOUT4[9], S6_CLKOUT4[10]}; //bits 5 downto 0 - rom[124] = {5'h0E, 16'h00D0, S6_CLKOUT5[10], S6_CLKOUT5[11], S6_CLKOUT5[8], S6_CLKOUT5[9], S6_CLKOUT5[6], //bits 15 downto 11 - S6_CLKOUT5[7], S6_CLKOUT5[20], S6_CLKOUT5[13], 2'h0, S6_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S6_CLKOUT5[5], S6_CLKOUT5[21], S6_CLKOUT5[12], S6_CLKOUT5[4]}; //bits 3 downto 0 + rom[124] = {5'h0E, 16'h00D0, S6_CLKOUT5[10], S6_CLKOUT5[11], S6_CLKOUT5[8], S6_CLKOUT5[9], S6_CLKOUT5[6], //bits 15 downto 11 + S6_CLKOUT5[7], S6_CLKOUT5[20], S6_CLKOUT5[13], 2'h0, S6_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S6_CLKOUT5[5], S6_CLKOUT5[21], S6_CLKOUT5[12], S6_CLKOUT5[4]}; //bits 3 downto 0 - rom[125] = {5'h0F, 16'h0003, S6_CLKFBOUT[4], S6_CLKFBOUT[5], S6_CLKFBOUT[3], S6_CLKFBOUT[12], S6_CLKFBOUT[1], //bits 15 downto 11 - S6_CLKFBOUT[2], S6_CLKFBOUT[0], S6_CLKFBOUT[19], S6_CLKFBOUT[18], S6_CLKFBOUT[17], //bits 10 downto 6 - S6_CLKFBOUT[15], S6_CLKFBOUT[16], S6_CLKOUT0[12], S6_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[125] = {5'h0F, 16'h0003, S6_CLKFBOUT[4], S6_CLKFBOUT[5], S6_CLKFBOUT[3], S6_CLKFBOUT[12], S6_CLKFBOUT[1], //bits 15 downto 11 + S6_CLKFBOUT[2], S6_CLKFBOUT[0], S6_CLKFBOUT[19], S6_CLKFBOUT[18], S6_CLKFBOUT[17], //bits 10 downto 6 + S6_CLKFBOUT[15], S6_CLKFBOUT[16], S6_CLKOUT0[12], S6_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[126] = {5'h10, 16'h800C, 1'b0, S6_CLKOUT0[9], S6_CLKOUT0[11], S6_CLKOUT0[10], S6_CLKFBOUT[10], S6_CLKFBOUT[11], //bits 15 downto 10 - S6_CLKFBOUT[9], S6_CLKFBOUT[8], S6_CLKFBOUT[7], S6_CLKFBOUT[6], S6_CLKFBOUT[13], //bits 9 downto 5 - S6_CLKFBOUT[20], 2'h0, S6_CLKFBOUT[21], S6_CLKFBOUT[22]}; //bits 4 downto 0 + rom[126] = {5'h10, 16'h800C, 1'b0, S6_CLKOUT0[9], S6_CLKOUT0[11], S6_CLKOUT0[10], S6_CLKFBOUT[10], S6_CLKFBOUT[11], //bits 15 downto 10 + S6_CLKFBOUT[9], S6_CLKFBOUT[8], S6_CLKFBOUT[7], S6_CLKFBOUT[6], S6_CLKFBOUT[13], //bits 9 downto 5 + S6_CLKFBOUT[20], 2'h0, S6_CLKFBOUT[21], S6_CLKFBOUT[22]}; //bits 4 downto 0 - rom[127] = {5'h11, 16'hFC00, 6'h00, S6_CLKOUT3[3], S6_CLKOUT3[16], S6_CLKOUT2[11], S6_CLKOUT2[1], S6_CLKOUT1[18], //bits 15 downto 6 - S6_CLKOUT1[0], S6_CLKOUT0[6], S6_CLKOUT0[20], S6_CLKOUT0[8], S6_CLKOUT0[7]}; //bits 5 downto 0 + rom[127] = {5'h11, 16'hFC00, 6'h00, S6_CLKOUT3[3], S6_CLKOUT3[16], S6_CLKOUT2[11], S6_CLKOUT2[1], S6_CLKOUT1[18], //bits 15 downto 6 + S6_CLKOUT1[0], S6_CLKOUT0[6], S6_CLKOUT0[20], S6_CLKOUT0[8], S6_CLKOUT0[7]}; //bits 5 downto 0 - rom[128] = {5'h12, 16'hF0FF, 4'h0, S6_CLKOUT5[14], S6_CLKFBOUT[14], S6_CLKOUT4[0], S6_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[128] = {5'h12, 16'hF0FF, 4'h0, S6_CLKOUT5[14], S6_CLKFBOUT[14], S6_CLKOUT4[0], S6_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[129] = {5'h13, 16'h5120, S6_DIVCLK[11], 1'b0, S6_DIVCLK[10], 1'b0, S6_DIVCLK[7], S6_DIVCLK[8], //bits 15 downto 10 - S6_DIVCLK[0], 1'b0, S6_DIVCLK[5], S6_DIVCLK[2], 1'b0, S6_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[129] = {5'h13, 16'h5120, S6_DIVCLK[11], 1'b0, S6_DIVCLK[10], 1'b0, S6_DIVCLK[7], S6_DIVCLK[8], //bits 15 downto 10 + S6_DIVCLK[0], 1'b0, S6_DIVCLK[5], S6_DIVCLK[2], 1'b0, S6_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[130] = {5'h14, 16'h2FFF, S6_LOCK[1], S6_LOCK[2], 1'b0, S6_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[130] = {5'h14, 16'h2FFF, S6_LOCK[1], S6_LOCK[2], 1'b0, S6_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[131] = {5'h15, 16'hBFF4, 1'b0, S6_DIVCLK[12], 10'h000, S6_LOCK[38], 1'b0, S6_LOCK[32], S6_LOCK[39]}; //bits 15 downto 0 + rom[131] = {5'h15, 16'hBFF4, 1'b0, S6_DIVCLK[12], 10'h000, S6_LOCK[38], 1'b0, S6_LOCK[32], S6_LOCK[39]}; //bits 15 downto 0 - rom[132] = {5'h16, 16'h0A55, S6_LOCK[15], S6_LOCK[13], S6_LOCK[27], S6_LOCK[16], 1'b0, S6_LOCK[10], //bits 15 downto 10 - 1'b0, S6_DIVCLK[9], S6_DIVCLK[1], 1'b0, S6_DIVCLK[6], 1'b0, S6_DIVCLK[3], //bits 9 downto 3 - 1'b0, S6_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[132] = {5'h16, 16'h0A55, S6_LOCK[15], S6_LOCK[13], S6_LOCK[27], S6_LOCK[16], 1'b0, S6_LOCK[10], //bits 15 downto 10 + 1'b0, S6_DIVCLK[9], S6_DIVCLK[1], 1'b0, S6_DIVCLK[6], 1'b0, S6_DIVCLK[3], //bits 9 downto 3 + 1'b0, S6_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[133] = {5'h17, 16'hFFD0, 10'h000, S6_LOCK[17], 1'b0, S6_LOCK[8], S6_LOCK[9], S6_LOCK[23], S6_LOCK[22]}; //bits 15 downto 0 + rom[133] = {5'h17, 16'hFFD0, 10'h000, S6_LOCK[17], 1'b0, S6_LOCK[8], S6_LOCK[9], S6_LOCK[23], S6_LOCK[22]}; //bits 15 downto 0 - rom[134] = {5'h18, 16'h1039, S6_DIGITAL_FILT[6], S6_DIGITAL_FILT[7], S6_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S6_DIGITAL_FILT[2], S6_DIGITAL_FILT[1], S6_DIGITAL_FILT[3], S6_DIGITAL_FILT[9], //bits 11 downto 8 - S6_DIGITAL_FILT[8], S6_LOCK[26], 3'h0, S6_LOCK[19], S6_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[134] = {5'h18, 16'h1039, S6_DIGITAL_FILT[6], S6_DIGITAL_FILT[7], S6_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S6_DIGITAL_FILT[2], S6_DIGITAL_FILT[1], S6_DIGITAL_FILT[3], S6_DIGITAL_FILT[9], //bits 11 downto 8 + S6_DIGITAL_FILT[8], S6_LOCK[26], 3'h0, S6_LOCK[19], S6_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[135] = {5'h19, 16'h0000, S6_LOCK[24], S6_LOCK[25], S6_LOCK[21], S6_LOCK[14], S6_LOCK[11], //bits 15 downto 11 - S6_LOCK[12], S6_LOCK[20], S6_LOCK[6], S6_LOCK[35], S6_LOCK[36], //bits 10 downto 6 - S6_LOCK[37], S6_LOCK[3], S6_LOCK[33], S6_LOCK[31], S6_LOCK[34], S6_LOCK[30]}; //bits 5 downto 0 + rom[135] = {5'h19, 16'h0000, S6_LOCK[24], S6_LOCK[25], S6_LOCK[21], S6_LOCK[14], S6_LOCK[11], //bits 15 downto 11 + S6_LOCK[12], S6_LOCK[20], S6_LOCK[6], S6_LOCK[35], S6_LOCK[36], //bits 10 downto 6 + S6_LOCK[37], S6_LOCK[3], S6_LOCK[33], S6_LOCK[31], S6_LOCK[34], S6_LOCK[30]}; //bits 5 downto 0 - rom[136] = {5'h1A, 16'hFFFC, 14'h0000, S6_LOCK[28], S6_LOCK[29]}; //bits 15 downto 0 + rom[136] = {5'h1A, 16'hFFFC, 14'h0000, S6_LOCK[28], S6_LOCK[29]}; //bits 15 downto 0 - rom[137] = {5'h1D, 16'h2FFF, S6_LOCK[7], S6_LOCK[4], 1'b0, S6_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[137] = {5'h1D, 16'h2FFF, S6_LOCK[7], S6_LOCK[4], 1'b0, S6_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 7 Initialization //*********************************************************************** rom[138] = {5'h05, 16'h50FF, S7_CLKOUT0[19], 1'b0, S7_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S7_CLKOUT0[16], S7_CLKOUT0[17], S7_CLKOUT0[15], S7_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S7_CLKOUT0[16], S7_CLKOUT0[17], S7_CLKOUT0[15], S7_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[139] = {5'h06, 16'h010B, S7_CLKOUT1[4], S7_CLKOUT1[5], S7_CLKOUT1[3], S7_CLKOUT1[12], //bits 15 down to 12 - S7_CLKOUT1[1], S7_CLKOUT1[2], S7_CLKOUT1[19], 1'b0, S7_CLKOUT1[17], S7_CLKOUT1[16], //bits 11 down to 6 - S7_CLKOUT1[14], S7_CLKOUT1[15], 1'b0, S7_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[139] = {5'h06, 16'h010B, S7_CLKOUT1[4], S7_CLKOUT1[5], S7_CLKOUT1[3], S7_CLKOUT1[12], //bits 15 down to 12 + S7_CLKOUT1[1], S7_CLKOUT1[2], S7_CLKOUT1[19], 1'b0, S7_CLKOUT1[17], S7_CLKOUT1[16], //bits 11 down to 6 + S7_CLKOUT1[14], S7_CLKOUT1[15], 1'b0, S7_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[140] = {5'h07, 16'hE02C, 3'h0, S7_CLKOUT1[11], S7_CLKOUT1[9], S7_CLKOUT1[10], //bits 15 down to 10 - S7_CLKOUT1[8], S7_CLKOUT1[7], S7_CLKOUT1[6], S7_CLKOUT1[20], 1'b0, S7_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S7_CLKOUT1[21], S7_CLKOUT1[22]}; //bits 3 down to 0 + rom[140] = {5'h07, 16'hE02C, 3'h0, S7_CLKOUT1[11], S7_CLKOUT1[9], S7_CLKOUT1[10], //bits 15 down to 10 + S7_CLKOUT1[8], S7_CLKOUT1[7], S7_CLKOUT1[6], S7_CLKOUT1[20], 1'b0, S7_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S7_CLKOUT1[21], S7_CLKOUT1[22]}; //bits 3 down to 0 - rom[141] = {5'h08, 16'h4001, S7_CLKOUT2[22], 1'b0, S7_CLKOUT2[5], S7_CLKOUT2[21], //bits 15 downto 12 - S7_CLKOUT2[12], S7_CLKOUT2[4], S7_CLKOUT2[3], S7_CLKOUT2[2], S7_CLKOUT2[0], S7_CLKOUT2[19], //bits 11 down to 6 - S7_CLKOUT2[17], S7_CLKOUT2[18], S7_CLKOUT2[15], S7_CLKOUT2[16], S7_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[141] = {5'h08, 16'h4001, S7_CLKOUT2[22], 1'b0, S7_CLKOUT2[5], S7_CLKOUT2[21], //bits 15 downto 12 + S7_CLKOUT2[12], S7_CLKOUT2[4], S7_CLKOUT2[3], S7_CLKOUT2[2], S7_CLKOUT2[0], S7_CLKOUT2[19], //bits 11 down to 6 + S7_CLKOUT2[17], S7_CLKOUT2[18], S7_CLKOUT2[15], S7_CLKOUT2[16], S7_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[142] = {5'h09, 16'h0D03, S7_CLKOUT3[14], S7_CLKOUT3[15], S7_CLKOUT0[21], S7_CLKOUT0[22], 2'h0, S7_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S7_CLKOUT2[9], S7_CLKOUT2[8], S7_CLKOUT2[6], S7_CLKOUT2[7], S7_CLKOUT2[13], S7_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[142] = {5'h09, 16'h0D03, S7_CLKOUT3[14], S7_CLKOUT3[15], S7_CLKOUT0[21], S7_CLKOUT0[22], 2'h0, S7_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S7_CLKOUT2[9], S7_CLKOUT2[8], S7_CLKOUT2[6], S7_CLKOUT2[7], S7_CLKOUT2[13], S7_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[143] = {5'h0A, 16'hB001, 1'b0, S7_CLKOUT3[13], 2'h0, S7_CLKOUT3[21], S7_CLKOUT3[22], S7_CLKOUT3[5], S7_CLKOUT3[4], //bits 15 downto 8 - S7_CLKOUT3[12], S7_CLKOUT3[2], S7_CLKOUT3[0], S7_CLKOUT3[1], S7_CLKOUT3[18], S7_CLKOUT3[19], //bits 7 downto 2 - S7_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[143] = {5'h0A, 16'hB001, 1'b0, S7_CLKOUT3[13], 2'h0, S7_CLKOUT3[21], S7_CLKOUT3[22], S7_CLKOUT3[5], S7_CLKOUT3[4], //bits 15 downto 8 + S7_CLKOUT3[12], S7_CLKOUT3[2], S7_CLKOUT3[0], S7_CLKOUT3[1], S7_CLKOUT3[18], S7_CLKOUT3[19], //bits 7 downto 2 + S7_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[144] = {5'h0B, 16'h0110, S7_CLKOUT0[5], S7_CLKOUT4[19], S7_CLKOUT4[14], S7_CLKOUT4[17], //bits 15 downto 12 - S7_CLKOUT4[15], S7_CLKOUT4[16], S7_CLKOUT0[4], 1'b0, S7_CLKOUT3[11], S7_CLKOUT3[10], //bits 11 downto 6 - S7_CLKOUT3[9], 1'b0, S7_CLKOUT3[7], S7_CLKOUT3[8], S7_CLKOUT3[20], S7_CLKOUT3[6]}; //bits 5 downto 0 + rom[144] = {5'h0B, 16'h0110, S7_CLKOUT0[5], S7_CLKOUT4[19], S7_CLKOUT4[14], S7_CLKOUT4[17], //bits 15 downto 12 + S7_CLKOUT4[15], S7_CLKOUT4[16], S7_CLKOUT0[4], 1'b0, S7_CLKOUT3[11], S7_CLKOUT3[10], //bits 11 downto 6 + S7_CLKOUT3[9], 1'b0, S7_CLKOUT3[7], S7_CLKOUT3[8], S7_CLKOUT3[20], S7_CLKOUT3[6]}; //bits 5 downto 0 - rom[145] = {5'h0C, 16'h0B00, S7_CLKOUT4[7], S7_CLKOUT4[8], S7_CLKOUT4[20], S7_CLKOUT4[6], 1'b0, S7_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S7_CLKOUT4[22], S7_CLKOUT4[21], S7_CLKOUT4[4], S7_CLKOUT4[5], S7_CLKOUT4[3], //bits 9 downto 3 - S7_CLKOUT4[12], S7_CLKOUT4[1], S7_CLKOUT4[2]}; //bits 2 downto 0 + rom[145] = {5'h0C, 16'h0B00, S7_CLKOUT4[7], S7_CLKOUT4[8], S7_CLKOUT4[20], S7_CLKOUT4[6], 1'b0, S7_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S7_CLKOUT4[22], S7_CLKOUT4[21], S7_CLKOUT4[4], S7_CLKOUT4[5], S7_CLKOUT4[3], //bits 9 downto 3 + S7_CLKOUT4[12], S7_CLKOUT4[1], S7_CLKOUT4[2]}; //bits 2 downto 0 - rom[146] = {5'h0D, 16'h0008, S7_CLKOUT5[2], S7_CLKOUT5[3], S7_CLKOUT5[0], S7_CLKOUT5[1], S7_CLKOUT5[18], //bits 15 downto 11 - S7_CLKOUT5[19], S7_CLKOUT5[17], S7_CLKOUT5[16], S7_CLKOUT5[15], S7_CLKOUT0[3], //bits 10 downto 6 - S7_CLKOUT0[0], S7_CLKOUT0[2], 1'b0, S7_CLKOUT4[11], S7_CLKOUT4[9], S7_CLKOUT4[10]}; //bits 5 downto 0 + rom[146] = {5'h0D, 16'h0008, S7_CLKOUT5[2], S7_CLKOUT5[3], S7_CLKOUT5[0], S7_CLKOUT5[1], S7_CLKOUT5[18], //bits 15 downto 11 + S7_CLKOUT5[19], S7_CLKOUT5[17], S7_CLKOUT5[16], S7_CLKOUT5[15], S7_CLKOUT0[3], //bits 10 downto 6 + S7_CLKOUT0[0], S7_CLKOUT0[2], 1'b0, S7_CLKOUT4[11], S7_CLKOUT4[9], S7_CLKOUT4[10]}; //bits 5 downto 0 - rom[147] = {5'h0E, 16'h00D0, S7_CLKOUT5[10], S7_CLKOUT5[11], S7_CLKOUT5[8], S7_CLKOUT5[9], S7_CLKOUT5[6], //bits 15 downto 11 - S7_CLKOUT5[7], S7_CLKOUT5[20], S7_CLKOUT5[13], 2'h0, S7_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S7_CLKOUT5[5], S7_CLKOUT5[21], S7_CLKOUT5[12], S7_CLKOUT5[4]}; //bits 3 downto 0 + rom[147] = {5'h0E, 16'h00D0, S7_CLKOUT5[10], S7_CLKOUT5[11], S7_CLKOUT5[8], S7_CLKOUT5[9], S7_CLKOUT5[6], //bits 15 downto 11 + S7_CLKOUT5[7], S7_CLKOUT5[20], S7_CLKOUT5[13], 2'h0, S7_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S7_CLKOUT5[5], S7_CLKOUT5[21], S7_CLKOUT5[12], S7_CLKOUT5[4]}; //bits 3 downto 0 - rom[148] = {5'h0F, 16'h0003, S7_CLKFBOUT[4], S7_CLKFBOUT[5], S7_CLKFBOUT[3], S7_CLKFBOUT[12], S7_CLKFBOUT[1], //bits 15 downto 11 - S7_CLKFBOUT[2], S7_CLKFBOUT[0], S7_CLKFBOUT[19], S7_CLKFBOUT[18], S7_CLKFBOUT[17], //bits 10 downto 6 - S7_CLKFBOUT[15], S7_CLKFBOUT[16], S7_CLKOUT0[12], S7_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[148] = {5'h0F, 16'h0003, S7_CLKFBOUT[4], S7_CLKFBOUT[5], S7_CLKFBOUT[3], S7_CLKFBOUT[12], S7_CLKFBOUT[1], //bits 15 downto 11 + S7_CLKFBOUT[2], S7_CLKFBOUT[0], S7_CLKFBOUT[19], S7_CLKFBOUT[18], S7_CLKFBOUT[17], //bits 10 downto 6 + S7_CLKFBOUT[15], S7_CLKFBOUT[16], S7_CLKOUT0[12], S7_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[149] = {5'h10, 16'h800C, 1'b0, S7_CLKOUT0[9], S7_CLKOUT0[11], S7_CLKOUT0[10], S7_CLKFBOUT[10], S7_CLKFBOUT[11], //bits 15 downto 10 - S7_CLKFBOUT[9], S7_CLKFBOUT[8], S7_CLKFBOUT[7], S7_CLKFBOUT[6], S7_CLKFBOUT[13], //bits 9 downto 5 - S7_CLKFBOUT[20], 2'h0, S7_CLKFBOUT[21], S7_CLKFBOUT[22]}; //bits 4 downto 0 + rom[149] = {5'h10, 16'h800C, 1'b0, S7_CLKOUT0[9], S7_CLKOUT0[11], S7_CLKOUT0[10], S7_CLKFBOUT[10], S7_CLKFBOUT[11], //bits 15 downto 10 + S7_CLKFBOUT[9], S7_CLKFBOUT[8], S7_CLKFBOUT[7], S7_CLKFBOUT[6], S7_CLKFBOUT[13], //bits 9 downto 5 + S7_CLKFBOUT[20], 2'h0, S7_CLKFBOUT[21], S7_CLKFBOUT[22]}; //bits 4 downto 0 - rom[150] = {5'h11, 16'hFC00, 6'h00, S7_CLKOUT3[3], S7_CLKOUT3[16], S7_CLKOUT2[11], S7_CLKOUT2[1], S7_CLKOUT1[18], //bits 15 downto 6 - S7_CLKOUT1[0], S7_CLKOUT0[6], S7_CLKOUT0[20], S7_CLKOUT0[8], S7_CLKOUT0[7]}; //bits 5 downto 0 + rom[150] = {5'h11, 16'hFC00, 6'h00, S7_CLKOUT3[3], S7_CLKOUT3[16], S7_CLKOUT2[11], S7_CLKOUT2[1], S7_CLKOUT1[18], //bits 15 downto 6 + S7_CLKOUT1[0], S7_CLKOUT0[6], S7_CLKOUT0[20], S7_CLKOUT0[8], S7_CLKOUT0[7]}; //bits 5 downto 0 - rom[151] = {5'h12, 16'hF0FF, 4'h0, S7_CLKOUT5[14], S7_CLKFBOUT[14], S7_CLKOUT4[0], S7_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[151] = {5'h12, 16'hF0FF, 4'h0, S7_CLKOUT5[14], S7_CLKFBOUT[14], S7_CLKOUT4[0], S7_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[152] = {5'h13, 16'h5120, S7_DIVCLK[11], 1'b0, S7_DIVCLK[10], 1'b0, S7_DIVCLK[7], S7_DIVCLK[8], //bits 15 downto 10 - S7_DIVCLK[0], 1'b0, S7_DIVCLK[5], S7_DIVCLK[2], 1'b0, S7_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[152] = {5'h13, 16'h5120, S7_DIVCLK[11], 1'b0, S7_DIVCLK[10], 1'b0, S7_DIVCLK[7], S7_DIVCLK[8], //bits 15 downto 10 + S7_DIVCLK[0], 1'b0, S7_DIVCLK[5], S7_DIVCLK[2], 1'b0, S7_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[153] = {5'h14, 16'h2FFF, S7_LOCK[1], S7_LOCK[2], 1'b0, S7_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[153] = {5'h14, 16'h2FFF, S7_LOCK[1], S7_LOCK[2], 1'b0, S7_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[154] = {5'h15, 16'hBFF4, 1'b0, S7_DIVCLK[12], 10'h000, S7_LOCK[38], 1'b0, S7_LOCK[32], S7_LOCK[39]}; //bits 15 downto 0 + rom[154] = {5'h15, 16'hBFF4, 1'b0, S7_DIVCLK[12], 10'h000, S7_LOCK[38], 1'b0, S7_LOCK[32], S7_LOCK[39]}; //bits 15 downto 0 - rom[155] = {5'h16, 16'h0A55, S7_LOCK[15], S7_LOCK[13], S7_LOCK[27], S7_LOCK[16], 1'b0, S7_LOCK[10], //bits 15 downto 10 - 1'b0, S7_DIVCLK[9], S7_DIVCLK[1], 1'b0, S7_DIVCLK[6], 1'b0, S7_DIVCLK[3], //bits 9 downto 3 - 1'b0, S7_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[155] = {5'h16, 16'h0A55, S7_LOCK[15], S7_LOCK[13], S7_LOCK[27], S7_LOCK[16], 1'b0, S7_LOCK[10], //bits 15 downto 10 + 1'b0, S7_DIVCLK[9], S7_DIVCLK[1], 1'b0, S7_DIVCLK[6], 1'b0, S7_DIVCLK[3], //bits 9 downto 3 + 1'b0, S7_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[156] = {5'h17, 16'hFFD0, 10'h000, S7_LOCK[17], 1'b0, S7_LOCK[8], S7_LOCK[9], S7_LOCK[23], S7_LOCK[22]}; //bits 15 downto 0 + rom[156] = {5'h17, 16'hFFD0, 10'h000, S7_LOCK[17], 1'b0, S7_LOCK[8], S7_LOCK[9], S7_LOCK[23], S7_LOCK[22]}; //bits 15 downto 0 - rom[157] = {5'h18, 16'h1039, S7_DIGITAL_FILT[6], S7_DIGITAL_FILT[7], S7_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S7_DIGITAL_FILT[2], S7_DIGITAL_FILT[1], S7_DIGITAL_FILT[3], S7_DIGITAL_FILT[9], //bits 11 downto 8 - S7_DIGITAL_FILT[8], S7_LOCK[26], 3'h0, S7_LOCK[19], S7_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[157] = {5'h18, 16'h1039, S7_DIGITAL_FILT[6], S7_DIGITAL_FILT[7], S7_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S7_DIGITAL_FILT[2], S7_DIGITAL_FILT[1], S7_DIGITAL_FILT[3], S7_DIGITAL_FILT[9], //bits 11 downto 8 + S7_DIGITAL_FILT[8], S7_LOCK[26], 3'h0, S7_LOCK[19], S7_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[158] = {5'h19, 16'h0000, S7_LOCK[24], S7_LOCK[25], S7_LOCK[21], S7_LOCK[14], S7_LOCK[11], //bits 15 downto 11 - S7_LOCK[12], S7_LOCK[20], S7_LOCK[6], S7_LOCK[35], S7_LOCK[36], //bits 10 downto 6 - S7_LOCK[37], S7_LOCK[3], S7_LOCK[33], S7_LOCK[31], S7_LOCK[34], S7_LOCK[30]}; //bits 5 downto 0 + rom[158] = {5'h19, 16'h0000, S7_LOCK[24], S7_LOCK[25], S7_LOCK[21], S7_LOCK[14], S7_LOCK[11], //bits 15 downto 11 + S7_LOCK[12], S7_LOCK[20], S7_LOCK[6], S7_LOCK[35], S7_LOCK[36], //bits 10 downto 6 + S7_LOCK[37], S7_LOCK[3], S7_LOCK[33], S7_LOCK[31], S7_LOCK[34], S7_LOCK[30]}; //bits 5 downto 0 - rom[159] = {5'h1A, 16'hFFFC, 14'h0000, S7_LOCK[28], S7_LOCK[29]}; //bits 15 downto 0 + rom[159] = {5'h1A, 16'hFFFC, 14'h0000, S7_LOCK[28], S7_LOCK[29]}; //bits 15 downto 0 - rom[160] = {5'h1D, 16'h2FFF, S7_LOCK[7], S7_LOCK[4], 1'b0, S7_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[160] = {5'h1D, 16'h2FFF, S7_LOCK[7], S7_LOCK[4], 1'b0, S7_LOCK[5], 12'h000}; //bits 15 downto 0 //*********************************************************************** // State 8 Initialization //*********************************************************************** rom[161] = {5'h05, 16'h50FF, S8_CLKOUT0[19], 1'b0, S8_CLKOUT0[18], 1'b0,//bits 15 down to 12 - S8_CLKOUT0[16], S8_CLKOUT0[17], S8_CLKOUT0[15], S8_CLKOUT0[14], 8'h00};//bits 11 downto 0 + S8_CLKOUT0[16], S8_CLKOUT0[17], S8_CLKOUT0[15], S8_CLKOUT0[14], 8'h00};//bits 11 downto 0 - rom[162] = {5'h06, 16'h010B, S8_CLKOUT1[4], S8_CLKOUT1[5], S8_CLKOUT1[3], S8_CLKOUT1[12], //bits 15 down to 12 - S8_CLKOUT1[1], S8_CLKOUT1[2], S8_CLKOUT1[19], 1'b0, S8_CLKOUT1[17], S8_CLKOUT1[16], //bits 11 down to 6 - S8_CLKOUT1[14], S8_CLKOUT1[15], 1'b0, S8_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + rom[162] = {5'h06, 16'h010B, S8_CLKOUT1[4], S8_CLKOUT1[5], S8_CLKOUT1[3], S8_CLKOUT1[12], //bits 15 down to 12 + S8_CLKOUT1[1], S8_CLKOUT1[2], S8_CLKOUT1[19], 1'b0, S8_CLKOUT1[17], S8_CLKOUT1[16], //bits 11 down to 6 + S8_CLKOUT1[14], S8_CLKOUT1[15], 1'b0, S8_CLKOUT0[13], 2'h0}; //bits 5 down to 0 - rom[163] = {5'h07, 16'hE02C, 3'h0, S8_CLKOUT1[11], S8_CLKOUT1[9], S8_CLKOUT1[10], //bits 15 down to 10 - S8_CLKOUT1[8], S8_CLKOUT1[7], S8_CLKOUT1[6], S8_CLKOUT1[20], 1'b0, S8_CLKOUT1[13], //bits 9 down to 4 - 2'b00, S8_CLKOUT1[21], S8_CLKOUT1[22]}; //bits 3 down to 0 + rom[163] = {5'h07, 16'hE02C, 3'h0, S8_CLKOUT1[11], S8_CLKOUT1[9], S8_CLKOUT1[10], //bits 15 down to 10 + S8_CLKOUT1[8], S8_CLKOUT1[7], S8_CLKOUT1[6], S8_CLKOUT1[20], 1'b0, S8_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S8_CLKOUT1[21], S8_CLKOUT1[22]}; //bits 3 down to 0 - rom[164] = {5'h08, 16'h4001, S8_CLKOUT2[22], 1'b0, S8_CLKOUT2[5], S8_CLKOUT2[21], //bits 15 downto 12 - S8_CLKOUT2[12], S8_CLKOUT2[4], S8_CLKOUT2[3], S8_CLKOUT2[2], S8_CLKOUT2[0], S8_CLKOUT2[19], //bits 11 down to 6 - S8_CLKOUT2[17], S8_CLKOUT2[18], S8_CLKOUT2[15], S8_CLKOUT2[16], S8_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + rom[164] = {5'h08, 16'h4001, S8_CLKOUT2[22], 1'b0, S8_CLKOUT2[5], S8_CLKOUT2[21], //bits 15 downto 12 + S8_CLKOUT2[12], S8_CLKOUT2[4], S8_CLKOUT2[3], S8_CLKOUT2[2], S8_CLKOUT2[0], S8_CLKOUT2[19], //bits 11 down to 6 + S8_CLKOUT2[17], S8_CLKOUT2[18], S8_CLKOUT2[15], S8_CLKOUT2[16], S8_CLKOUT2[14], 1'b0}; //bits 5 down to 0 - rom[165] = {5'h09, 16'h0D03, S8_CLKOUT3[14], S8_CLKOUT3[15], S8_CLKOUT0[21], S8_CLKOUT0[22], 2'h0, S8_CLKOUT2[10], 1'b0, //bits 15 downto 8 - S8_CLKOUT2[9], S8_CLKOUT2[8], S8_CLKOUT2[6], S8_CLKOUT2[7], S8_CLKOUT2[13], S8_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + rom[165] = {5'h09, 16'h0D03, S8_CLKOUT3[14], S8_CLKOUT3[15], S8_CLKOUT0[21], S8_CLKOUT0[22], 2'h0, S8_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S8_CLKOUT2[9], S8_CLKOUT2[8], S8_CLKOUT2[6], S8_CLKOUT2[7], S8_CLKOUT2[13], S8_CLKOUT2[20], 2'h0}; //bits 7 downto 0 - rom[166] = {5'h0A, 16'hB001, 1'b0, S8_CLKOUT3[13], 2'h0, S8_CLKOUT3[21], S8_CLKOUT3[22], S8_CLKOUT3[5], S8_CLKOUT3[4], //bits 15 downto 8 - S8_CLKOUT3[12], S8_CLKOUT3[2], S8_CLKOUT3[0], S8_CLKOUT3[1], S8_CLKOUT3[18], S8_CLKOUT3[19], //bits 7 downto 2 - S8_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + rom[166] = {5'h0A, 16'hB001, 1'b0, S8_CLKOUT3[13], 2'h0, S8_CLKOUT3[21], S8_CLKOUT3[22], S8_CLKOUT3[5], S8_CLKOUT3[4], //bits 15 downto 8 + S8_CLKOUT3[12], S8_CLKOUT3[2], S8_CLKOUT3[0], S8_CLKOUT3[1], S8_CLKOUT3[18], S8_CLKOUT3[19], //bits 7 downto 2 + S8_CLKOUT3[17], 1'b0}; //bits 1 downto 0 - rom[167] = {5'h0B, 16'h0110, S8_CLKOUT0[5], S8_CLKOUT4[19], S8_CLKOUT4[14], S8_CLKOUT4[17], //bits 15 downto 12 - S8_CLKOUT4[15], S8_CLKOUT4[16], S8_CLKOUT0[4], 1'b0, S8_CLKOUT3[11], S8_CLKOUT3[10], //bits 11 downto 6 - S8_CLKOUT3[9], 1'b0, S8_CLKOUT3[7], S8_CLKOUT3[8], S8_CLKOUT3[20], S8_CLKOUT3[6]}; //bits 5 downto 0 + rom[167] = {5'h0B, 16'h0110, S8_CLKOUT0[5], S8_CLKOUT4[19], S8_CLKOUT4[14], S8_CLKOUT4[17], //bits 15 downto 12 + S8_CLKOUT4[15], S8_CLKOUT4[16], S8_CLKOUT0[4], 1'b0, S8_CLKOUT3[11], S8_CLKOUT3[10], //bits 11 downto 6 + S8_CLKOUT3[9], 1'b0, S8_CLKOUT3[7], S8_CLKOUT3[8], S8_CLKOUT3[20], S8_CLKOUT3[6]}; //bits 5 downto 0 - rom[168] = {5'h0C, 16'h0B00, S8_CLKOUT4[7], S8_CLKOUT4[8], S8_CLKOUT4[20], S8_CLKOUT4[6], 1'b0, S8_CLKOUT4[13], //bits 15 downto 10 - 2'h0, S8_CLKOUT4[22], S8_CLKOUT4[21], S8_CLKOUT4[4], S8_CLKOUT4[5], S8_CLKOUT4[3], //bits 9 downto 3 - S8_CLKOUT4[12], S8_CLKOUT4[1], S8_CLKOUT4[2]}; //bits 2 downto 0 + rom[168] = {5'h0C, 16'h0B00, S8_CLKOUT4[7], S8_CLKOUT4[8], S8_CLKOUT4[20], S8_CLKOUT4[6], 1'b0, S8_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S8_CLKOUT4[22], S8_CLKOUT4[21], S8_CLKOUT4[4], S8_CLKOUT4[5], S8_CLKOUT4[3], //bits 9 downto 3 + S8_CLKOUT4[12], S8_CLKOUT4[1], S8_CLKOUT4[2]}; //bits 2 downto 0 - rom[169] = {5'h0D, 16'h0008, S8_CLKOUT5[2], S8_CLKOUT5[3], S8_CLKOUT5[0], S8_CLKOUT5[1], S8_CLKOUT5[18], //bits 15 downto 11 - S8_CLKOUT5[19], S8_CLKOUT5[17], S8_CLKOUT5[16], S8_CLKOUT5[15], S8_CLKOUT0[3], //bits 10 downto 6 - S8_CLKOUT0[0], S8_CLKOUT0[2], 1'b0, S8_CLKOUT4[11], S8_CLKOUT4[9], S8_CLKOUT4[10]}; //bits 5 downto 0 + rom[169] = {5'h0D, 16'h0008, S8_CLKOUT5[2], S8_CLKOUT5[3], S8_CLKOUT5[0], S8_CLKOUT5[1], S8_CLKOUT5[18], //bits 15 downto 11 + S8_CLKOUT5[19], S8_CLKOUT5[17], S8_CLKOUT5[16], S8_CLKOUT5[15], S8_CLKOUT0[3], //bits 10 downto 6 + S8_CLKOUT0[0], S8_CLKOUT0[2], 1'b0, S8_CLKOUT4[11], S8_CLKOUT4[9], S8_CLKOUT4[10]}; //bits 5 downto 0 - rom[170] = {5'h0E, 16'h00D0, S8_CLKOUT5[10], S8_CLKOUT5[11], S8_CLKOUT5[8], S8_CLKOUT5[9], S8_CLKOUT5[6], //bits 15 downto 11 - S8_CLKOUT5[7], S8_CLKOUT5[20], S8_CLKOUT5[13], 2'h0, S8_CLKOUT5[22], 1'b0, //bits 10 downto 4 - S8_CLKOUT5[5], S8_CLKOUT5[21], S8_CLKOUT5[12], S8_CLKOUT5[4]}; //bits 3 downto 0 + rom[170] = {5'h0E, 16'h00D0, S8_CLKOUT5[10], S8_CLKOUT5[11], S8_CLKOUT5[8], S8_CLKOUT5[9], S8_CLKOUT5[6], //bits 15 downto 11 + S8_CLKOUT5[7], S8_CLKOUT5[20], S8_CLKOUT5[13], 2'h0, S8_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S8_CLKOUT5[5], S8_CLKOUT5[21], S8_CLKOUT5[12], S8_CLKOUT5[4]}; //bits 3 downto 0 - rom[171] = {5'h0F, 16'h0003, S8_CLKFBOUT[4], S8_CLKFBOUT[5], S8_CLKFBOUT[3], S8_CLKFBOUT[12], S8_CLKFBOUT[1], //bits 15 downto 11 - S8_CLKFBOUT[2], S8_CLKFBOUT[0], S8_CLKFBOUT[19], S8_CLKFBOUT[18], S8_CLKFBOUT[17], //bits 10 downto 6 - S8_CLKFBOUT[15], S8_CLKFBOUT[16], S8_CLKOUT0[12], S8_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + rom[171] = {5'h0F, 16'h0003, S8_CLKFBOUT[4], S8_CLKFBOUT[5], S8_CLKFBOUT[3], S8_CLKFBOUT[12], S8_CLKFBOUT[1], //bits 15 downto 11 + S8_CLKFBOUT[2], S8_CLKFBOUT[0], S8_CLKFBOUT[19], S8_CLKFBOUT[18], S8_CLKFBOUT[17], //bits 10 downto 6 + S8_CLKFBOUT[15], S8_CLKFBOUT[16], S8_CLKOUT0[12], S8_CLKOUT0[1], 2'b00}; //bits 5 downto 0 - rom[172] = {5'h10, 16'h800C, 1'b0, S8_CLKOUT0[9], S8_CLKOUT0[11], S8_CLKOUT0[10], S8_CLKFBOUT[10], S8_CLKFBOUT[11], //bits 15 downto 10 - S8_CLKFBOUT[9], S8_CLKFBOUT[8], S8_CLKFBOUT[7], S8_CLKFBOUT[6], S8_CLKFBOUT[13], //bits 9 downto 5 - S8_CLKFBOUT[20], 2'h0, S8_CLKFBOUT[21], S8_CLKFBOUT[22]}; //bits 4 downto 0 + rom[172] = {5'h10, 16'h800C, 1'b0, S8_CLKOUT0[9], S8_CLKOUT0[11], S8_CLKOUT0[10], S8_CLKFBOUT[10], S8_CLKFBOUT[11], //bits 15 downto 10 + S8_CLKFBOUT[9], S8_CLKFBOUT[8], S8_CLKFBOUT[7], S8_CLKFBOUT[6], S8_CLKFBOUT[13], //bits 9 downto 5 + S8_CLKFBOUT[20], 2'h0, S8_CLKFBOUT[21], S8_CLKFBOUT[22]}; //bits 4 downto 0 - rom[173] = {5'h11, 16'hFC00, 6'h00, S8_CLKOUT3[3], S8_CLKOUT3[16], S8_CLKOUT2[11], S8_CLKOUT2[1], S8_CLKOUT1[18], //bits 15 downto 6 - S8_CLKOUT1[0], S8_CLKOUT0[6], S8_CLKOUT0[20], S8_CLKOUT0[8], S8_CLKOUT0[7]}; //bits 5 downto 0 + rom[173] = {5'h11, 16'hFC00, 6'h00, S8_CLKOUT3[3], S8_CLKOUT3[16], S8_CLKOUT2[11], S8_CLKOUT2[1], S8_CLKOUT1[18], //bits 15 downto 6 + S8_CLKOUT1[0], S8_CLKOUT0[6], S8_CLKOUT0[20], S8_CLKOUT0[8], S8_CLKOUT0[7]}; //bits 5 downto 0 - rom[174] = {5'h12, 16'hF0FF, 4'h0, S8_CLKOUT5[14], S8_CLKFBOUT[14], S8_CLKOUT4[0], S8_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + rom[174] = {5'h12, 16'hF0FF, 4'h0, S8_CLKOUT5[14], S8_CLKFBOUT[14], S8_CLKOUT4[0], S8_CLKOUT4[18], 8'h00}; //bits 15 downto 0 - rom[175] = {5'h13, 16'h5120, S8_DIVCLK[11], 1'b0, S8_DIVCLK[10], 1'b0, S8_DIVCLK[7], S8_DIVCLK[8], //bits 15 downto 10 - S8_DIVCLK[0], 1'b0, S8_DIVCLK[5], S8_DIVCLK[2], 1'b0, S8_DIVCLK[13], 4'h0}; //bits 9 downto 0 + rom[175] = {5'h13, 16'h5120, S8_DIVCLK[11], 1'b0, S8_DIVCLK[10], 1'b0, S8_DIVCLK[7], S8_DIVCLK[8], //bits 15 downto 10 + S8_DIVCLK[0], 1'b0, S8_DIVCLK[5], S8_DIVCLK[2], 1'b0, S8_DIVCLK[13], 4'h0}; //bits 9 downto 0 - rom[176] = {5'h14, 16'h2FFF, S8_LOCK[1], S8_LOCK[2], 1'b0, S8_LOCK[0], 12'h000}; //bits 15 downto 0 + rom[176] = {5'h14, 16'h2FFF, S8_LOCK[1], S8_LOCK[2], 1'b0, S8_LOCK[0], 12'h000}; //bits 15 downto 0 - rom[177] = {5'h15, 16'hBFF4, 1'b0, S8_DIVCLK[12], 10'h000, S8_LOCK[38], 1'b0, S8_LOCK[32], S8_LOCK[39]}; //bits 15 downto 0 + rom[177] = {5'h15, 16'hBFF4, 1'b0, S8_DIVCLK[12], 10'h000, S8_LOCK[38], 1'b0, S8_LOCK[32], S8_LOCK[39]}; //bits 15 downto 0 - rom[178] = {5'h16, 16'h0A55, S8_LOCK[15], S8_LOCK[13], S8_LOCK[27], S8_LOCK[16], 1'b0, S8_LOCK[10], //bits 15 downto 10 - 1'b0, S8_DIVCLK[9], S8_DIVCLK[1], 1'b0, S8_DIVCLK[6], 1'b0, S8_DIVCLK[3], //bits 9 downto 3 - 1'b0, S8_DIVCLK[4], 1'b0}; //bits 2 downto 0 + rom[178] = {5'h16, 16'h0A55, S8_LOCK[15], S8_LOCK[13], S8_LOCK[27], S8_LOCK[16], 1'b0, S8_LOCK[10], //bits 15 downto 10 + 1'b0, S8_DIVCLK[9], S8_DIVCLK[1], 1'b0, S8_DIVCLK[6], 1'b0, S8_DIVCLK[3], //bits 9 downto 3 + 1'b0, S8_DIVCLK[4], 1'b0}; //bits 2 downto 0 - rom[179] = {5'h17, 16'hFFD0, 10'h000, S8_LOCK[17], 1'b0, S8_LOCK[8], S8_LOCK[9], S8_LOCK[23], S8_LOCK[22]}; //bits 15 downto 0 + rom[179] = {5'h17, 16'hFFD0, 10'h000, S8_LOCK[17], 1'b0, S8_LOCK[8], S8_LOCK[9], S8_LOCK[23], S8_LOCK[22]}; //bits 15 downto 0 - rom[180] = {5'h18, 16'h1039, S8_DIGITAL_FILT[6], S8_DIGITAL_FILT[7], S8_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 - S8_DIGITAL_FILT[2], S8_DIGITAL_FILT[1], S8_DIGITAL_FILT[3], S8_DIGITAL_FILT[9], //bits 11 downto 8 - S8_DIGITAL_FILT[8], S8_LOCK[26], 3'h0, S8_LOCK[19], S8_LOCK[18], 1'b0}; //bits 7 downto 0 + rom[180] = {5'h18, 16'h1039, S8_DIGITAL_FILT[6], S8_DIGITAL_FILT[7], S8_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S8_DIGITAL_FILT[2], S8_DIGITAL_FILT[1], S8_DIGITAL_FILT[3], S8_DIGITAL_FILT[9], //bits 11 downto 8 + S8_DIGITAL_FILT[8], S8_LOCK[26], 3'h0, S8_LOCK[19], S8_LOCK[18], 1'b0}; //bits 7 downto 0 - rom[181] = {5'h19, 16'h0000, S8_LOCK[24], S8_LOCK[25], S8_LOCK[21], S8_LOCK[14], S8_LOCK[11], //bits 15 downto 11 - S8_LOCK[12], S8_LOCK[20], S8_LOCK[6], S8_LOCK[35], S8_LOCK[36], //bits 10 downto 6 - S8_LOCK[37], S8_LOCK[3], S8_LOCK[33], S8_LOCK[31], S8_LOCK[34], S8_LOCK[30]}; //bits 5 downto 0 + rom[181] = {5'h19, 16'h0000, S8_LOCK[24], S8_LOCK[25], S8_LOCK[21], S8_LOCK[14], S8_LOCK[11], //bits 15 downto 11 + S8_LOCK[12], S8_LOCK[20], S8_LOCK[6], S8_LOCK[35], S8_LOCK[36], //bits 10 downto 6 + S8_LOCK[37], S8_LOCK[3], S8_LOCK[33], S8_LOCK[31], S8_LOCK[34], S8_LOCK[30]}; //bits 5 downto 0 - rom[182] = {5'h1A, 16'hFFFC, 14'h0000, S8_LOCK[28], S8_LOCK[29]}; //bits 15 downto 0 + rom[182] = {5'h1A, 16'hFFFC, 14'h0000, S8_LOCK[28], S8_LOCK[29]}; //bits 15 downto 0 - rom[183] = {5'h1D, 16'h2FFF, S8_LOCK[7], S8_LOCK[4], 1'b0, S8_LOCK[5], 12'h000}; //bits 15 downto 0 + rom[183] = {5'h1D, 16'h2FFF, S8_LOCK[7], S8_LOCK[4], 1'b0, S8_LOCK[5], 12'h000}; //bits 15 downto 0 - // Initialize the rest of the ROM + // Initialize the rest of the ROM // for(ii = 46; ii < 64; ii = ii +1) begin // rom[ii] = 0; // end @@ -1537,7 +1537,7 @@ module pll_drp // State sync reg [3:0] current_state = RESTART; reg [3:0] next_state = RESTART; - + // State Definitions localparam RESTART = 4'h1; localparam WAIT_LOCK = 4'h2; @@ -1548,15 +1548,15 @@ module pll_drp localparam BITSET = 4'h7; localparam WRITE = 4'h8; localparam WAIT_DRDY = 4'h9; - - // These variables are used to keep track of the number of iterations that + + // These variables are used to keep track of the number of iterations that // each state takes to reconfigure // STATE_COUNT_CONST is used to reset the counters and should match the // number of registers necessary to reconfigure each state. localparam STATE_COUNT_CONST = 23; - reg [4:0] state_count = STATE_COUNT_CONST; + reg [4:0] state_count = STATE_COUNT_CONST; reg [4:0] next_state_count = STATE_COUNT_CONST; - + // This block assigns the next register value from the state machine below always @(posedge SCLK) begin DADDR <= #TCQ next_daddr; @@ -1564,13 +1564,13 @@ module pll_drp DEN <= #TCQ next_den; RST_PLL <= #TCQ next_rst_pll; DI <= #TCQ next_di; - + SRDY <= #TCQ next_srdy; - + rom_addr <= #TCQ next_rom_addr; state_count <= #TCQ next_state_count; end - + // This block assigns the next state, reset is syncronous. always @(posedge SCLK) begin if(RST) begin @@ -1579,7 +1579,7 @@ module pll_drp current_state <= #TCQ next_state; end end - + always @* begin // Setup the default values next_srdy = 1'b0; @@ -1590,7 +1590,7 @@ module pll_drp next_di = DI; next_rom_addr = rom_addr; next_state_count = state_count; - + case (current_state) // If RST is asserted reset the machine RESTART: begin @@ -1600,15 +1600,15 @@ module pll_drp next_rst_pll = 1'b1; next_state = WAIT_LOCK; end - + // Waits for the PLL to assert LOCKED - once it does asserts SRDY WAIT_LOCK: begin // Make sure reset is de-asserted next_rst_pll = 1'b0; - // Reset the number of registers left to write for the next + // Reset the number of registers left to write for the next // reconfiguration event. next_state_count = STATE_COUNT_CONST; - + if(LOCKED) begin // PLL is locked, go on to wait for the SEN signal next_state = WAIT_SEN; @@ -1620,8 +1620,8 @@ module pll_drp next_state = WAIT_LOCK; end end - - // Wait for the next SEN pulse and set the ROM addr appropriately + + // Wait for the next SEN pulse and set the ROM addr appropriately // based on SADDR WAIT_SEN: begin if(SEN) begin @@ -1667,7 +1667,7 @@ module pll_drp next_state = WAIT_A_DRDY; end end - + // Zero out the bits that are not set in the mask stored in rom BITMASK: begin // Do the mask @@ -1675,7 +1675,7 @@ module pll_drp // Go on to set the bits next_state = BITSET; end - + // After the input is masked, OR the bits with calculated value in rom BITSET: begin // Set the bits that need to be assigned @@ -1685,20 +1685,20 @@ module pll_drp // Go on to write the data to the PLL next_state = WRITE; end - + // DI is setup so assert DWE, DEN, and RST_PLL. Subtract one from the // state count and go to wait for DRDY. WRITE: begin // Set WE and EN on PLL next_dwe = 1'b1; next_den = 1'b1; - + // Decrement the number of registers left to write next_state_count = state_count - 1'b1; // Wait for the write to complete next_state = WAIT_DRDY; end - + // Wait for DRDY to assert from the PLL. If the state count is not 0 // jump to ADDRESS (continue reconfiguration). If state count is // 0 wait for lock. @@ -1718,12 +1718,12 @@ module pll_drp next_state = WAIT_DRDY; end end - + // If in an unknown state reset the machine default: begin next_state = RESTART; end endcase end - + endmodule diff --git a/cores/Spectrum/pll_top.v b/cores/Spectrum/pll_top.v index eb57bf1..40faa1b 100644 --- a/cores/Spectrum/pll_top.v +++ b/cores/Spectrum/pll_top.v @@ -79,8 +79,6 @@ module pll_top wire locked; // These signals are used for the BUFG's necessary for the design. - wire clkin_bufgout; - wire clkfb_bufgout; wire clkfb_bufgin; @@ -103,11 +101,6 @@ module pll_top wire clk5_bufgout; // Global buffers used in design -// BUFG BUFG_IN ( -// .O(clkin_bufgout), -// .I(CLKIN) -// ); - assign clkin_bufgout = CLKIN; BUFG BUFG_FB ( .O(clkfb_bufgout), @@ -337,7 +330,7 @@ module pll_top .SRDY(SRDY), // Input from IBUFG - .SCLK(clkin_bufgout), + .SCLK(CLKIN), // Direct connections to the PLL_ADV .DO(dout), diff --git a/cores/Spectrum/rom.v b/cores/Spectrum/rom.v index 928d078..3db54f9 100644 --- a/cores/Spectrum/rom.v +++ b/cores/Spectrum/rom.v @@ -24,7 +24,7 @@ module rom ( output reg [7:0] dout ); - reg [7:0] mem[0:255]; + reg [7:0] mem[0:255]; //127 integer i; initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM for (i=0;i<256;i=i+1) begin @@ -34,6 +34,6 @@ module rom ( end always @(posedge clk) begin - dout <= mem[a[7:0]]; + dout <= mem[a[7:0]]; //6:0 end endmodule diff --git a/cores/Spectrum/zxuno.v b/cores/Spectrum/zxuno.v index 34bfc51..6a281cc 100644 --- a/cores/Spectrum/zxuno.v +++ b/cores/Spectrum/zxuno.v @@ -65,7 +65,7 @@ module zxuno ( input wire joyleft, input wire joyright, input wire joyfire, - + // MOUSE inout wire mouseclk, inout wire mousedata, @@ -81,7 +81,7 @@ module zxuno ( wire mreq_n,iorq_n,rd_n,wr_n,int_n,m1_n,nmi_n,rfsh_n; wire enable_nmi_n; wire [15:0] cpuaddr; - wire [7:0] cpudin; + reg [7:0] cpudin; wire [7:0] cpudout; wire [7:0] ula_dout; @@ -191,24 +191,46 @@ module zxuno ( // Asignación de dato para la CPU segun la decodificación de todos los dispositivos // conectados a ella. - assign cpudin = (oe_n_romyram==1'b0)? memory_dout : - (oe_n_ay==1'b0)? ay_dout : - (oe_n_joystick==1'b0)? joystick_dout : - (oe_n_zxunoaddr==1'b0)? zxuno_addr_to_cpu : - (oe_n_spi==1'b0)? spi_dout : - (oe_n_scancode==1'b0)? scancode_dout : - (oe_n_kbstatus==1'b0)? kbstatus_dout : - (oe_n_coreid==1'b0)? coreid_dout : - (oe_n_keymap==1'b0)? keymap_dout : - (oe_n_scratch==1'b0)? scratch_dout : - (oe_n_scndblctrl==1'b0)? scndblctrl_dout : - (oe_n_nmievents==1'b0)? nmievents_dout : - (oe_n_kmouse==1'b0)? kmouse_dout : - (oe_n_mousedata==1'b0)? mousedata_dout : - (oe_n_mousestatus==1'b0)? mousestatus_dout : - (oe_n_rasterint==1'b0)? rasterint_dout : - (oe_n_devoptions==1'b0)? devoptions_dout : - ula_dout; +// assign cpudin = (oe_n_romyram==1'b0)? memory_dout : +// (oe_n_ay==1'b0)? ay_dout : +// (oe_n_joystick==1'b0)? joystick_dout : +// (oe_n_zxunoaddr==1'b0)? zxuno_addr_to_cpu : +// (oe_n_spi==1'b0)? spi_dout : +// (oe_n_scancode==1'b0)? scancode_dout : +// (oe_n_kbstatus==1'b0)? kbstatus_dout : +// (oe_n_coreid==1'b0)? coreid_dout : +// (oe_n_keymap==1'b0)? keymap_dout : +// (oe_n_scratch==1'b0)? scratch_dout : +// (oe_n_scndblctrl==1'b0)? scndblctrl_dout : +// (oe_n_nmievents==1'b0)? nmievents_dout : +// (oe_n_kmouse==1'b0)? kmouse_dout : +// (oe_n_mousedata==1'b0)? mousedata_dout : +// (oe_n_mousestatus==1'b0)? mousestatus_dout : +// (oe_n_rasterint==1'b0)? rasterint_dout : +// (oe_n_devoptions==1'b0)? devoptions_dout : +// ula_dout; + always @* begin + case (1'b0) + oe_n_ay : cpudin = ay_dout; + oe_n_joystick : cpudin = joystick_dout; + oe_n_zxunoaddr : cpudin = zxuno_addr_to_cpu; + oe_n_spi : cpudin = spi_dout; + oe_n_scancode : cpudin = scancode_dout; + oe_n_kbstatus : cpudin = kbstatus_dout; + oe_n_coreid : cpudin = coreid_dout; + oe_n_keymap : cpudin = keymap_dout; + oe_n_scratch : cpudin = scratch_dout; + oe_n_scndblctrl : cpudin = scndblctrl_dout; + oe_n_nmievents : cpudin = nmievents_dout; + oe_n_kmouse : cpudin = kmouse_dout; + oe_n_mousedata : cpudin = mousedata_dout; + oe_n_mousestatus : cpudin = mousestatus_dout; + oe_n_rasterint : cpudin = rasterint_dout; + oe_n_devoptions : cpudin = devoptions_dout; + oe_n_romyram : cpudin = memory_dout; + default : cpudin = ula_dout; + endcase + end tv80n_wrapper el_z80 ( .m1_n(m1_n), @@ -232,7 +254,7 @@ module zxuno ( ); ula_radas la_ula ( - // Clocks + // Clocks .clk14(clk14), // 14MHz master clock .clk7(clk7), .wssclk(wssclk), // 5MHz WSS clock @@ -240,15 +262,15 @@ module zxuno ( .CPUContention(CPUContention), .rst_n(mrst_n & rst_n & power_on_reset_n), - // CPU interface - .a(cpuaddr), + // CPU interface + .a(cpuaddr), .access_to_contmem(access_to_screen), - .mreq_n(mreq_n), - .iorq_n(iorq_n), - .rd_n(rd_n), - .wr_n(wr_n), - .int_n(int_n), - .din(cpudout), + .mreq_n(mreq_n), + .iorq_n(iorq_n), + .rd_n(rd_n), + .wr_n(wr_n), + .int_n(int_n), + .din(cpudout), .dout(ula_dout), .rasterint_enable(rasterint_enable), .vretraceint_disable(vretraceint_disable), @@ -258,7 +280,7 @@ module zxuno ( // VRAM interface .va(vram_addr), // 16KB videoram, 2 pages .vramdata(vram_dout), - + // I/O ports .ear(ear), .mic(mic), @@ -271,10 +293,10 @@ module zxuno ( .enable_timexmmu(enable_timexmmu), // Video - .r(r), - .g(g), - .b(b), - .hsync(hsync), + .r(r), + .g(g), + .b(b), + .hsync(hsync), .vsync(vsync) ); @@ -533,7 +555,7 @@ module zxuno ( multiboot el_multiboot ( .clk(clk), - .clk_icap(clk), + .clk_icap(clk14), .rst_n(rst_n & mrst_n & power_on_reset_n), .kb_boot_core(boot_second_core), .zxuno_addr(zxuno_addr), @@ -567,21 +589,21 @@ module zxuno ( .oe_n(oe_n_ay), .audio_out_ay1(ay1_audio), .audio_out_ay2(ay2_audio) - ); + ); /////////////////////////////////// // SOUND MIXER /////////////////////////////////// // 8-bit mixer to generate different audio levels according to input sources - mixer audio_mix( - .clkdac(clk), - .reset(1'b0), - .mic(mic), - .spk(spk), + mixer audio_mix( + .clkdac(clk), + .reset(1'b0), + .mic(mic), + .spk(spk), .ear(ear), .ay1(ay1_audio), - .ay2(ay2_audio), - .audio(audio_out) - ); + .ay2(ay2_audio), + .audio(audio_out) + ); endmodule diff --git a/cores/bitgen.bat b/cores/bitgen.bat new file mode 100644 index 0000000..ca48b5a --- /dev/null +++ b/cores/bitgen.bat @@ -0,0 +1,2 @@ +call mypath +%mypath%\bitgen.exe %* \ No newline at end of file diff --git a/cores/map.bat b/cores/map.bat new file mode 100644 index 0000000..541fb62 --- /dev/null +++ b/cores/map.bat @@ -0,0 +1,2 @@ +call mypath +%mypath%\map.exe %* \ No newline at end of file diff --git a/cores/mypath.txt b/cores/mypath.txt new file mode 100644 index 0000000..261f133 --- /dev/null +++ b/cores/mypath.txt @@ -0,0 +1,2 @@ +rem put the correct path and rename this file to .bat +set mypath=C:\path_to\Xilinx\14.7\ISE_DS\ISE\bin\nt64 \ No newline at end of file diff --git a/cores/ngdbuild.bat b/cores/ngdbuild.bat new file mode 100644 index 0000000..7dddbff --- /dev/null +++ b/cores/ngdbuild.bat @@ -0,0 +1,2 @@ +call mypath +%mypath%\ngdbuild.exe %* \ No newline at end of file diff --git a/cores/par.bat b/cores/par.bat new file mode 100644 index 0000000..4d90ce7 --- /dev/null +++ b/cores/par.bat @@ -0,0 +1,2 @@ +call mypath +%mypath%\par.exe %* \ No newline at end of file diff --git a/cores/trce.bat b/cores/trce.bat new file mode 100644 index 0000000..ae347df --- /dev/null +++ b/cores/trce.bat @@ -0,0 +1,2 @@ +call mypath +%mypath%\trce.exe %* \ No newline at end of file diff --git a/cores/xst.bat b/cores/xst.bat new file mode 100644 index 0000000..98f173e --- /dev/null +++ b/cores/xst.bat @@ -0,0 +1,2 @@ +call mypath +%mypath%\xst.exe %* \ No newline at end of file diff --git a/firmware/firmware.asm b/firmware/firmware.asm index dc5a845..911b3ca 100644 --- a/firmware/firmware.asm +++ b/firmware/firmware.asm @@ -51,7 +51,8 @@ ; inputs lo: cursor position hi: max length ; otro lo: pagina actual hi: mascara paginas define sdhc $8fd4 - define empstr $8fd5 + define scnbak $8fd5 + define empstr $8fd6 define config $9000 define indexe $a000 define active $a040 @@ -214,8 +215,16 @@ keytab defb $00, $7a, $78, $63, $76 ; Caps z x c v start ld bc, chrend-runbit ldir - wreg scandbl_ctrl, $80 call loadch + ld a, scandbl_ctrl + ld bc, zxuno_port + out (c), a + inc b + ld a, (outvid) + scf + rra + ld (scnbak), a + out (c), a im 1 ld de, fincad-1 ; descomprimo cadenas ld hl, finstr-1 @@ -262,7 +271,7 @@ start3 ld a, b jr z, start3 ld b, $13 ldir - ld bc, zxuno_port ; print ID + ld bc, zxuno_port out (c), a ; a = $ff = core_id inc b ld hl, cad0+6 ; Load address of coreID string @@ -1284,9 +1293,13 @@ upgra ld bc, (menuop) ld d, 7 upgra1 push af call help - ld de, $0200 | cad60>>8 - ld hl, cmbpnt pop af + jr nz, upgra15 + ld bc, $1806 + ld ix, cad116 + call prnmul +upgra15 ld de, $0200 | cad60>>8 + ld hl, cmbpnt jr nz, upgra2 ld (hl), cad60 & $ff inc l @@ -1311,7 +1324,7 @@ upgra3 ld a, ixl inc l ld (hl), bnames>>8 inc l - ld (ix+23), b + ld (ix+22), b add ix, bc ld a, (ix+31) cp ' ' @@ -3985,12 +3998,24 @@ l3ec3 ld a, ixl in l, (c) jp (hl) - block $3eff-$ ; 50 bytes + block $3ee6-$ ; 25 bytes + +lbytes ld a, (scnbak) + and %01111111 + call setvid + call lbytes2 + ld a, (scnbak) +setvid ld l, scandbl_ctrl + ld bc, zxuno_port + out (c), l + inc b + out (c), a + ret l3eff in l,(c) jp (hl) -lbytes di ; disable interrupts +lbytes2 di ; disable interrupts ld a, $0f ; make the border white and mic off. out ($fe), a ; output to port. push ix @@ -4158,7 +4183,7 @@ decbhl dec hl block $7e00-$ cad0 defb 'Core: ',0 cad1 defm 'http://zxuno.speccy.org', 0 - defm 'ZX-Uno BIOS v0.328', 0 + defm 'ZX-Uno BIOS v0.40', 0 defm 'Copyleft ', 127, ' 2016 ZX-Uno Team', 0 defm 'Processor: Z80 3.5MHz', 0 defm 'Memory: 512K Ok', 0 @@ -4193,7 +4218,7 @@ cad8 defm $10, ' ', $10, ' ', $10, 0 cad9 defb $14, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11 defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $18, $11 defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $15, 0 - defb ' BIOS v0.328 ', $7f, '2016 ZX-Uno Team', 0 + defb ' BIOS v0.40 ', $7f, '2016 ZX-Uno Team', 0 cad10 defb 'Hardware tests', 0 defb $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11, $11 defb $11, $11, $11, $11, 0 @@ -4496,6 +4521,15 @@ cad114 defb 'Break to exit', 0 cad115 defb 'Slot occupied, select', 0 defb 'another or delete a', 0 defb 'ROM to free it', 0 +cad116 defb '2', 0 + defb '3', 0 + defb '4', 0 + defb '5', 0 + defb '6', 0 + defb '7', 0 + defb '8', 0 + defb '9', 0, 0 + ;cad199 defb 'af0000 bc0000 de0000 hl0000 sp0000 ix0000 iy0000', 0 fincad diff --git a/firmware/rom_taps/rooted.tap b/firmware/rom_taps/rooted.tap new file mode 100644 index 0000000..9570929 Binary files /dev/null and b/firmware/rom_taps/rooted.tap differ