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Añado core zxpp01

This commit is contained in:
antoniovillena 2016-08-23 21:01:57 +02:00
parent 0637ef9126
commit c2b3846598
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170
cores/KypSpectrum/clock.vhd Normal file
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-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____25.143______0.000______50.0______372.649____211.523
-- CLK_OUT2____14.080______0.000______50.0______420.640____211.523
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
clock32 : in std_logic;
-- Clock out ports
clock25 : out std_logic;
clock14 : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clock32);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 22,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 28,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 50,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clock25,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clock14,
I => clkout1);
end xilinx;

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SET machine=zxpp
SET speed=2
SET ruta_ucf=papilio
SET ruta_bat=..\
call %ruta_bat%genxst.bat
rem call %ruta_bat%generar.bat v2_v3
rem call %ruta_bat%generar.bat v4
rem call %ruta_bat%generar.bat Ap
call %ruta_bat%generar.bat Pa

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cores/KypSpectrum/papilio_zxuno_Pa.ucf Normal file
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# UCF file for the Papilio Pro board
# Generated by pin_converter, written by Kevin Lindsey
# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
# Main board wing pin [] to FPGA pin Pxx map
# -------C------- -------B------- -------A-------
# [GND] [C00] P114 [GND] [B00] P99 P100 [A15]
# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14]
# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13]
# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12]
# [C04] P118 [B04] P84 P85 [A11] [5V0]
# [C05] P119 [B05] P82 P83 [A10] [3V3]
# [C06] P120 [B06] P80 P81 [A09] [2V5]
# [C07] P121 [B07] P78 P79 [A08] [GND]
# [GND] [C08] P123 [GND] [B08] P74 P75 [A07]
# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06]
# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05]
# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04]
# [C12] P131 [B12] P57 P58 [A03] [5V0]
# [C13] P132 [B13] P55 P56 [A02] [3V3]
# [C14] P133 [B14] P50 P51 [A01] [2V5]
# [C15] P134 [B15] P47 P48 [A00] [GND]
## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
CONFIG PROHIBIT=P144;
CONFIG PROHIBIT=P69;
CONFIG PROHIBIT=P60;
NET netCLK LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
NET netHS LOC="P117" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C3
NET netVS LOC="P116" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C2
NET netR(0) LOC="P118" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C4
NET netR(1) LOC="P119" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C5
NET netR(2) LOC="P120" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C6
NET netR(3) LOC="P121" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C7
NET netG(0) LOC="P84" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4
NET netG(1) LOC="P82" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5
NET netG(2) LOC="P80" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6
NET netG(3) LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7
NET netB(0) LOC="P99" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0
NET netB(1) LOC="P97" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1
NET netB(2) LOC="P92" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2
NET netB(3) LOC="P87" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3

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cores/KypSpectrum/vga.vhd Normal file
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- |VGA 640x480 | Horizontal| Vertical|
-- +------------+-----------+-----------+
-- |Visible area| 0-639:640| 0-479:480|
-- |Front porch |640-655: 16|480-489: 10|
-- |Sync pulse |656-751: 96|490-491: 2|
-- |Back porch |752-799: 48|492-524: 33|
-- |Whole line | 800| 525|
entity vga is
port
(
clock25 : in std_logic;
hs : out std_logic;
vs : out std_logic;
rgb : out std_logic_vector(11 downto 0)
);
end;
architecture behavioral of vga is
signal x : std_logic_vector(9 downto 0);
signal y : std_logic_vector(9 downto 0);
begin
process(clock25)
begin
if rising_edge(clock25) then
if x < 799 then x <= x+1;
else
x <= (others => '0');
if y < 524 then y <= y+1;
else
y <= (others => '0');
end if;
end if;
if x >= 640+16 and x < 640+16+96 then hs <= '0'; else hs <= '1'; end if;
if y >= 480+10 and y < 480+10+ 2 then vs <= '0'; else vs <= '1'; end if;
if x < 640 and y < 480 then
rgb <= x"777";
else
rgb <= x"000";
end if;
end if;
end process;
end;

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cores/KypSpectrum/zxpp.prj Normal file
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vhdl work "vga.vhd"
vhdl work "clock.vhd"
vhdl work "zxpp.vhd"

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cores/KypSpectrum/zxpp.ut Normal file
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-w
-g DebugBitstream:No
-g Compress
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:Yes
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

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cores/KypSpectrum/zxpp.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity zxpp is
port
(
netCLK : in std_logic;
netVS : out std_logic;
netHS : out std_logic;
netR : out std_logic_vector(3 downto 0);
netG : out std_logic_vector(3 downto 0);
netB : out std_logic_vector(3 downto 0)
);
end;
architecture structural of zxpp is
component clock is
port
(
clock32 : in std_logic;
clock25 : out std_logic;
clock14 : out std_logic
);
end component;
component vga is
port
(
clock25 : in std_logic;
hs : out std_logic;
vs : out std_logic;
rgb : out std_logic_vector(11 downto 0)
);
end component;
signal clock25 : std_logic;
signal clock14 : std_logic;
begin
Uclock: clock port map
(
clock32 => netCLK,
clock25 => clock25,
clock14 => clock14
);
Uvga: vga port map
(
clock25 => clock25,
hs => netHS,
vs => netVS,
rgb(11 downto 8) => netR,
rgb( 7 downto 4) => netG,
rgb( 3 downto 0) => netB
);
end;

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cores/KypSpectrum/zxpp.xst Normal file
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set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn zxpp.prj
-ofn zxpp
-ofmt NGC
-p xc6slx9-2-tqg144
-top zxpp
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5