diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.bin b/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.bin
index 1e4c9eb..22d65ab 100644
Binary files a/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.bin and b/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.bin differ
diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.rpt b/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.rpt
index e9b3da9..d52b55f 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.rpt
+++ b/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM.rpt
@@ -1,3 +1,3 @@
-End of code:\t000031f0 g       *ABS*	00000000 _romend
-Start of BSS:\t000031f0 g       .bss	00000000 __bss_start__
-End of BSS:\t00003728 g       .bss	00000000 __bss_end__
+End of code:\t00001c08 g       *ABS*	00000000 _romend
+Start of BSS:\t00001c08 g       .bss	00000000 __bss_start__
+End of BSS:\t00002140 g       .bss	00000000 __bss_end__
diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd b/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd
index 8bbe593..839841c 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd
+++ b/cores/NES/src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd
@@ -68,17 +68,17 @@ shared variable ram : ram_type :=
      5 => x"80040400",
      6 => x"00000016",
      7 => x"00000000",
-     8 => x"0b0b80e3",
-     9 => x"f0080b0b",
-    10 => x"80e3f408",
-    11 => x"0b0b80e3",
-    12 => x"f8080b0b",
+     8 => x"0b0b0bb9",
+     9 => x"8c080b0b",
+    10 => x"0bb99008",
+    11 => x"0b0b0bb9",
+    12 => x"94080b0b",
     13 => x"0b0b9808",
-    14 => x"2d0b0b80",
-    15 => x"e3f80c0b",
-    16 => x"0b80e3f4",
-    17 => x"0c0b0b80",
-    18 => x"e3f00c04",
+    14 => x"2d0b0b0b",
+    15 => x"b9940c0b",
+    16 => x"0b0bb990",
+    17 => x"0c0b0b0b",
+    18 => x"b98c0c04",
     19 => x"00000000",
     20 => x"00000000",
     21 => x"00000000",
@@ -107,7 +107,7 @@ shared variable ram : ram_type :=
     44 => x"72fc060c",
     45 => x"51510471",
     46 => x"fc06080b",
-    47 => x"0b80de98",
+    47 => x"0b0bb3b4",
     48 => x"73830610",
     49 => x"10050806",
     50 => x"7381ff06",
@@ -116,3146 +116,1777 @@ shared variable ram : ram_type :=
     53 => x"1010102b",
     54 => x"0772fc06",
     55 => x"0c515104",
-    56 => x"80e3f070",
-    57 => x"80eea827",
-    58 => x"8b388071",
-    59 => x"70840553",
-    60 => x"0c81e304",
-    61 => x"8c51b192",
-    62 => x"0402fc05",
-    63 => x"0df88051",
-    64 => x"8f0b80e4",
-    65 => x"800c9f0b",
-    66 => x"80e4840c",
-    67 => x"a0717081",
-    68 => x"05533480",
-    69 => x"e48408ff",
-    70 => x"0580e484",
-    71 => x"0c80e484",
-    72 => x"088025e8",
-    73 => x"3880e480",
-    74 => x"08ff0580",
-    75 => x"e4800c80",
-    76 => x"e4800880",
-    77 => x"25d03880",
-    78 => x"0b80e484",
-    79 => x"0c800b80",
-    80 => x"e4800c02",
-    81 => x"84050d04",
-    82 => x"02f0050d",
-    83 => x"f88053f8",
-    84 => x"a05483bf",
-    85 => x"52737081",
-    86 => x"05553351",
-    87 => x"70737081",
-    88 => x"055534ff",
-    89 => x"12527180",
-    90 => x"25eb38fb",
-    91 => x"c0539f52",
-    92 => x"a0737081",
-    93 => x"055534ff",
-    94 => x"12527180",
-    95 => x"25f23802",
-    96 => x"90050d04",
-    97 => x"02f4050d",
-    98 => x"74538e0b",
-    99 => x"80e48008",
-   100 => x"25913882",
-   101 => x"c82d80e4",
-   102 => x"8008ff05",
-   103 => x"80e4800c",
-   104 => x"838a0480",
-   105 => x"e4800880",
-   106 => x"e4840853",
-   107 => x"51728a2e",
-   108 => x"098106be",
-   109 => x"38715171",
-   110 => x"9f24a438",
-   111 => x"80e48008",
-   112 => x"a02911f8",
-   113 => x"80115151",
-   114 => x"a0713480",
-   115 => x"e4840881",
-   116 => x"0580e484",
-   117 => x"0c80e484",
-   118 => x"08519f71",
-   119 => x"25de3880",
-   120 => x"0b80e484",
-   121 => x"0c80e480",
-   122 => x"08810580",
-   123 => x"e4800c84",
-   124 => x"880470a0",
-   125 => x"2912f880",
-   126 => x"11515172",
-   127 => x"713480e4",
-   128 => x"84088105",
-   129 => x"80e4840c",
-   130 => x"80e48408",
-   131 => x"a02e0981",
-   132 => x"06913880",
-   133 => x"0b80e484",
-   134 => x"0c80e480",
-   135 => x"08810580",
-   136 => x"e4800c02",
-   137 => x"8c050d04",
-   138 => x"02e8050d",
-   139 => x"77795656",
-   140 => x"880bfc16",
-   141 => x"77712c8f",
-   142 => x"06545254",
-   143 => x"80537272",
-   144 => x"25953871",
-   145 => x"53fbe014",
-   146 => x"51877134",
-   147 => x"8114ff14",
-   148 => x"545472f1",
-   149 => x"387153f9",
-   150 => x"1576712c",
-   151 => x"87065351",
-   152 => x"71802e8b",
-   153 => x"38fbe014",
-   154 => x"51717134",
-   155 => x"81145472",
-   156 => x"8e249538",
-   157 => x"8f733153",
-   158 => x"fbe01451",
-   159 => x"a0713481",
-   160 => x"14ff1454",
-   161 => x"5472f138",
-   162 => x"0298050d",
-   163 => x"0402ec05",
-   164 => x"0d800b80",
-   165 => x"e4880cf6",
-   166 => x"8c08f690",
-   167 => x"0871882c",
-   168 => x"565481ff",
-   169 => x"06527372",
-   170 => x"25893871",
-   171 => x"54820b80",
-   172 => x"e4880c72",
-   173 => x"882c7381",
-   174 => x"ff065455",
-   175 => x"7473258d",
-   176 => x"387280e4",
-   177 => x"88088407",
-   178 => x"80e4880c",
-   179 => x"5573842b",
-   180 => x"86a07125",
-   181 => x"83713170",
-   182 => x"0b0b80e0",
-   183 => x"dc0c8171",
-   184 => x"2bff05f6",
-   185 => x"880cfdfc",
-   186 => x"13ff122c",
-   187 => x"788829ff",
-   188 => x"94057081",
-   189 => x"2c80e488",
-   190 => x"08525852",
-   191 => x"55515254",
-   192 => x"76802e85",
-   193 => x"38708107",
-   194 => x"5170f694",
-   195 => x"0c710981",
-   196 => x"05f6800c",
-   197 => x"72098105",
-   198 => x"f6840c02",
-   199 => x"94050d04",
-   200 => x"02f4050d",
-   201 => x"74537270",
-   202 => x"81055480",
-   203 => x"f52d5271",
-   204 => x"802e8938",
-   205 => x"71518384",
-   206 => x"2d86a604",
-   207 => x"810b80e3",
-   208 => x"f00c028c",
-   209 => x"050d0402",
-   210 => x"fc050d81",
-   211 => x"808051c0",
-   212 => x"115170fb",
-   213 => x"38028405",
-   214 => x"0d0402fc",
-   215 => x"050dec51",
-   216 => x"83710c86",
-   217 => x"c72d8271",
-   218 => x"0c028405",
-   219 => x"0d0402fc",
-   220 => x"050dec51",
-   221 => x"8a710c86",
-   222 => x"c72d86c7",
-   223 => x"2d86c72d",
-   224 => x"86c72d86",
-   225 => x"c72d86c7",
-   226 => x"2d86c72d",
-   227 => x"86c72d86",
-   228 => x"c72d86c7",
-   229 => x"2d86c72d",
-   230 => x"86c72d86",
-   231 => x"c72d86c7",
-   232 => x"2d86c72d",
-   233 => x"86c72d86",
-   234 => x"c72d86c7",
-   235 => x"2d86c72d",
-   236 => x"86c72d86",
-   237 => x"c72d86c7",
-   238 => x"2d86c72d",
-   239 => x"86c72d86",
-   240 => x"c72d86c7",
-   241 => x"2d86c72d",
-   242 => x"86c72d86",
-   243 => x"c72d86c7",
-   244 => x"2d86c72d",
-   245 => x"86c72d86",
-   246 => x"c72d86c7",
-   247 => x"2d86c72d",
-   248 => x"86c72d86",
-   249 => x"c72d86c7",
-   250 => x"2d86c72d",
-   251 => x"86c72d86",
-   252 => x"c72d86c7",
-   253 => x"2d86c72d",
-   254 => x"86c72d86",
-   255 => x"c72d86c7",
-   256 => x"2d86c72d",
-   257 => x"86c72d86",
-   258 => x"c72d86c7",
-   259 => x"2d86c72d",
-   260 => x"86c72d86",
-   261 => x"c72d86c7",
-   262 => x"2d86c72d",
-   263 => x"86c72d86",
-   264 => x"c72d86c7",
-   265 => x"2d86c72d",
-   266 => x"86c72d86",
-   267 => x"c72d86c7",
-   268 => x"2d86c72d",
-   269 => x"86c72d86",
-   270 => x"c72d86c7",
-   271 => x"2d86c72d",
-   272 => x"86c72d86",
-   273 => x"c72d86c7",
-   274 => x"2d86c72d",
-   275 => x"86c72d86",
-   276 => x"c72d86c7",
-   277 => x"2d86c72d",
-   278 => x"86c72d86",
-   279 => x"c72d86c7",
-   280 => x"2d86c72d",
-   281 => x"86c72d86",
-   282 => x"c72d86c7",
-   283 => x"2d86c72d",
-   284 => x"86c72d86",
-   285 => x"c72d86c7",
-   286 => x"2d86c72d",
-   287 => x"86c72d86",
-   288 => x"c72d86c7",
-   289 => x"2d86c72d",
-   290 => x"86c72d86",
-   291 => x"c72d86c7",
-   292 => x"2d86c72d",
-   293 => x"86c72d86",
-   294 => x"c72d86c7",
-   295 => x"2d86c72d",
-   296 => x"86c72d86",
-   297 => x"c72d86c7",
-   298 => x"2d86c72d",
-   299 => x"86c72d86",
-   300 => x"c72d86c7",
-   301 => x"2d86c72d",
-   302 => x"86c72d86",
-   303 => x"c72d86c7",
-   304 => x"2d86c72d",
-   305 => x"86c72d86",
-   306 => x"c72d86c7",
-   307 => x"2d86c72d",
-   308 => x"86c72d86",
-   309 => x"c72d86c7",
-   310 => x"2d86c72d",
-   311 => x"86c72d86",
-   312 => x"c72d86c7",
-   313 => x"2d86c72d",
-   314 => x"86c72d86",
-   315 => x"c72d86c7",
-   316 => x"2d86c72d",
-   317 => x"86c72d86",
-   318 => x"c72d86c7",
-   319 => x"2d86c72d",
-   320 => x"86c72d86",
-   321 => x"c72d86c7",
-   322 => x"2d86c72d",
-   323 => x"86c72d86",
-   324 => x"c72d86c7",
-   325 => x"2d86c72d",
-   326 => x"86c72d86",
-   327 => x"c72d86c7",
-   328 => x"2d86c72d",
-   329 => x"86c72d86",
-   330 => x"c72d86c7",
-   331 => x"2d86c72d",
-   332 => x"86c72d86",
-   333 => x"c72d86c7",
-   334 => x"2d86c72d",
-   335 => x"86c72d86",
-   336 => x"c72d86c7",
-   337 => x"2d86c72d",
-   338 => x"86c72d86",
-   339 => x"c72d86c7",
-   340 => x"2d86c72d",
-   341 => x"86c72d86",
-   342 => x"c72d86c7",
-   343 => x"2d86c72d",
-   344 => x"86c72d86",
-   345 => x"c72d86c7",
-   346 => x"2d86c72d",
-   347 => x"86c72d86",
-   348 => x"c72d86c7",
-   349 => x"2d86c72d",
-   350 => x"86c72d86",
-   351 => x"c72d86c7",
-   352 => x"2d86c72d",
-   353 => x"86c72d86",
-   354 => x"c72d86c7",
-   355 => x"2d86c72d",
-   356 => x"86c72d86",
-   357 => x"c72d86c7",
-   358 => x"2d86c72d",
-   359 => x"86c72d86",
-   360 => x"c72d86c7",
-   361 => x"2d86c72d",
-   362 => x"86c72d86",
-   363 => x"c72d86c7",
-   364 => x"2d86c72d",
-   365 => x"86c72d86",
-   366 => x"c72d86c7",
-   367 => x"2d86c72d",
-   368 => x"86c72d86",
-   369 => x"c72d86c7",
-   370 => x"2d86c72d",
-   371 => x"86c72d86",
-   372 => x"c72d86c7",
-   373 => x"2d86c72d",
-   374 => x"86c72d86",
-   375 => x"c72d86c7",
-   376 => x"2d86c72d",
-   377 => x"86c72d86",
-   378 => x"c72d86c7",
-   379 => x"2d86c72d",
-   380 => x"86c72d86",
-   381 => x"c72d86c7",
-   382 => x"2d86c72d",
-   383 => x"86c72d86",
-   384 => x"c72d86c7",
-   385 => x"2d86c72d",
-   386 => x"86c72d86",
-   387 => x"c72d86c7",
-   388 => x"2d86c72d",
-   389 => x"86c72d86",
-   390 => x"c72d86c7",
-   391 => x"2d86c72d",
-   392 => x"86c72d86",
-   393 => x"c72d86c7",
-   394 => x"2d86c72d",
-   395 => x"86c72d86",
-   396 => x"c72d86c7",
-   397 => x"2d86c72d",
-   398 => x"86c72d86",
-   399 => x"c72d86c7",
-   400 => x"2d86c72d",
-   401 => x"86c72d86",
-   402 => x"c72d86c7",
-   403 => x"2d86c72d",
-   404 => x"86c72d86",
-   405 => x"c72d86c7",
-   406 => x"2d86c72d",
-   407 => x"86c72d86",
-   408 => x"c72d86c7",
-   409 => x"2d86c72d",
-   410 => x"86c72d86",
-   411 => x"c72d86c7",
-   412 => x"2d86c72d",
-   413 => x"86c72d86",
-   414 => x"c72d86c7",
-   415 => x"2d86c72d",
-   416 => x"86c72d86",
-   417 => x"c72d86c7",
-   418 => x"2d86c72d",
-   419 => x"86c72d86",
-   420 => x"c72d86c7",
-   421 => x"2d86c72d",
-   422 => x"86c72d86",
-   423 => x"c72d86c7",
-   424 => x"2d86c72d",
-   425 => x"86c72d86",
-   426 => x"c72d86c7",
-   427 => x"2d86c72d",
-   428 => x"86c72d86",
-   429 => x"c72d86c7",
-   430 => x"2d86c72d",
-   431 => x"86c72d86",
-   432 => x"c72d86c7",
-   433 => x"2d86c72d",
-   434 => x"86c72d86",
-   435 => x"c72d86c7",
-   436 => x"2d86c72d",
-   437 => x"86c72d86",
-   438 => x"c72d86c7",
-   439 => x"2d86c72d",
-   440 => x"86c72d86",
-   441 => x"c72d86c7",
-   442 => x"2d86c72d",
-   443 => x"86c72d86",
-   444 => x"c72d86c7",
-   445 => x"2d86c72d",
-   446 => x"86c72d86",
-   447 => x"c72d86c7",
-   448 => x"2d86c72d",
-   449 => x"86c72d86",
-   450 => x"c72d86c7",
-   451 => x"2d86c72d",
-   452 => x"86c72d86",
-   453 => x"c72d86c7",
-   454 => x"2d86c72d",
-   455 => x"86c72d86",
-   456 => x"c72d86c7",
-   457 => x"2d86c72d",
-   458 => x"86c72d86",
-   459 => x"c72d86c7",
-   460 => x"2d86c72d",
-   461 => x"86c72d86",
-   462 => x"c72d86c7",
-   463 => x"2d86c72d",
-   464 => x"86c72d86",
-   465 => x"c72d86c7",
-   466 => x"2d86c72d",
-   467 => x"86c72d86",
-   468 => x"c72d86c7",
-   469 => x"2d86c72d",
-   470 => x"86c72d86",
-   471 => x"c72d86c7",
-   472 => x"2d86c72d",
-   473 => x"86c72d86",
-   474 => x"c72d86c7",
-   475 => x"2d86c72d",
-   476 => x"86c72d86",
-   477 => x"c72d86c7",
-   478 => x"2d86c72d",
-   479 => x"86c72d86",
-   480 => x"c72d86c7",
-   481 => x"2d86c72d",
-   482 => x"86c72d86",
-   483 => x"c72d86c7",
-   484 => x"2d86c72d",
-   485 => x"86c72d86",
-   486 => x"c72d86c7",
-   487 => x"2d86c72d",
-   488 => x"86c72d86",
-   489 => x"c72d86c7",
-   490 => x"2d86c72d",
-   491 => x"86c72d86",
-   492 => x"c72d86c7",
-   493 => x"2d86c72d",
-   494 => x"86c72d86",
-   495 => x"c72d86c7",
-   496 => x"2d86c72d",
-   497 => x"86c72d86",
-   498 => x"c72d86c7",
-   499 => x"2d86c72d",
-   500 => x"86c72d86",
-   501 => x"c72d86c7",
-   502 => x"2d86c72d",
-   503 => x"86c72d86",
-   504 => x"c72d86c7",
-   505 => x"2d86c72d",
-   506 => x"86c72d86",
-   507 => x"c72d86c7",
-   508 => x"2d86c72d",
-   509 => x"86c72d86",
-   510 => x"c72d86c7",
-   511 => x"2d86c72d",
-   512 => x"86c72d86",
-   513 => x"c72d86c7",
-   514 => x"2d86c72d",
-   515 => x"86c72d86",
-   516 => x"c72d86c7",
-   517 => x"2d86c72d",
-   518 => x"86c72d86",
-   519 => x"c72d86c7",
-   520 => x"2d86c72d",
-   521 => x"86c72d86",
-   522 => x"c72d86c7",
-   523 => x"2d86c72d",
-   524 => x"86c72d86",
-   525 => x"c72d86c7",
-   526 => x"2d86c72d",
-   527 => x"86c72d86",
-   528 => x"c72d86c7",
-   529 => x"2d86c72d",
-   530 => x"86c72d86",
-   531 => x"c72d86c7",
-   532 => x"2d86c72d",
-   533 => x"86c72d86",
-   534 => x"c72d86c7",
-   535 => x"2d86c72d",
-   536 => x"86c72d86",
-   537 => x"c72d86c7",
-   538 => x"2d86c72d",
-   539 => x"86c72d86",
-   540 => x"c72d86c7",
-   541 => x"2d86c72d",
-   542 => x"86c72d86",
-   543 => x"c72d86c7",
-   544 => x"2d86c72d",
-   545 => x"86c72d86",
-   546 => x"c72d86c7",
-   547 => x"2d86c72d",
-   548 => x"86c72d86",
-   549 => x"c72d86c7",
-   550 => x"2d86c72d",
-   551 => x"86c72d86",
-   552 => x"c72d86c7",
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+  1802 => x"00000002",
+  1803 => x"0000210e",
+  1804 => x"00001785",
+  1805 => x"00000002",
+  1806 => x"0000212c",
+  1807 => x"00001785",
+  1808 => x"00000002",
+  1809 => x"0000214a",
+  1810 => x"00001785",
+  1811 => x"00000002",
+  1812 => x"00002168",
+  1813 => x"00001785",
+  1814 => x"00000002",
+  1815 => x"00002186",
+  1816 => x"00001785",
+  1817 => x"00000002",
+  1818 => x"000021a4",
+  1819 => x"00001785",
+  1820 => x"00000004",
+  1821 => x"00001af0",
+  1822 => x"00000000",
+  1823 => x"00000000",
+  1824 => x"00000000",
+  1825 => x"00001920",
+  1826 => x"00000000",
 	others => x"00000000"
 );
 
diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/host.h b/cores/NES/src/CtrlModule/CtrlModule/Firmware/host.h
index 76116fe..3bb3172 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/Firmware/host.h
+++ b/cores/NES/src/CtrlModule/CtrlModule/Firmware/host.h
@@ -17,6 +17,7 @@
 #define HOST_CONTROL_SELECT 8
 #define HOST_CONTROL_START 16
 #define HOST_CONTROL_LOADER_RESET 32
+#define HOST_CONTROL_MASTER_RESET 64
 
 /* DIP switches / "Front Panel" controls - bits 15 downto 0 */
 #define REG_HOST_SCALERED 0x10
diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/keyboard.h b/cores/NES/src/CtrlModule/CtrlModule/Firmware/keyboard.h
index 531ff40..22fde59 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/Firmware/keyboard.h
+++ b/cores/NES/src/CtrlModule/CtrlModule/Firmware/keyboard.h
@@ -47,6 +47,8 @@
 #define KEY_1 0x16
 #define KEY_2 0x1E
 
+#define KEY_BACKSP 0x66
+
 
 int HandlePS2RawCodes();
 void ClearKeyboard();
diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/main.c b/cores/NES/src/CtrlModule/CtrlModule/Firmware/main.c
index d38f323..8d8a510 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/Firmware/main.c
+++ b/cores/NES/src/CtrlModule/CtrlModule/Firmware/main.c
@@ -44,6 +44,13 @@ void Delay()
 		c--;
 	}
 }
+void SuperDelay()
+{	int i=1;
+	for (i=1;i<=576;i++)
+	{
+		Delay();
+	}
+}
 void Reset(int row)
 {
 	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_RESET|HOST_CONTROL_DIVERT_KEYBOARD; // Reset host core
@@ -53,56 +60,8 @@ void Reset(int row)
 
 void Select(int row)
 {
-	
 	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_SELECT|HOST_CONTROL_DIVERT_KEYBOARD; // Send select
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
+	SuperDelay();
 	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_DIVERT_KEYBOARD;
 }
 
@@ -110,54 +69,7 @@ void Start(int row)
 {
 	
 	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_START|HOST_CONTROL_DIVERT_KEYBOARD; // Send start
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
+	SuperDelay();
 	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_DIVERT_KEYBOARD;
 }
 
@@ -165,54 +77,14 @@ void ResetLoader()
 {
 	
 	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_LOADER_RESET;
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
-	Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();Delay();
+	SuperDelay();
+}
+
+void masterReset()
+{
+	
+	HW_HOST(REG_HOST_CONTROL)=HOST_CONTROL_MASTER_RESET;
+	SuperDelay();
 }
 
 static struct menu_entry topmenu[]; // Forward declaration.
diff --git a/cores/NES/src/CtrlModule/CtrlModule/Firmware/menu.c b/cores/NES/src/CtrlModule/CtrlModule/Firmware/menu.c
index 469e245..5dfaea0 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/Firmware/menu.c
+++ b/cores/NES/src/CtrlModule/CtrlModule/Firmware/menu.c
@@ -152,6 +152,11 @@ int Menu_Run()
 
 		if(TestKey(KEY_2))
 			Select();
+		// master reset
+		if ((TestKey(KEY_LCTRL) || TestKey(KEY_RCTRL)) && (TestKey(KEY_ALT) || TestKey(KEY_ALTGR)) && TestKey(KEY_BACKSP) ) 
+		{
+			masterReset();
+		}
 		//q
 
 		TestKey(KEY_PAGEUP);
@@ -160,6 +165,11 @@ int Menu_Run()
 		return;
 	}
 
+	// master reset
+	if ((TestKey(KEY_LCTRL) || TestKey(KEY_RCTRL)) && (TestKey(KEY_ALT) || TestKey(KEY_ALTGR)) && TestKey(KEY_BACKSP) ) 
+	{
+		masterReset();
+	}
 
 	if(TestKey(KEY_UPARROW)&2)
 	{
diff --git a/cores/NES/src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd b/cores/NES/src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd
index 968289d..95751aa 100644
--- a/cores/NES/src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd
+++ b/cores/NES/src/CtrlModule/CtrlModule/RTL/CtrlModule.vhd
@@ -45,6 +45,7 @@ entity CtrlModule is
 		host_reset_loader : out std_logic;
 		host_select : out std_logic;
 		host_start : out std_logic;
+		host_master_reset : out std_logic := '0';
 		
 		-- Boot upload signals
 		host_bootdata : out std_logic_vector(31 downto 0);
@@ -326,6 +327,7 @@ begin
 							host_select<=mem_write(3);
 							host_start<=mem_write(4);
 							host_reset_loader <=mem_write(5);
+							host_master_reset <=mem_write(6);
 
 --						when X"F0" => -- Scale Red
 --							mem_busy<='0';
diff --git a/cores/NES/src/GameLoader.v b/cores/NES/src/GameLoader.v
index 4a0d8c6..2a17736 100644
--- a/cores/NES/src/GameLoader.v
+++ b/cores/NES/src/GameLoader.v
@@ -34,8 +34,9 @@ module GameLoader(input clk, input reset,
   reg [21:0] bytes_left;
   
   assign error = (state == 3);
-  wire [7:0] prgrom = ines[4];
-  wire [7:0] chrrom = ines[5];
+  wire [7:0] prgrom = ines[4];	// Number of 16384 byte program ROM pages
+  wire [7:0] chrrom = ines[5];	// Number of 8192 byte character ROM pages (0 indicates CHR RAM)
+  wire has_chr_ram = (chrrom == 0);
   assign mem_data = indata;
   assign mem_write = (bytes_left != 0) && (state == 1 || state == 2) && indata_clk;
   
@@ -55,9 +56,25 @@ module GameLoader(input clk, input reset,
                         chrrom <= 32 ? 5 : 
                         chrrom <= 64 ? 6 : 7;
   
-  wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
-  wire has_chr_ram = (chrrom == 0);
-  assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
+  // detect iNES2.0 compliant header
+  wire is_nes20 = (ines[7][3:2] == 2'b10);
+  // differentiate dirty iNES1.0 headers from proper iNES2.0 ones
+  wire is_dirty = !is_nes20 && ((ines[8]  != 0) 
+									  || (ines[9]  != 0)
+									  || (ines[10] != 0)
+									  || (ines[11] != 0)
+									  || (ines[12] != 0)
+									  || (ines[13] != 0)
+									  || (ines[14] != 0)
+									  || (ines[15] != 0));
+  
+  // Read the mapper number
+  wire [7:0] mapper = {is_dirty ? 4'b0000 : ines[7][7:4], ines[6][7:4]};
+  
+  // ines[6][0] is mirroring
+  // ines[6][3] is 4 screen mode
+  assign mapper_flags = {15'b0, ines[6][3], has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
+  
   always @(posedge clk) begin
     if (reset) begin
       state <= 0;
@@ -72,8 +89,8 @@ module GameLoader(input clk, input reset,
            ines[ctr] <= indata;
            bytes_left <= {prgrom, 14'b0};
            if (ctr == 4'b1111)
-             state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] && !ines[6][3] ? 1 : 3;
-         end
+				 // Check the 'NES' header. Also, we don't support trainers.
+             state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] ? 1 : 3;         end
       1, 2: begin // Read the next |bytes_left| bytes into |mem_addr|
           if (bytes_left != 0) begin
             if (indata_clk) begin
diff --git a/cores/NES/src/NES_ZXUNO.v b/cores/NES/src/NES_ZXUNO.v
index 47a5187..005c5c5 100644
--- a/cores/NES/src/NES_ZXUNO.v
+++ b/cores/NES/src/NES_ZXUNO.v
@@ -51,6 +51,8 @@ module NES_ZXUNO(
   wire host_select;
   wire host_start;
   
+  wire master_reset;
+  
   reg boot_state = 1'b0;
  
   wire [31:0] bootdata;
@@ -127,8 +129,7 @@ module NES_ZXUNO(
   wire [7:0] joystick1, joystick2;
   wire p_sel = !host_select;
   wire p_start = !host_start;
-  assign joystick1 = {~P_R, ~P_L, ~P_D, ~P_U, ~p_start, ~p_sel, ~P_tr, ~P_A};
-  
+  assign joystick1 = {~P_R, ~P_L, ~P_D, ~P_U, ~p_start | (~P_R & ~P_L), ~p_sel | (~P_D & ~P_U), ~P_tr, ~P_A};  
  
   always @(posedge clk) begin
     if (joypad_strobe) begin
@@ -276,7 +277,8 @@ wire [31:0] rom_size;
 			.host_reset_loader(host_reset_loader),
 			.host_bootdata(bootdata), 
 			.host_bootdata_req(bootdata_req), 
-			.host_bootdata_ack(bootdata_ack)
+			.host_bootdata_ack(bootdata_ack),
+			.host_master_reset(master_reset)
 	);
 	
 	OSD_Overlay osd (
@@ -385,4 +387,12 @@ begin
 	loader_input <= dout_fifo;
 //	data <= bytesloaded[19:4];
 end
+
+//-----------------Multiboot-------------
+    multiboot el_multiboot (
+        .clk_icap(clk),
+        .REBOOT(master_reset)
+    );
+
+
 endmodule
diff --git a/cores/NES/src/mmu.v b/cores/NES/src/mmu.v
index 65274b0..f35aa91 100644
--- a/cores/NES/src/mmu.v
+++ b/cores/NES/src/mmu.v
@@ -212,9 +212,12 @@ module MMC2(input clk, input ce, input reset,
     end
   end
   
-  // Update latches when 0x3D8 or 0x3E8 is accessed.
+// PPU reads $0FD8: latch 0 is set to $FD for subsequent reads
+// PPU reads $0FE8: latch 0 is set to $FE for subsequent reads
+// PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
+// PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads
   always @(posedge clk) if (ce && chr_read) begin
-    latch_0 <= (chr_ain & 14'h3ff8) == 14'h0fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h0fe8 ? 1 : latch_0;
+    latch_0 <= (chr_ain & 14'h3fff) == 14'h0fd8 ? 0 : (chr_ain & 14'h3fff) == 14'h0fe8 ? 1 : latch_0;
     latch_1 <= (chr_ain & 14'h3ff8) == 14'h1fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h1fe8 ? 1 : latch_1;
   end
   
@@ -248,8 +251,7 @@ module MMC2(input clk, input ce, input reset,
   assign chr_allow = flags[15];
 endmodule
 
-
-// This mapper also handles mapper 119 and 47.
+// This mapper also handles mapper 47,118,119 and 206.
 module MMC3(input clk, input ce, input reset,
             input [31:0] flags,
             input [15:0] prg_ain, output [21:0] prg_aout,
@@ -279,6 +281,9 @@ module MMC3(input clk, input ce, input reset,
   // TQROM maps 8kB CHR RAM
   wire TQROM = (flags[7:0] == 119);
   wire TxSROM = (flags[7:0] == 118); // Connects CHR A17 to CIRAM A10
+  wire DxROM = (flags[7:0] == 206);
+  
+  wire four_screen_mirroring = flags[16] | DxROM;
   
   // Mapper 47 is a multicart that has 128k for each game. It has no RAM.
   wire mapper47 = (flags[7:0] == 47);
@@ -382,16 +387,144 @@ module MMC3(input clk, input ce, input reset,
   wire [21:0] prg_aout_tmp = {3'b00_0,  prgsel, prg_ain[12:0]};
 
   assign {chr_allow, chr_aout} = 
-      (TQROM && chrsel[6]) ? {1'b1,      9'b11_1111_111, chrsel[2:0], chr_ain[9:0]} :   // TQROM 8kb CHR-RAM
+      (TQROM && chrsel[6])   ? {1'b1,    9'b11_1111_111, chrsel[2:0], chr_ain[9:0]} :   // TQROM 8kb CHR-RAM
+      (four_screen_mirroring && chr_ain[13]) ? {1'b1,    9'b11_1111_111, chr_ain[13], chr_ain[11:0]} :  // DxROM 8kb CHR-RAM
                              {flags[15], 4'b10_00, chrsel, chr_ain[9:0]};               // Standard MMC3
 
   assign prg_is_ram = prg_ain >= 'h6000 && prg_ain < 'h8000 && ram_enable && !(ram_protect && prg_write);
   assign prg_allow = prg_ain[15] && !prg_write || prg_is_ram && !mapper47;
   wire [21:0] prg_ram = {9'b11_1100_000, prg_ain[12:0]};
-  assign prg_aout = prg_is_ram  && !mapper47 ? prg_ram : prg_aout_tmp;
+  assign prg_aout = prg_is_ram  && !mapper47 && !DxROM ? prg_ram : prg_aout_tmp;
   assign vram_a10 = (TxSROM == 0) ? (mirroring ? chr_ain[11] : chr_ain[10]) :
                                     chrsel[7];
+  assign vram_ce = chr_ain[13] && !four_screen_mirroring;
+endmodule
+
+// MMC4 mapper chip. PRG ROM: 256kB. Bank Size: 16kB. CHR ROM: 128kB
+module MMC4(input clk, input ce, input reset,
+            input [31:0] flags,
+            input [15:0] prg_ain, output [21:0] prg_aout,
+            input prg_read, prg_write,                   // Read / write signals
+            input [7:0] prg_din,
+            output prg_allow,                            // Enable access to memory for the specified operation.
+            input chr_read, input [13:0] chr_ain, output [21:0] chr_aout,
+            output chr_allow,                      		// Allow write
+            output vram_a10,                             // Value for A10 address line
+            output vram_ce);                             // True if the address should be routed to the internal 2kB VRAM.
+
+// PRG ROM bank select ($A000-$AFFF)
+// 7  bit  0
+// ---- ----
+// xxxx PPPP
+//      ||||
+//      ++++- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
+  reg [3:0] prg_bank;
+
+// CHR ROM $FD/0000 bank select ($B000-$BFFF)
+// 7  bit  0
+// ---- ----
+// xxxC CCCC
+//    | ||||
+//    +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
+//            used when latch 0 = $FD
+  reg   [4:0] chr_bank_0a;
+
+// CHR ROM $FE/0000 bank select ($C000-$CFFF)
+// 7  bit  0
+// ---- ----
+// xxxC CCCC
+//    | ||||
+//    +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
+//            used when latch 0 = $FE
+   reg [4:0] chr_bank_0b;
+   
+// CHR ROM $FD/1000 bank select ($D000-$DFFF)
+// 7  bit  0
+// ---- ----
+// xxxC CCCC
+//    | ||||
+//    +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
+//            used when latch 1 = $FD
+  reg [4:0] chr_bank_1a;
+   
+// CHR ROM $FE/1000 bank select ($E000-$EFFF)
+// 7  bit  0
+// ---- ----
+// xxxC CCCC
+//    | ||||
+//    +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
+//            used when latch 1 = $FE
+  reg [4:0] chr_bank_1b; 
+  
+// Mirroring ($F000-$FFFF)
+// 7  bit  0
+// ---- ----
+// xxxx xxxM
+//         |
+//         +- Select nametable mirroring (0: vertical; 1: horizontal)  
+  reg mirroring;
+  
+  reg latch_0, latch_1;
+  
+  // Update registers
+  always @(posedge clk) if (ce) begin
+    if (reset)
+	   prg_bank <= 4'b1110;	  
+    else if (prg_write && prg_ain[15]) begin
+      case(prg_ain[14:12])
+      2: prg_bank <= prg_din[3:0];     // $A000
+      3: chr_bank_0a <= prg_din[4:0];  // $B000
+      4: chr_bank_0b <= prg_din[4:0];  // $C000
+      5: chr_bank_1a <= prg_din[4:0];  // $D000
+      6: chr_bank_1b <= prg_din[4:0];  // $E000
+      7: mirroring <=  prg_din[0];     // $F000
+      endcase
+    end
+  end
+  
+// PPU reads $0FD8 through $0FDF: latch 0 is set to $FD for subsequent reads
+// PPU reads $0FE8 through $0FEF: latch 0 is set to $FE for subsequent reads
+// PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
+// PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads
+  always @(posedge clk) if (ce && chr_read) begin
+    latch_0 <= (chr_ain & 14'h3ff8) == 14'h0fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h0fe8 ? 1 : latch_0;
+    latch_1 <= (chr_ain & 14'h3ff8) == 14'h1fd8 ? 0 : (chr_ain & 14'h3ff8) == 14'h1fe8 ? 1 : latch_1;
+  end
+  
+  // The PRG bank to load. Each increment here is 16kb. So valid values are 0..15.
+  reg [3:0] prgsel;
+  always @* begin
+    casez(prg_ain[14])
+    1'b0:    prgsel = prg_bank;
+    default: prgsel = 4'b1111;
+    endcase
+  end
+  wire [21:0] prg_aout_tmp = {4'b00_00, prgsel, prg_ain[13:0]};
+
+  // The CHR bank to load. Each increment here is 4kb. So valid values are 0..31.
+  reg [4:0] chrsel;
+  always @* begin
+    casez({chr_ain[12], latch_0, latch_1})
+    3'b00?: chrsel = chr_bank_0a;
+    3'b01?: chrsel = chr_bank_0b;
+    3'b1?0: chrsel = chr_bank_1a;
+    3'b1?1: chrsel = chr_bank_1b;
+    endcase
+  end
+  assign chr_aout = {5'b100_00, chrsel, chr_ain[11:0]};
+  
+  // The a10 VRAM address line. (Used for mirroring)
+  assign vram_a10 = mirroring ? chr_ain[11] : chr_ain[10];
   assign vram_ce = chr_ain[13];
+  
+  assign chr_allow = flags[15];
+  
+  wire prg_is_ram = prg_ain >= 'h6000 && prg_ain < 'h8000;
+  assign prg_allow = prg_ain[15] && !prg_write ||
+                     prg_is_ram;
+  wire [21:0] prg_ram = {9'b11_1100_000, prg_ain[12:0]};
+  assign prg_aout = prg_is_ram ? prg_ram : prg_aout_tmp;
+
 endmodule
 
 module MMC5(input clk, input ce, input reset,
@@ -762,7 +895,7 @@ module Rambo1(input clk, input ce, input reset,
     {chr_bank_0, chr_bank_1} <= 0;
     {chr_bank_2, chr_bank_3, chr_bank_4, chr_bank_5} <= 0;
     {chr_bank_8, chr_bank_9} <= 0;
-    {prg_bank_0, prg_bank_1, prg_bank_2} <= 0;
+    {prg_bank_0, prg_bank_1, prg_bank_2} <= 6'b111111;
     irq_cycle_mode <= 0;
     cycle_counter <= 0;
     irq <= 0;
@@ -1592,6 +1725,11 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
   MMC3 mmc3(clk, ppu_ce, reset, flags, prg_ain, mmc3_prg_addr, prg_read, prg_write, prg_din, mmc3_prg_allow,
                                    chr_ain, mmc3_chr_addr, mmc3_chr_allow, mmc3_vram_a10, mmc3_vram_ce, mmc3_irq);
 
+  wire mmc4_prg_allow, mmc4_vram_a10, mmc4_vram_ce, mmc4_chr_allow;
+  wire [21:0] mmc4_prg_addr, mmc4_chr_addr;
+  MMC4 mmc4(clk, ppu_ce, reset, flags, prg_ain, mmc4_prg_addr, prg_read, prg_write, prg_din, mmc4_prg_allow,
+                                   chr_read, chr_ain, mmc4_chr_addr, mmc4_chr_allow, mmc4_vram_a10, mmc4_vram_ce);
+
   wire mmc5_prg_allow, mmc5_vram_a10, mmc5_vram_ce, mmc5_chr_allow, mmc5_irq;
   wire [21:0] mmc5_prg_addr, mmc5_chr_addr;
   wire [7:0] mmc5_chr_dout, mmc5_prg_dout;
@@ -1703,8 +1841,11 @@ module MultiMapper(input clk, input ce, input ppu_ce, input reset,
     118, // TxSROM connects A17 to CIRAM A10.
     119, // TQROM  uses the Nintendo MMC3 like other TxROM boards but uses the CHR bank number specially.
     47,  // Mapper 047 is a MMC3 multicart
+	 206, // MMC3 w/o IRQ or WRAM support
     4:  {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow, irq} = {mmc3_prg_addr, mmc3_prg_allow, mmc3_chr_addr, mmc3_vram_a10, mmc3_vram_ce, mmc3_chr_allow, mmc3_irq};
 
+    10: {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow}      = {mmc4_prg_addr, mmc4_prg_allow, mmc4_chr_addr, mmc4_vram_a10, mmc4_vram_ce, mmc4_chr_allow};
+	 
     5:  {prg_aout, prg_allow, chr_aout, vram_a10, vram_ce, chr_allow, has_chr_dout, prg_dout, irq} = {mmc5_prg_addr, mmc5_prg_allow, mmc5_chr_addr, mmc5_vram_a10, mmc5_vram_ce, mmc5_chr_allow, mmc5_has_chr_dout, mmc5_prg_dout, mmc5_irq};
 
     0,
diff --git a/cores/NES/src/multiboot_v4.v b/cores/NES/src/multiboot_v4.v
new file mode 100644
index 0000000..14c951a
--- /dev/null
+++ b/cores/NES/src/multiboot_v4.v
@@ -0,0 +1,310 @@
+module multiboot (
+    input wire clk_icap,
+	 input wire REBOOT
+    );
+              
+    reg [23:0] spi_addr = 24'h058000;  // default: SPI address of second core as defined by the SPI memory map
+
+    reg [4:0] q = 5'b00000;
+    reg reboot_ff = 1'b0;
+
+    always @(posedge clk_icap) begin
+      q[0] <= REBOOT;
+      q[1] <= q[0];
+      q[2] <= q[1];
+      q[3] <= q[2];
+      q[4] <= q[3];
+      reboot_ff <= (q[4] && (!q[3]) && (!q[2]) && (!q[1]) );
+    end
+	 
+    multiboot_spartan6 hacer_multiboot (
+        .CLK(clk_icap),
+        .MBT_RESET(1'b0),
+        .MBT_REBOOT(reboot_ff),
+        .spi_addr(spi_addr)
+    );
+endmodule            
+    
+module multiboot_spartan6 (
+    input wire CLK,
+    input wire MBT_RESET,
+    input wire MBT_REBOOT,
+    input wire [23:0] spi_addr
+  );
+
+reg  [15:0] icap_din;
+reg         icap_ce;
+reg         icap_wr;
+
+reg  [15:0] ff_icap_din_reversed;
+reg         ff_icap_ce;
+reg         ff_icap_wr;
+
+
+  ICAP_SPARTAN6 ICAP_SPARTAN6_inst (
+  
+    .CE        (ff_icap_ce),   // Clock enable input
+    .CLK       (CLK),         // Clock input
+    .I         (ff_icap_din_reversed),  // 16-bit data input
+    .WRITE     (ff_icap_wr)    // Write input
+  );
+
+
+//  -------------------------------------------------
+//  --  State Machine for ICAP_SPARTAN6 MultiBoot  --
+//  -------------------------------------------------
+
+
+parameter         IDLE     = 0, 
+                  SYNC_H   = 1, 
+                  SYNC_L   = 2, 
+                  
+                  CWD_H    = 3,  
+                  CWD_L    = 4,  
+                                 
+                  GEN1_H   = 5,  
+                  GEN1_L   = 6,  
+                                 
+                  GEN2_H   = 7,  
+                  GEN2_L   = 8,  
+                                 
+                  GEN3_H   = 9,  
+                  GEN3_L   = 10, 
+                                 
+                  GEN4_H   = 11, 
+                  GEN4_L   = 12, 
+                                 
+                  GEN5_H   = 13, 
+                  GEN5_L   = 14, 
+                                 
+                  NUL_H    = 15, 
+                  NUL_L    = 16, 
+                                 
+                  MOD_H    = 17, 
+                  MOD_L    = 18, 
+                                 
+                  HCO_H    = 19, 
+                  HCO_L    = 20, 
+                                 
+                  RBT_H    = 21, 
+                  RBT_L    = 22, 
+                  
+                  NOOP_0   = 23, 
+                  NOOP_1   = 24,
+                  NOOP_2   = 25,
+                  NOOP_3   = 26;
+                  
+                   
+reg [4:0]     state;
+reg [4:0]     next_state;
+
+
+always @*
+   begin: COMB
+
+      case (state)
+      
+         IDLE:
+            begin
+               if (MBT_REBOOT)
+                  begin
+                     next_state  = SYNC_H;
+                     icap_ce     = 0;
+                     icap_wr     = 0;
+                     icap_din    = 16'hAA99;  // Sync word 1 
+                  end
+               else
+                  begin
+                     next_state  = IDLE;
+                     icap_ce     = 1;
+                     icap_wr     = 1;
+                     icap_din    = 16'hFFFF;  // Null 
+                  end
+            end
+            
+         SYNC_H:
+            begin
+               next_state  = SYNC_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h5566;    // Sync word 2
+            end
+
+         SYNC_L:
+            begin
+               next_state  = NUL_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h30A1;    //  Write to Command Register....
+            end
+
+        NUL_H:
+            begin
+              // next_state  = NUL_L;
+	       next_state  = GEN1_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h0000;   //  Null Command issued....  value = 0x0000
+            end
+
+//Q
+
+         GEN1_H:
+            begin
+               next_state  = GEN1_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3261;    //  Escritura a reg GENERAL_1 (bit boot en caliente)
+            end
+
+        GEN1_L:
+            begin
+               next_state  = GEN2_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = spi_addr[15:0]; //16'hC000;   //  dreccion SPI BAJA
+            end
+
+         GEN2_H:
+            begin
+               next_state  = GEN2_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3281;   //  Escritura a reg GENERAL_2
+            end
+
+        GEN2_L:
+            begin
+               next_state  = MOD_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = {8'h6B, spi_addr[23:16]}; // 16'h030A;   //  03 lectura SPI opcode + direccion SPI ALTA (03 = 1x, 6B = 4x)
+            end
+	
+///////	Registro MODE (para carga a 4x tras reboot)
+
+        MOD_H:
+            begin
+               next_state  = MOD_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3301;   //  Escritura a reg MODE
+            end
+
+        MOD_L:
+            begin
+               next_state  = NUL_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h3100; // Activamos bit de lectura a modo 4x en el proceso de Config
+            end				
+/////
+
+        NUL_L:
+            begin
+               next_state  = RBT_H;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h30A1;    //  Write to Command Register....
+            end
+
+        RBT_H:
+            begin
+               next_state  = RBT_L;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h000E;    // REBOOT Command 0x000E
+            end
+
+//--------------------
+
+        RBT_L:
+            begin
+               next_state  = NOOP_0;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    //  NOOP
+            end
+
+        NOOP_0:
+            begin
+               next_state  = NOOP_1;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+        NOOP_1:
+            begin
+               next_state  = NOOP_2;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+        NOOP_2:
+            begin
+               next_state  = NOOP_3;
+               icap_ce     = 0;
+               icap_wr     = 0;
+               icap_din    = 16'h2000;    // NOOP
+            end
+
+//--------------------
+
+        NOOP_3:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16'h1111;    // NULL value
+            end
+          
+        default:
+            begin
+               next_state  = IDLE;
+               icap_ce     = 1;
+               icap_wr     = 1;
+               icap_din    = 16'h1111;    //  16'h1111"
+            end
+
+      endcase
+   end
+
+always @(posedge CLK)
+
+   begin:   SEQ
+      if (MBT_RESET)
+         state <= IDLE;
+      else
+         state <= next_state;
+   end
+
+
+always @(posedge CLK)
+
+   begin:   ICAP_FF
+   
+        ff_icap_din_reversed[0]  <= icap_din[7];   //need to reverse bits to ICAP module since D0 bit is read first
+        ff_icap_din_reversed[1]  <= icap_din[6]; 
+        ff_icap_din_reversed[2]  <= icap_din[5]; 
+        ff_icap_din_reversed[3]  <= icap_din[4]; 
+        ff_icap_din_reversed[4]  <= icap_din[3]; 
+        ff_icap_din_reversed[5]  <= icap_din[2]; 
+        ff_icap_din_reversed[6]  <= icap_din[1]; 
+        ff_icap_din_reversed[7]  <= icap_din[0]; 
+        ff_icap_din_reversed[8]  <= icap_din[15];
+        ff_icap_din_reversed[9]  <= icap_din[14];
+        ff_icap_din_reversed[10] <= icap_din[13];
+        ff_icap_din_reversed[11] <= icap_din[12];
+        ff_icap_din_reversed[12] <= icap_din[11];
+        ff_icap_din_reversed[13] <= icap_din[10];
+        ff_icap_din_reversed[14] <= icap_din[9]; 
+        ff_icap_din_reversed[15] <= icap_din[8]; 
+        
+        ff_icap_ce  <= icap_ce;
+        ff_icap_wr  <= icap_wr;
+   end  
+        
+        
+endmodule
diff --git a/cores/NES/xilinx/NES_ZXUNO.prj b/cores/NES/xilinx/NES_ZXUNO.prj
index 85ea51e..9053cd5 100644
--- a/cores/NES/xilinx/NES_ZXUNO.prj
+++ b/cores/NES/xilinx/NES_ZXUNO.prj
@@ -15,6 +15,7 @@ vhdl work "../src/CtrlModule/CtrlModule/Firmware/CtrlROM_ROM.vhd"
 verilog work "../src/vga.v"
 verilog work "../src/sigma_delta_dac.v"
 verilog work "../src/nes.v"
+verilog work "../src/multiboot_v4.v"
 verilog work "../src/memorycontroller.v"
 verilog work "../src/hq2x.v"
 verilog work "../src/GameLoader.v"
diff --git a/cores/NES/xilinx/NES_ZXUNO.xst b/cores/NES/xilinx/NES_ZXUNO.xst
index 4ccf3f5..3a8c425 100644
--- a/cores/NES/xilinx/NES_ZXUNO.xst
+++ b/cores/NES/xilinx/NES_ZXUNO.xst
@@ -9,6 +9,7 @@ run
 -opt_mode Speed
 -opt_level 1
 -power NO
+-uc "timings.xcf"
 -iuc NO
 -keep_hierarchy No
 -netlist_hierarchy As_Optimized
diff --git a/cores/NES/xilinx/timings.xcf b/cores/NES/xilinx/timings.xcf
new file mode 100644
index 0000000..0310d07
--- /dev/null
+++ b/cores/NES/xilinx/timings.xcf
@@ -0,0 +1,2 @@
+# Timing constraints
+NET "CLOCK_50" PERIOD=20 ns;