mirror of https://github.com/zxdos/zxuno.git
SamCoupe a test4 (final)
This commit is contained in:
antoniovillena
parent
e6c3fca97a
commit
d22cd23c8e
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@ -226,23 +226,29 @@ module asic (
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mem_contention = 1'b0;
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io_contention = 1'b0;
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if (screen_off == 1'b0 && hc[3:0]<4'd10)
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io_contention = 1'b1;
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if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
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hc[3:0]==4'd1 ||
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hc[3:0]==4'd8 ||
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hc[3:0]==4'd9) )
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io_contention = 1'b1;
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// if (screen_off == 1'b0 && hc[3:0]<4'd10)
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// io_contention = 1'b1;
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// if (screen_off == 1'b1 && (hc[3:0]==4'd0 ||
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// hc[3:0]==4'd1 ||
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// hc[3:0]==4'd8 ||
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// hc[3:0]==4'd9) )
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// io_contention = 1'b1;
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if (fetching_pixels == 1'b1 && hc[3:0]<4'd10)
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if (fetching_pixels == 1'b1 && hc[3:0]<4'd10) begin
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mem_contention = 1'b1;
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//io_contention = 1'b1;
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end
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if (fetching_pixels == 1'b0 && (hc[3:0]==4'd0 ||
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hc[3:0]==4'd1 ||
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hc[3:0]==4'd8 ||
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hc[3:0]==4'd9) )
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hc[3:0]==4'd9) ) begin
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mem_contention = 1'b1;
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if (screen_mode == 2'b00 && hc[3:0]<4'd10 && (hc<10'd128 || hc>=10'd256))
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//io_contention = 1'b1;
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end
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if (screen_mode == 2'b00 && hc[3:0]<4'd10 && (hc<10'd128 || hc>=10'd256)) begin
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mem_contention = 1'b1; // extra contention for MODE 1
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//io_contention = 1'b1;
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end
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end
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assign asic_is_using_ram = mem_contention & fetching_pixels;
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@ -1,34 +1,34 @@
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# Clocks & debug
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NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
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#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
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#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
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NET "clk50mhz" PERIOD=20 ns;
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NET "clk12" PERIOD=83 ns;
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# Video output
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NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
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NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
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NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
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NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
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NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
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NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
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NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
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NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
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NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
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NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
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#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
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NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
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NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
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NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
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NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
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NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
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NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
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NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
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NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
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NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
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NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
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NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
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NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
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#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
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NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
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NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
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# Sound input/output
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NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
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NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
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NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
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NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
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NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
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NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
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# Keyboard and mouse
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NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
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NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
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#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
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#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
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NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
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NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
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#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
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#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
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# SRAM
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NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
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@ -51,34 +51,32 @@ NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
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NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
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NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
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NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
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NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
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NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
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NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
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NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
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NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
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NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
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NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
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NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
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NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
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NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
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NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
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NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
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NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
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NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
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NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
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# SPI Flash
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#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
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#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
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#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
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#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
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#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
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#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
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# SD/MMC
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#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
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#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
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#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
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#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
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#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
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#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
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#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
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#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
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# JOYSTICK
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#NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
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#NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
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#NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
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#NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
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#NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
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#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
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#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
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#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
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#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
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#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
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@ -0,0 +1,82 @@
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# Clocks & debug
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NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
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#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
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NET "clk50mhz" PERIOD=20 ns;
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NET "clk12" PERIOD=83 ns;
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# Video output
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NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
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NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
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NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
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NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
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NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
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NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
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NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
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NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
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NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
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NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
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#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
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NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
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NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
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# Sound input/output
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NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
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NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
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NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
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# Keyboard and mouse
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NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
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NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
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#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
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#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
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# SRAM
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NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
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NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
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NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
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NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
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NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
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NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
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NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
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NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
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NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
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NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
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# SPI Flash
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#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
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#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
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#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
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#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
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# SD/MMC
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#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
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#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
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#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
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#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
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# JOYSTICK
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#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
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#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
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#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
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#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
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#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
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@ -0,0 +1,107 @@
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# Clocks & debug
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NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
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#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
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NET "clk50mhz" PERIOD=20 ns;
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NET "clk12" PERIOD=83 ns;
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# Video output
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NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
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NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
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NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
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NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
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NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
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NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
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NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
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NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
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NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
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NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
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#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
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NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
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NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
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# Sound input/output
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NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
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NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
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NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
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# Keyboard and mouse
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NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
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NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
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#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
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#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
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# SRAM
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NET "sram_addr<0>" LOC="P139" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<1>" LOC="P140" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<2>" LOC="P141" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<3>" LOC="P142" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<4>" LOC="P143" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<5>" LOC="P137" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<6>" LOC="P134" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<7>" LOC="P133" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<8>" LOC="P131" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<9>" LOC="P117" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<10>" LOC="P116" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<11>" LOC="P115" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<12>" LOC="P114" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<13>" LOC="P112" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<14>" LOC="P99" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<15>" LOC="P100" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<16>" LOC="P101" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<17>" LOC="P102" | IOSTANDARD = LVCMOS33;
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NET "sram_addr<18>" LOC="P104" | IOSTANDARD = LVCMOS33;
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#NET "sram_addr<0>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<1>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<2>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<3>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<4>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<5>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<7>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<8>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<9>" LOC="P99" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<10>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<11>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<12>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<13>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<14>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<16>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<17>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<18>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_we_n" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
#NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
#NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
#NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
#NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# Clocks & debug
|
||||
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
|
||||
NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "clk50mhz" PERIOD=20 ns;
|
||||
NET "clk12" PERIOD=83 ns;
|
||||
|
||||
# Video output
|
||||
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
|
||||
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
|
||||
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
|
||||
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
|
||||
NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33;
|
||||
NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
|
||||
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Sound input/output
|
||||
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
|
||||
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
|
||||
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Keyboard and mouse
|
||||
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
|
||||
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
|
||||
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
|
||||
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
|
||||
|
||||
# SRAM
|
||||
NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
|
||||
NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SPI Flash
|
||||
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
|
||||
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# SD/MMC
|
||||
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
|
||||
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
|
||||
|
||||
# JOYSTICK
|
||||
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
|
||||
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
|
||||
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
|
||||
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
|
||||
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
|
||||
#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5
|
||||
|
|
@ -65,6 +65,7 @@ module ps2_keyb(
|
|||
wire extended;
|
||||
wire released;
|
||||
assign scancode_dout = kbcode;
|
||||
wire teclado_limpio;
|
||||
|
||||
/*
|
||||
| BSY | x | x | x | ERR | RLS | EXT | PEN |
|
||||
|
|
@ -101,6 +102,7 @@ module ps2_keyb(
|
|||
.scan(kbcode),
|
||||
.extended(extended),
|
||||
.released(released),
|
||||
.kbclean(teclado_limpio),
|
||||
.sam_row(rows),
|
||||
.sam_col(cols),
|
||||
.master_reset(master_reset),
|
||||
|
|
@ -114,6 +116,16 @@ module ps2_keyb(
|
|||
.rewind(regaddr_changed == 1'b1 && zxuno_addr == KEYMAP)
|
||||
);
|
||||
|
||||
keyboard_pressed_status comprueba_teclado_limpio (
|
||||
.clk(clk),
|
||||
.rst(1'b0),
|
||||
.scan_received(nueva_tecla),
|
||||
.scancode(kbcode),
|
||||
.extended(extended),
|
||||
.released(released),
|
||||
.kbclean(teclado_limpio)
|
||||
);
|
||||
|
||||
ps2_host_to_kb escritura_a_teclado (
|
||||
.clk(clk),
|
||||
.ps2clk_ext(clkps2),
|
||||
|
|
|
|||
|
|
@ -35,59 +35,10 @@ module ram_dual_port_turnos (
|
|||
inout wire [7:0] sram_d
|
||||
);
|
||||
|
||||
parameter ASIC = 2'd0,
|
||||
CPUADDR = 2'd1,
|
||||
CPUWRITE = 2'd2;
|
||||
|
||||
// assign sram_d = ((state == CPUADDR && cpu_we_n == 1'b0) || state == CPUWRITE)? data_from_cpu : 8'hZZ;
|
||||
// assign sram_we_n = (cpu_we_n == 1'b0 && state == CPUWRITE)? 1'b0 : 1'b1;
|
||||
|
||||
// reg [1:0] state = ASIC;
|
||||
// always @(posedge clk) begin
|
||||
// case (state)
|
||||
// ASIC:
|
||||
// begin
|
||||
// data_to_asic <= sram_d;
|
||||
// if (whichturn == 1'b0) begin
|
||||
// sram_a <= cpuramaddr;
|
||||
// state <= CPUADDR;
|
||||
// end
|
||||
// else
|
||||
// sram_a <= vramaddr;
|
||||
// end
|
||||
// CPUADDR:
|
||||
// begin
|
||||
// data_to_cpu <= sram_d;
|
||||
// if (whichturn == 1'b1) begin
|
||||
// sram_a <= vramaddr;
|
||||
// state <= ASIC;
|
||||
// end
|
||||
// else begin
|
||||
// sram_a <= cpuramaddr;
|
||||
// if (cpu_we_n == 1'b0) begin
|
||||
// state <= CPUWRITE;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// CPUWRITE:
|
||||
// begin
|
||||
// if (whichturn == 1'b1) begin
|
||||
// sram_a <= vramaddr;
|
||||
// state <= ASIC;
|
||||
// end
|
||||
// else if (cpu_we_n == 1'b1) begin
|
||||
// sram_a <= cpuramaddr;
|
||||
// state <= CPUADDR;
|
||||
// end
|
||||
// end
|
||||
// default: state <= ASIC;
|
||||
// endcase
|
||||
// end
|
||||
|
||||
assign sram_d = (cpu_we_n == 1'b0 && whichturn == 1'b0)? data_from_cpu : 8'hZZ;
|
||||
always @* begin
|
||||
//data_to_cpu = 8'hFF;
|
||||
//data_to_asic = 8'hFF;
|
||||
data_to_cpu = 8'hFF;
|
||||
data_to_asic = 8'hFF;
|
||||
if (whichturn == 1'b1) begin // ASIC
|
||||
sram_a = vramaddr;
|
||||
sram_we_n = 1'b1;
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ module relojes
|
|||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_DIVIDE (100),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_DIVIDE (75),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
|
|
|
|||
|
|
@ -536,8 +536,8 @@ module saa1099_envelope_gen (
|
|||
stereoshape <= 1'b0;
|
||||
envshape <= 3'b000;
|
||||
envclock <= 1'b0;
|
||||
write_to_address_prev = 1'b0;
|
||||
write_to_data_prev = 1'b0;
|
||||
write_to_address_prev <= 1'b0;
|
||||
write_to_data_prev <= 1'b0;
|
||||
pending_data <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
|
|
|
|||
|
|
@ -0,0 +1,187 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="samcoupe.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_sam.bgn" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="tld_sam.bit" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="tld_sam.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="tld_sam.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="tld_sam.drc" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="tld_sam.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_sam.ncd" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="tld_sam.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="tld_sam.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="tld_sam.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="tld_sam.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="tld_sam.par" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="tld_sam.pcf" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tld_sam.prj"/>
|
||||
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="tld_sam.ptwx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="tld_sam.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="tld_sam.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="tld_sam.twr" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="tld_sam.twx" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="tld_sam.unroutes" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_sam.ut" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_XPI" xil_pn:name="tld_sam.xpi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="tld_sam.xst"/>
|
||||
<file xil_pn:fileType="FILE_NCD" xil_pn:name="tld_sam_guide.ncd" xil_pn:origination="imported"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_sam_map.map" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_sam_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_sam_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="tld_sam_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_sam_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_sam_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="tld_sam_pad.csv" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="tld_sam_pad.txt" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_sam_par.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_sam_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="tld_sam_summary.xml"/>
|
||||
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="tld_sam_usage.xml"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_sam_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6115208449814914759" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8108781279231808984" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1343511641341017349" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477811" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2805040128463979342" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460477935" xil_pn:in_ck="-5783567514349303730" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="9121203831162331750" xil_pn:start_ts="1460477811">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_sam.lso"/>
|
||||
<outfile xil_pn:name="tld_sam.ngc"/>
|
||||
<outfile xil_pn:name="tld_sam.ngr"/>
|
||||
<outfile xil_pn:name="tld_sam.prj"/>
|
||||
<outfile xil_pn:name="tld_sam.stx"/>
|
||||
<outfile xil_pn:name="tld_sam.syr"/>
|
||||
<outfile xil_pn:name="tld_sam.xst"/>
|
||||
<outfile xil_pn:name="tld_sam_xst.xrpt"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460479194" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981284104174886" xil_pn:start_ts="1460479193">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460479217" xil_pn:in_ck="-8396312258588544680" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-2060531862303609495" xil_pn:start_ts="1460479194">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_sam.bld"/>
|
||||
<outfile xil_pn:name="tld_sam.ngd"/>
|
||||
<outfile xil_pn:name="tld_sam_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460479307" xil_pn:in_ck="-8396312258588544679" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1460479217">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_sam.pcf"/>
|
||||
<outfile xil_pn:name="tld_sam_map.map"/>
|
||||
<outfile xil_pn:name="tld_sam_map.mrp"/>
|
||||
<outfile xil_pn:name="tld_sam_map.ncd"/>
|
||||
<outfile xil_pn:name="tld_sam_map.ngm"/>
|
||||
<outfile xil_pn:name="tld_sam_map.xrpt"/>
|
||||
<outfile xil_pn:name="tld_sam_summary.xml"/>
|
||||
<outfile xil_pn:name="tld_sam_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460479383" xil_pn:in_ck="4953532180165969138" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1460479307">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_sam.ncd"/>
|
||||
<outfile xil_pn:name="tld_sam.pad"/>
|
||||
<outfile xil_pn:name="tld_sam.par"/>
|
||||
<outfile xil_pn:name="tld_sam.ptwx"/>
|
||||
<outfile xil_pn:name="tld_sam.unroutes"/>
|
||||
<outfile xil_pn:name="tld_sam.xpi"/>
|
||||
<outfile xil_pn:name="tld_sam_pad.csv"/>
|
||||
<outfile xil_pn:name="tld_sam_pad.txt"/>
|
||||
<outfile xil_pn:name="tld_sam_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460479453" xil_pn:in_ck="182820444665985127" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7369995838840786959" xil_pn:start_ts="1460479383">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_sam.bgn"/>
|
||||
<outfile xil_pn:name="tld_sam.bit"/>
|
||||
<outfile xil_pn:name="tld_sam.drc"/>
|
||||
<outfile xil_pn:name="tld_sam.ut"/>
|
||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1460479383" xil_pn:in_ck="-8396312258588544811" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1460479362">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="tld_sam.twr"/>
|
||||
<outfile xil_pn:name="tld_sam.twx"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
|
|
@ -159,7 +159,7 @@ module samcoupe (
|
|||
);
|
||||
|
||||
ram_dual_port_turnos ram_512k (
|
||||
.clk(clk24),
|
||||
.clk(1'b0 /*clk24*/),
|
||||
.whichturn(asic_is_using_ram),
|
||||
.vramaddr(vramaddr),
|
||||
.cpuramaddr(cpuramaddr),
|
||||
|
|
|
|||
|
|
@ -9,89 +9,89 @@
|
|||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="asic.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="tb_asic.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="rom.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="ram.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="samcoupe.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="tld_sam.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="pines_zxuno.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="relojes.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="tb_samcoupe.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_alu.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_core.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_mcode.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80_reg.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="tv80n.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2_keyb.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="ps2_port.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="scancode_to_speccy.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="saa1099.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="audio_management.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="pines_zxuno.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
|
|
@ -104,6 +104,7 @@
|
|||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
|
|
@ -115,7 +116,7 @@
|
|||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="Full-Parallel" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -126,7 +127,7 @@
|
|||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -143,11 +144,12 @@
|
|||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -163,6 +165,7 @@
|
|||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
|
|
@ -185,7 +188,6 @@
|
|||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -196,7 +198,7 @@
|
|||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
|
|
@ -225,7 +227,9 @@
|
|||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
|
|
@ -235,6 +239,7 @@
|
|||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
|
|
@ -247,7 +252,7 @@
|
|||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -290,7 +295,6 @@
|
|||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
|
|
@ -321,7 +325,6 @@
|
|||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
|
|
@ -364,6 +367,7 @@
|
|||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
|
@ -395,7 +399,7 @@
|
|||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
|
|
@ -415,9 +419,7 @@
|
|||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/tld_sam" xil_pn:name="pines_zxuno.ucf"/>
|
||||
</bindings>
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ module scancode_to_sam (
|
|||
input wire [7:0] scan,
|
||||
input wire extended,
|
||||
input wire released,
|
||||
input wire kbclean,
|
||||
//------------------------
|
||||
input wire [8:0] sam_row,
|
||||
output wire [7:0] sam_col,
|
||||
|
|
@ -118,7 +119,7 @@ module scancode_to_sam (
|
|||
always @(posedge clk) begin
|
||||
if (scan_received == 1'b1)
|
||||
key_is_pending <= 1'b1;
|
||||
if (rst == 1'b1)
|
||||
if (rst == 1'b1 || (kbclean == 1'b1 && state == IDLE && scan_received == 1'b0))
|
||||
state <= CLEANMATRIX;
|
||||
else begin
|
||||
case (state)
|
||||
|
|
@ -219,7 +220,7 @@ module scancode_to_sam (
|
|||
end
|
||||
CPUTIME: begin
|
||||
if (rewind == 1'b1) begin
|
||||
cpuaddr = 14'h0000;
|
||||
cpuaddr <= 14'h0000;
|
||||
state <= IDLE;
|
||||
end
|
||||
else if (cpuread == 1'b1) begin
|
||||
|
|
@ -247,19 +248,6 @@ module scancode_to_sam (
|
|||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
// else if (state == UPDCOUNTERS1) begin
|
||||
// if (~released)
|
||||
// keycount <= keycount + 4'b0001; // suma 1 al contador de pulsaciones
|
||||
// else if (released && keycount != 4'b0000)
|
||||
// keycount <= keycount + 4'b1111; // o le resta 1 al contador de pulsaciones, pero sin bajar de 0
|
||||
// state <= UPDCOUNTERS2;
|
||||
// end
|
||||
// else if (state == UPDCOUNTERS2) begin
|
||||
// if (keycount == 4'b0000) // si es la última tecla soltada, limpia la matriz de teclado del Spectrum
|
||||
// state <= CLEANMATRIX;
|
||||
// else
|
||||
// state <= IDLE;
|
||||
// end
|
||||
default: begin
|
||||
state <= IDLE;
|
||||
end
|
||||
|
|
@ -267,3 +255,86 @@ module scancode_to_sam (
|
|||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module keyboard_pressed_status (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire scan_received,
|
||||
input wire [7:0] scancode,
|
||||
input wire extended,
|
||||
input wire released,
|
||||
output reg kbclean
|
||||
);
|
||||
|
||||
parameter
|
||||
RESETTING = 2'd0,
|
||||
UPDATING = 2'd1,
|
||||
SCANNING = 2'd2;
|
||||
|
||||
reg keybstat_ne[0:255]; // non extended keymap
|
||||
reg keybstat_ex[0:255]; // extended keymap
|
||||
reg [7:0] addrscan = 8'h00; // keymap bit address
|
||||
reg keypressed_ne = 1'b0; // there is at least one key pressed
|
||||
reg keypressed_ex = 1'b0; // there is at least one extended key pressed
|
||||
reg [1:0] state = RESETTING;
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
kbclean = 1'b1;
|
||||
for (i=0;i<256;i=i+1) begin
|
||||
keybstat_ne[i] = 1'b0;
|
||||
keybstat_ex[i] = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst == 1'b1) begin
|
||||
state <= RESETTING;
|
||||
addrscan <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case (state)
|
||||
RESETTING:
|
||||
begin
|
||||
if (addrscan == 8'hFF) begin
|
||||
addrscan <= 8'h00;
|
||||
state <= SCANNING;
|
||||
kbclean <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
keybstat_ne[addrscan] <= 1'b0;
|
||||
keybstat_ex[addrscan] <= 1'b0;
|
||||
addrscan <= addrscan + 8'd1;
|
||||
end
|
||||
end
|
||||
UPDATING:
|
||||
begin
|
||||
state <= SCANNING;
|
||||
addrscan <= 8'h00;
|
||||
kbclean <= 1'b0;
|
||||
keypressed_ne <= 1'b0;
|
||||
keypressed_ex <= 1'b0;
|
||||
if (extended == 1'b0)
|
||||
keybstat_ne[scancode] <= ~released;
|
||||
else
|
||||
keybstat_ex[scancode] <= ~released;
|
||||
end
|
||||
SCANNING:
|
||||
begin
|
||||
if (scan_received == 1'b1)
|
||||
state <= UPDATING;
|
||||
addrscan <= addrscan + 8'd1;
|
||||
if (addrscan == 8'hFF) begin
|
||||
kbclean <= ~(keypressed_ne | keypressed_ex);
|
||||
keypressed_ne <= 1'b0;
|
||||
keypressed_ex <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
keypressed_ne <= keypressed_ne | keybstat_ne[addrscan];
|
||||
keypressed_ex <= keypressed_ex | keybstat_ex[addrscan];
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue