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Actualizo Oric

This commit is contained in:
antoniovillena 2016-05-04 22:25:41 +02:00
parent 75e2043f7f
commit d5de44e85e
11 changed files with 388 additions and 465 deletions
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2
cores/JupiterAce/jupiter_ace_zxuno_Ap.ucf
View File

@ -48,6 +48,8 @@ NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;

429
cores/Oric/FPGAOric.xise
View File

@ -1,429 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="source/dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="source/keyboard/keyboard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="source/keyboard/keymap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="source/keyboard/keymatrix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="source/m6522.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="source/oricatmos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="source/keyboard/ps2key.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="source/rom_oa.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="source/T65/T65.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="source/T65/T65_MCode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="source/T65/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="source/T65/T65_Pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="source/ram48k.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="source/ram16k.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="source/YM2149_linmix.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="source/scan_converter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="source/ula.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="source/oric_zxuno.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ORIC|RTL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../source/oricatmos.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ORIC" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="ORIC" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ORIC_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ORIC_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ORIC_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ORIC_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="ORIC" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/simul_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.simul_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.simul_test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.5/ISE_DS/ISE/spartan6/data/spartan6_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="build" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|simul_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-08-04T14:35:10" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="75120E1B02AE4FBFB07CDCF24D5B0430" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

17
cores/Oric/build/ORIC.prj Normal file
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@ -0,0 +1,17 @@
vhdl work "../source/T65/T65_Pack.vhd"
vhdl work "../source/T65/T65_MCode.vhd"
vhdl work "../source/T65/T65_ALU.vhd"
vhdl work "../source/ram16k.vhd"
vhdl work "../source/keyboard/ps2key.vhd"
vhdl work "../source/keyboard/keymatrix.vhd"
vhdl work "../source/keyboard/keymap.vhd"
vhdl work "../source/YM2149_linmix.vhd"
vhdl work "../source/ula.vhd"
vhdl work "../source/T65/T65.vhd"
vhdl work "../source/scan_converter.vhd"
vhdl work "../source/rom_oa.vhd"
vhdl work "../source/ram48k.vhd"
vhdl work "../source/m6522.vhd"
vhdl work "../source/keyboard/keyboard.vhd"
vhdl work "../source/dac.vhd"
vhdl work "../source/oricatmos.vhd"

30
cores/Oric/build/ORIC.ut Normal file
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@ -0,0 +1,30 @@
-w
-g Binary:no
-g Compress
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

52
cores/Oric/build/ORIC.xst Normal file
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@ -0,0 +1,52 @@
set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn ORIC.prj
-ofn ORIC
-ofmt NGC
-p xc6slx9-3-tqg144
-top ORIC
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

7
cores/Oric/build/make.bat Normal file
View File

@ -0,0 +1,7 @@
SET machine=oric
SET ruta_ucf=..\source\oric
SET ruta_bat=..\..\
call %ruta_bat%genxst.bat
call %ruta_bat%generar.bat v2_v3
call %ruta_bat%generar.bat v4
call %ruta_bat%generar.bat Ap

35
cores/Oric/source/oric_zxuno.ucf
View File

@ -1,35 +0,0 @@
#UCF for ZX-UNO
NET "CLK_50" LOC = "P55" | IOSTANDARD = LVCMOS33 | PERIOD=20ns ;
NET "CLK_50" TNM_NET = "CLK_50" ;
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;
# Audio
NET "AUDIO_OUT" LOC = "P8" | IOSTANDARD = LVCMOS33 ;
NET "K7_TAPEOUT" LOC = "P9" | IOSTANDARD = LVCMOS33 ;
# Switch
NET "I_RESET" LOC = "P51" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "PS2DAT1" LOC = "P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "PS2CLK1" LOC = "P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "K7_TAPEIN" LOC = "P105" | IOSTANDARD = LVCMOS33;
NET O_HSYNC LOC = "P87" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC = "P85" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC = "P81" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(1) LOC = "P80" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(0) LOC = "P79" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC = "P84" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(1) LOC = "P83" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(0) LOC = "P82" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(2) LOC = "P93" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(1) LOC = "P92" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(0) LOC = "P88" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_NTSC LOC = "P67" | IOSTANDARD = LVCMOS33;
NET O_PAL LOC = "P66" | IOSTANDARD = LVCMOS33;

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#UCF for ZX-UNO
NET "CLK_50" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
NET O_VIDEO_R(2) LOC="P97" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(1) LOC="P95" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(0) LOC="P94" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC="P88" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(1) LOC="P87" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(0) LOC="P85" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC="P84" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(1) LOC="P83" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(0) LOC="P82" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_HSYNC LOC="P93" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC="P92" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_NTSC LOC="P51" | IOSTANDARD = LVCMOS33;
NET O_PAL LOC="P50" | IOSTANDARD = LVCMOS33;
# Audio
NET "AUDIO_OUT" LOC="P98" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEOUT" LOC="P99" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEIN" LOC="P1" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "PS2CLK1" LOC="P143" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "PS2DAT1" LOC="P142" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Switch
NET "I_RESET" LOC="P51" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;

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#UCF for ZX-UNO
NET "CLK_50" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET O_VIDEO_R(2) LOC="P93" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(1) LOC="P92" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(0) LOC="P88" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC="P84" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC="P81" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(1) LOC="P80" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(0) LOC="P79" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_HSYNC LOC="P87" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC="P85" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_NTSC LOC="P67" | IOSTANDARD = LVCMOS33;
NET O_PAL LOC="P66" | IOSTANDARD = LVCMOS33;
# Audio
NET "AUDIO_OUT" LOC="P8" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEOUT" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEIN" LOC="P105" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "PS2CLK1" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "PS2DAT1" LOC="P97" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
# Switch
NET "I_RESET" LOC="P51" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;

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#UCF for ZX-UNO
NET "CLK_50" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET O_VIDEO_R(2) LOC="P81" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC="P84" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC="P93" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_HSYNC LOC="P87" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC="P85" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS33;
NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS33;
# Audio
NET "AUDIO_OUT" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEOUT" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEIN" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "PS2CLK1" LOC="P99" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
NET "PS2DAT1" LOC="P98" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P123 | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Switch
NET "I_RESET" LOC="P51" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;