From e26f31f869c18555ba40084f67238bcc1609e407 Mon Sep 17 00:00:00 2001 From: antoniovillena Date: Thu, 28 Apr 2016 14:33:22 +0200 Subject: [PATCH] =?UTF-8?q?Spectrum=20test20=20(=C3=BAltima=20versi=C3=B3n?= =?UTF-8?q?)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- cores/Spectrum/bootloader_hex.txt | 263 +- cores/Spectrum/control_rasterint.v | 78 + cores/Spectrum/coreid.v | 8 +- cores/Spectrum/cuatro_relojes.v | 210 +- cores/Spectrum/genkeybmap_av.c | 432 + cores/Spectrum/genkeybmap_es.c | 4 +- cores/Spectrum/genkeybmap_us.c | 3 + cores/Spectrum/keyb_av_hex.txt | 16384 +++++++++++++++++++++ cores/Spectrum/keyb_es_hex.txt | 20 +- cores/Spectrum/keymaps/AV | Bin 0 -> 16384 bytes cores/Spectrum/keymaps/ES | Bin 16384 -> 16384 bytes cores/Spectrum/keymaps/US | Bin 16384 -> 16384 bytes cores/Spectrum/memory.v | 11 +- cores/Spectrum/multiboot.v | 359 + cores/Spectrum/multiboot_v4.v | 359 + cores/Spectrum/pal_sync_generator.v | 170 + cores/Spectrum/par_usage_statistics.html | 45 +- cores/Spectrum/pines_zxuno.ucf | 109 +- cores/Spectrum/pines_zxuno_Ap.ucf | 84 + cores/Spectrum/pines_zxuno_v3.ucf | 88 + cores/Spectrum/pines_zxuno_v4.ucf | 85 + cores/Spectrum/pll_drp.v | 1729 +++ cores/Spectrum/pll_drp_func.h | 641 + cores/Spectrum/pll_top.v | 353 + cores/Spectrum/ps2_mouse_kempston.v | 2 +- cores/Spectrum/rom.v | 6 +- cores/Spectrum/scancode_to_speccy.v | 97 +- cores/Spectrum/scandoubler_ctrl.v | 58 + cores/Spectrum/scratch_register.v | 2 + cores/Spectrum/timings_pentagon128.png | Bin 0 -> 20113 bytes cores/Spectrum/tld_zxuno.v | 102 +- cores/Spectrum/ula_radas.v | 89 +- cores/Spectrum/vga_scandoubler.v | 175 + cores/Spectrum/zxuno.gise | 105 +- cores/Spectrum/zxuno.v | 102 +- cores/Spectrum/zxuno.xise | 234 +- 36 files changed, 21771 insertions(+), 636 deletions(-) create mode 100644 cores/Spectrum/control_rasterint.v create mode 100644 cores/Spectrum/genkeybmap_av.c create mode 100644 cores/Spectrum/keyb_av_hex.txt create mode 100644 cores/Spectrum/keymaps/AV create mode 100644 cores/Spectrum/multiboot.v create mode 100644 cores/Spectrum/multiboot_v4.v create mode 100644 cores/Spectrum/pal_sync_generator.v create mode 100644 cores/Spectrum/pines_zxuno_Ap.ucf create mode 100644 cores/Spectrum/pines_zxuno_v3.ucf create mode 100644 cores/Spectrum/pines_zxuno_v4.ucf create mode 100644 cores/Spectrum/pll_drp.v create mode 100644 cores/Spectrum/pll_drp_func.h create mode 100644 cores/Spectrum/pll_top.v create mode 100644 cores/Spectrum/scandoubler_ctrl.v create mode 100644 cores/Spectrum/timings_pentagon128.png create mode 100644 cores/Spectrum/vga_scandoubler.v diff --git a/cores/Spectrum/bootloader_hex.txt b/cores/Spectrum/bootloader_hex.txt index 838b2c1..ba17a89 100644 --- a/cores/Spectrum/bootloader_hex.txt +++ b/cores/Spectrum/bootloader_hex.txt @@ -1,38 +1,94 @@ -F3 +31 +B1 +BF +11 +61 +C7 +D5 +11 +80 +ED +D5 +01 +AE +BF +18 +2B +DF +20 +05 +C9 +32 +30 +31 +36 +3E +16 +3D +20 +FD +04 +C8 +DB +FE +A9 +E6 +40 +28 +F7 +18 +43 01 3B FD -F7 -03 -01 -31 +E1 +ED +A3 +06 +FE +ED +A3 +E9 +5A +58 +55 +6E +6F +C3 +43 +C0 +F3 +C5 +EF +06 +10 EF -BF -3E -0A -F7 01 08 -F7 +DB +1F +F6 +E7 +3C +28 +28 +EF +03 +01 +AF +EF 03 00 -F7 +EF 02 03 ED 79 -11 -61 -E9 -D5 -56 -D5 39 ED -61 +59 ED -69 -2B +79 ED A2 04 @@ -43,65 +99,116 @@ FA ED 61 04 +C9 C3 -EC -BF -E1 -ED -A3 -06 -FE -ED -A3 -E9 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -C3 -00 +40 C0 ED 45 +79 +EE +47 +4F +D3 +FE +C9 +11 +53 +00 +DD +63 +CD +84 +00 +DD +21 +00 +C0 +11 +02 +40 +2E +62 +E5 +3E +0F +D3 +FE +0E +0A +DF +20 +FD +AF +29 +10 +FD +3D +20 +FA +D7 +28 +F3 +06 +9C +D7 +28 +EE +3E +C6 +B8 +30 +E9 +24 +20 +F3 +06 +C9 +DF +28 +E1 +78 +FE +D4 +30 +F6 +DF +28 +0E +EE +03 +4F +DD +75 +FE +DD +23 +1B +2E +01 +06 +B2 +D7 +28 +FE +3E +CB +B8 +CB +15 +30 +F4 +7C +AD +67 +7A +B3 +20 +E5 +B4 +20 +FE +01 +3B +FC +C9 diff --git a/cores/Spectrum/control_rasterint.v b/cores/Spectrum/control_rasterint.v new file mode 100644 index 0000000..5996078 --- /dev/null +++ b/cores/Spectrum/control_rasterint.v @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +`default_nettype none + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:24:57 12/06/2015 +// Design Name: +// Module Name: control_rasterint +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module rasterint_ctrl ( + input wire clk, + input wire rst_n, + input wire [7:0] zxuno_addr, + input wire zxuno_regrd, + input wire zxuno_regwr, + input wire [7:0] din, + output reg [7:0] dout, + output reg oe_n, + output wire rasterint_enable, + output wire vretraceint_disable, + output wire [8:0] raster_line, + input wire raster_int_in_progress + ); + + parameter RASTERLINE = 8'h0C; + parameter RASTERCTRL = 8'h0D; + + reg [7:0] rasterline_reg = 8'hFF; + reg raster_enable = 1'b0; + reg vretrace_disable = 1'b0; + reg raster_8th_bit = 1'b1; + + assign raster_line = {raster_8th_bit, rasterline_reg}; + assign rasterint_enable = raster_enable; + assign vretraceint_disable = vretrace_disable; + + always @(posedge clk) begin + if (rst_n == 1'b0) begin + raster_enable <= 1'b0; + vretrace_disable <= 1'b0; + raster_8th_bit <= 1'b1; + rasterline_reg <= 8'hFF; + end + else begin + if (zxuno_addr == RASTERLINE && zxuno_regwr == 1'b1) + rasterline_reg <= din; + if (zxuno_addr == RASTERCTRL && zxuno_regwr == 1'b1) + {vretrace_disable, raster_enable, raster_8th_bit} <= din[2:0]; + end + end + + always @* begin + dout = 8'hFF; + oe_n = 1'b1; + if (zxuno_addr == RASTERLINE && zxuno_regrd == 1'b1) begin + dout = rasterline_reg; + oe_n = 1'b0; + end + if (zxuno_addr == RASTERCTRL && zxuno_regrd == 1'b1) begin + dout = {raster_int_in_progress, 4'b0000, vretrace_disable, raster_enable, raster_8th_bit}; + oe_n = 1'b0; + end + end +endmodule diff --git a/cores/Spectrum/coreid.v b/cores/Spectrum/coreid.v index 3f814f9..8218390 100644 --- a/cores/Spectrum/coreid.v +++ b/cores/Spectrum/coreid.v @@ -36,13 +36,13 @@ module coreid ( for (i=0;i<16;i=i+1) text[i] = 8'h00; text[ 0] = "T"; - text[ 1] = "1"; - text[ 2] = "9"; + text[ 1] = "2"; + text[ 2] = "0"; text[ 3] = "-"; text[ 4] = "0"; - text[ 5] = "3"; + text[ 5] = "7"; text[ 6] = "1"; - text[ 7] = "0"; + text[ 7] = "2"; text[ 8] = "2"; text[ 9] = "0"; text[10] = "1"; diff --git a/cores/Spectrum/cuatro_relojes.v b/cores/Spectrum/cuatro_relojes.v index 3656dc1..5b911ce 100644 --- a/cores/Spectrum/cuatro_relojes.v +++ b/cores/Spectrum/cuatro_relojes.v @@ -1,162 +1,74 @@ -// file: tres_relojes.v -// -// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// CLK_OUT1 28.000 0.000 50.0 297.991 199.399 -// CLK_OUT2 14.000 180.000 50.0 342.124 199.399 -// CLK_OUT3 7.000 180.000 50.0 391.159 199.399 -// -//---------------------------------------------------------------------------- -// Input Clock Input Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// primary 50 0.010 - `timescale 1ps/1ps `default_nettype none -(* CORE_GENERATION_INFO = "tres_relojes,clk_wiz_v1_8,{component_name=tres_relojes,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *) -module cuatro_relojes +/* Change parameters using this online C code: http://goo.gl/Os0cKi */ + +module clock_generator (// Clock in ports input wire CLK_IN1, + input wire CPUContention, + input wire [2:0] pll_option, + input wire turbo_enable, // Clock out ports output wire CLK_OUT1, output wire CLK_OUT2, output wire CLK_OUT3, - output wire CLK_OUT4 - ); + output wire CLK_OUT4, + output wire cpuclk + ); + + wire cpuclk_selected; + + reg [2:0] pll_option_stored = 3'b000; + reg [7:0] pulso_reconf = 8'h01; // force initial reset at boot + always @(posedge CLK_IN1) begin + if (pll_option != pll_option_stored) begin + pll_option_stored <= pll_option; + pulso_reconf <= 8'b00000001; + end + else begin + pulso_reconf <= {pulso_reconf[6:0],1'b0}; + end + end - wire clkin1,clkout0,clkout1,clkout2,clkout3; - // Input buffering - //------------------------------------ - IBUFG clkin1_buf - (.O (clkin1), - .I (CLK_IN1)); + pll_top reconfiguracion_pll + ( + // SSTEP is the input to start a reconfiguration. It should only be + // pulsed for one clock cycle. + .SSTEP(pulso_reconf[7]), + // STATE determines which state the PLL_ADV will be reconfigured to. A + // value of 0 correlates to state 1, and a value of 1 correlates to state + // 2. + .STATE(pll_option_stored), + // RST will reset the entire reference design including the PLL_ADV + .RST(1'b0), + // CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the + // clock for the PLL_DRP module + .CLKIN(CLK_IN1), + // SRDY pulses for one clock cycle after the PLL_ADV is locked and the + // PLL_DRP module is ready to start another re-configuration + .SRDY(), + + // These are the clock outputs from the PLL_ADV. + .CLK0OUT(CLK_OUT1), + .CLK1OUT(CLK_OUT2), + .CLK2OUT(CLK_OUT3), + .CLK3OUT(CLK_OUT4) + ); - - // Clocking primitive - //------------------------------------ - // Instantiation of the PLL primitive - // * Unused inputs are tied off - // * Unused outputs are labeled unused - wire [15:0] do_unused; - wire drdy_unused; - wire locked_unused; - wire clkfbout; - wire clkfbout_buf; - wire clkout4_unused; - wire clkout5_unused; - - PLL_BASE - #(.BANDWIDTH ("OPTIMIZED"), - .CLK_FEEDBACK ("CLKFBOUT"), - .COMPENSATION ("SYSTEM_SYNCHRONOUS"), - .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT (9), - .CLKFBOUT_PHASE (0.000), - .CLKOUT0_DIVIDE (16), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT1_DIVIDE (32), - .CLKOUT1_PHASE (0.000), - .CLKOUT1_DUTY_CYCLE (0.500), - .CLKOUT2_DIVIDE (64), - .CLKOUT2_PHASE (0.000), - .CLKOUT3_DIVIDE (128), - .CLKOUT3_PHASE (0.000), - .CLKOUT2_DUTY_CYCLE (0.500), - .CLKIN_PERIOD (20.0), - .REF_JITTER (0.010)) - pll_base_inst - // Output clocks - (.CLKFBOUT (clkfbout), - .CLKOUT0 (clkout0), - .CLKOUT1 (clkout1), - .CLKOUT2 (clkout2), - .CLKOUT3 (clkout3), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .LOCKED (locked_unused), - .RST (1'b0), - // Input clock control - .CLKFBIN (clkfbout_buf), - .CLKIN (clkin1)); - - - // Output buffering - //----------------------------------- - BUFG clkf_buf - (.O (clkfbout_buf), - .I (clkfbout)); - - - BUFG clkout1_buf - (.O (CLK_OUT1), - .I (clkout0)); - - - BUFG clkout2_buf - (.O (CLK_OUT2), - .I (clkout1)); - - BUFG clkout3_buf - (.O (CLK_OUT3), - .I (clkout2)); - - BUFG clkout4_buf - (.O (CLK_OUT4), - .I (clkout3)); + BUFGMUX cpuclk_selector ( + .O(cpuclk_selected), + .I0(CLK_OUT4), + .I1(CLK_OUT3), + .S(turbo_enable) + ); + + BUFGMUX selector_reloj_cpu ( + .O(cpuclk), + .I0(cpuclk_selected), // when no contention, clock is this one + .I1(1'b1), // during contention, clock is pulled up + .S(CPUContention) // contention signal + ); + endmodule diff --git a/cores/Spectrum/genkeybmap_av.c b/cores/Spectrum/genkeybmap_av.c new file mode 100644 index 0000000..a735e5b --- /dev/null +++ b/cores/Spectrum/genkeybmap_av.c @@ -0,0 +1,432 @@ +#include +#include + +typedef unsigned char BYTE; +/* + 8 8 3 5 3 5 +AAADDDDD AAADDDDD MRN JJJJJ MMM XXXXX + +AAA = semifila del teclado a modificar | esta información está +DDDDD = dato (AND negado con lo que haya) de esa semifila | repetida para dos teclas +MRN = Master reset, Reset de usuario, NMI +JJJJJ = estado del joystick al pulsar tecla. Posiciones UDLRX +MMM = la tecla es un modificador +XXXXX = Reservado para uso futuro + +Ej: en la dirección de memoria correspondiente al código de la tecla ESC, +que correspondería a la pulsación simultánea de CAPS SHIFT+SPACE, pondríamos: +00000001 11100001 000 00000 000 00000 +Esto es: se activan las semifilas 0 y 7, y en cada una, se activa el bit 0 + +256 codigos + E0 = 512 codigos +SHIFT, CTRL, ALT = 8 combinaciones + +512*8=4096 direcciones x 32 bits = 16384 bytes +En el core se dispondrá como una memoria de 16384x8 bits + +Cada tecla ocupará cuatro direcciones consecutivas. +D+0 : tecla1 (o 0 si no la hay) +D+1 : tecla2 (o 0 si no la hay) +D+2 : señales de reset y joystick, 0 si no hay +D+3 : modificadores y señales de usuario, 0 si no hay +*/ + +// You shouldn't have to touch these defs unless your Spectrum has a different keyboard +// layout (because, for example, you are using a different ROM + +#define SP_1 0x61 +#define SP_2 0x62 +#define SP_3 0x64 +#define SP_4 0x68 +#define SP_5 0x70 + +#define SP_0 0x81 +#define SP_9 0x82 +#define SP_8 0x84 +#define SP_7 0x88 +#define SP_6 0x90 + +#define SP_Q 0x41 +#define SP_W 0x42 +#define SP_E 0x44 +#define SP_R 0x48 +#define SP_T 0x50 + +#define SP_P 0xA1 +#define SP_O 0xA2 +#define SP_I 0xA4 +#define SP_U 0xA8 +#define SP_Y 0xB0 + +#define SP_A 0x21 +#define SP_S 0x22 +#define SP_D 0x24 +#define SP_F 0x28 +#define SP_G 0x30 + +#define SP_ENTER 0xC1 +#define SP_L 0xC2 +#define SP_K 0xC4 +#define SP_J 0xC8 +#define SP_H 0xD0 + +#define SP_CAPS 0x01 +#define SP_Z 0x02 +#define SP_X 0x04 +#define SP_C 0x08 +#define SP_V 0x10 + +#define SP_SPACE 0xE1 +#define SP_SYMBOL 0xE2 +#define SP_M 0xE4 +#define SP_N 0xE8 +#define SP_B 0xF0 + +#define SP_BANG (SP_SYMBOL<<8) | SP_1 +#define SP_AT (SP_SYMBOL<<8) | SP_2 +#define SP_HASH (SP_SYMBOL<<8) | SP_3 +#define SP_DOLLAR (SP_SYMBOL<<8) | SP_4 +#define SP_PERCEN (SP_SYMBOL<<8) | SP_5 +#define SP_AMP (SP_SYMBOL<<8) | SP_6 +#define SP_APOSTRO (SP_SYMBOL<<8) | SP_7 +#define SP_PAROPEN (SP_SYMBOL<<8) | SP_8 +#define SP_PARCLOS (SP_SYMBOL<<8) | SP_9 +#define SP_UNDERSC (SP_SYMBOL<<8) | SP_0 +#define SP_LESS (SP_SYMBOL<<8) | SP_R +#define SP_LESSEQ (SP_SYMBOL<<8) | SP_Q +#define SP_GREATER (SP_SYMBOL<<8) | SP_T +#define SP_GREATEQ (SP_SYMBOL<<8) | SP_E +#define SP_NOTEQ (SP_SYMBOL<<8) | SP_W +#define SP_BRAOPEN (SP_SYMBOL<<8) | SP_Y +#define SP_BRACLOS (SP_SYMBOL<<8) | SP_U +#define SP_SEMICOL (SP_SYMBOL<<8) | SP_O +#define SP_QUOTE (SP_SYMBOL<<8) | SP_P +#define SP_TILDE (SP_SYMBOL<<8) | SP_A +#define SP_PIPE (SP_SYMBOL<<8) | SP_S +#define SP_BACKSLA (SP_SYMBOL<<8) | SP_D +#define SP_CUROPEN (SP_SYMBOL<<8) | SP_F +#define SP_CURCLOS (SP_SYMBOL<<8) | SP_G +#define SP_CARET (SP_SYMBOL<<8) | SP_H +#define SP_MINUS (SP_SYMBOL<<8) | SP_J +#define SP_PLUS (SP_SYMBOL<<8) | SP_K +#define SP_EQUAL (SP_SYMBOL<<8) | SP_L +#define SP_COLON (SP_SYMBOL<<8) | SP_Z +#define SP_POUND (SP_SYMBOL<<8) | SP_X +#define SP_QUEST (SP_SYMBOL<<8) | SP_C +#define SP_SLASH (SP_SYMBOL<<8) | SP_V +#define SP_STAR (SP_SYMBOL<<8) | SP_B +#define SP_COMMA (SP_SYMBOL<<8) | SP_N +#define SP_DOT (SP_SYMBOL<<8) | SP_M + +#define SP_EXTEND (SP_CAPS<<8) | SP_SYMBOL +#define SP_EDIT (SP_CAPS<<8) | SP_1 +#define SP_CPSLOCK (SP_CAPS<<8) | SP_2 +#define SP_TRUE (SP_CAPS<<8) | SP_3 +#define SP_INVERSE (SP_CAPS<<8) | SP_4 +#define SP_LEFT (SP_CAPS<<8) | SP_5 +#define SP_DOWN (SP_CAPS<<8) | SP_6 +#define SP_UP (SP_CAPS<<8) | SP_7 +#define SP_RIGHT (SP_CAPS<<8) | SP_8 +#define SP_GRAPH (SP_CAPS<<8) | SP_9 +#define SP_DELETE (SP_CAPS<<8) | SP_0 +#define SP_BREAK (SP_CAPS<<8) | SP_SPACE + +// END of Spectrum keys definitions + +// Definitions for additional signals generated by the keyboard core +// AAADDDDD AAADDDDD MRN JJJJJ MMM XXXXX +#define MODIFIER1 0x20 +#define MODIFIER2 0x40 +#define MODIFIER3 0x80 + +#define MRESET 0x80 +#define URESET 0x40 +#define NMI 0x20 + +#define JOYUP 0x10 +#define JOYDOWN 0x08 +#define JOYLEFT 0x04 +#define JOYRIGHT 0x02 +#define JOYFIRE 0x01 + +#define USER5 0x10 +#define USER4 0x08 +#define USER3 0x04 +#define USER2 0x02 +#define USER1 0x01 +// End of additional signals + +// A key can be pressed with up to three key modifiers +// which generates 8 combinations for each key +#define EXT 0x100 +#define MD1 0x200 +#define MD2 0x400 +#define MD3 0x800 + +// Scan code 2 list. First, non localized keys +#define PC_A 0x1C +#define PC_B 0x32 +#define PC_C 0x21 +#define PC_D 0x23 +#define PC_E 0x24 +#define PC_F 0x2B +#define PC_G 0x34 +#define PC_H 0x33 +#define PC_I 0x43 +#define PC_J 0x3B +#define PC_K 0x42 +#define PC_L 0x4B +#define PC_M 0x3A +#define PC_N 0x31 +#define PC_O 0x44 +#define PC_P 0x4D +#define PC_Q 0x15 +#define PC_R 0x2D +#define PC_S 0x1B +#define PC_T 0x2C +#define PC_U 0x3C +#define PC_V 0x2A +#define PC_W 0x1D +#define PC_X 0x22 +#define PC_Y 0x35 +#define PC_Z 0x1A + +#define PC_0 0x45 +#define PC_1 0x16 +#define PC_2 0x1E +#define PC_3 0x26 +#define PC_4 0x25 +#define PC_5 0x2E +#define PC_6 0x36 +#define PC_7 0x3D +#define PC_8 0x3E +#define PC_9 0x46 + +#define PC_F1 0x05 +#define PC_F2 0x06 +#define PC_F3 0x04 +#define PC_F4 0x0C +#define PC_F5 0x03 +#define PC_F6 0x0B +#define PC_F7 0x83 +#define PC_F8 0x0A +#define PC_F9 0x01 +#define PC_F10 0x09 +#define PC_F11 0x78 +#define PC_F12 0x07 + +#define PC_ESC 0x76 +#define PC_SPACE 0x29 +#define PC_LCTRL 0x14 +#define PC_RCTRL 0x14 | EXT +#define PC_LSHIFT 0x12 +#define PC_RSHIFT 0x59 +#define PC_LALT 0x11 +#define PC_RALT 0x11 | EXT +#define PC_LWIN 0x1F | EXT +#define PC_RWIN 0x27 | EXT +#define PC_APPS 0x2F | EXT + +#define PC_TAB 0x0D +#define PC_CPSLOCK 0x58 +#define PC_SCRLOCK 0x7E + +#define PC_INSERT 0x70 | EXT +#define PC_DELETE 0x71 | EXT +#define PC_HOME 0x6C | EXT +#define PC_END 0x69 | EXT +#define PC_PGUP 0x7D | EXT +#define PC_PGDOWN 0x7A | EXT +#define PC_BKSPACE 0x66 +#define PC_ENTER 0x5A +#define PC_UP 0x75 | EXT +#define PC_DOWN 0x72 | EXT +#define PC_LEFT 0x6B | EXT +#define PC_RIGHT 0x74 | EXT + +#define PC_NUMLOCK 0x77 +#define PC_KP_DIVIS 0x4A | EXT +#define PC_KP_MULT 0x7C +#define PC_KP_MINUS 0x7B +#define PC_KP_PLUS 0x79 +#define PC_KP_ENTER 0x5A | EXT +#define PC_KP_DOT 0x71 +#define PC_KP_0 0x70 +#define PC_KP_1 0x69 +#define PC_KP_2 0x72 +#define PC_KP_3 0x7A +#define PC_KP_4 0x6B +#define PC_KP_5 0x73 +#define PC_KP_6 0x74 +#define PC_KP_7 0x6C +#define PC_KP_8 0x75 +#define PC_KP_9 0x7D + +// Localized keyboards start to differenciate from here + +// Localized keyboard ES (Spain) +#define PC_BACKSLA 0x0E +#define PC_APOSTRO 0x4E +#define PC_OPNBANG 0x55 +#define PC_GRAVEAC 0x54 +#define PC_PLUS 0x5B +#define PC_EGNE 0x4C +#define PC_ACUTEAC 0x52 +#define PC_CEDILLA 0x5D +#define PC_LESS 0x61 +#define PC_COMMA 0x41 +#define PC_DOT 0x49 +#define PC_MINUS 0x4A + +#define MAP(pc,sp,rj,mu) { \ + rom[(pc)*4] = (((sp)>>8)&0xFF); \ + rom[(pc)*4+1] = (((sp))&0xFF); \ + rom[(pc)*4+2] = (rj); \ + rom[(pc)*4+3] = (mu); \ + } + +#define MAPANY(pc,sp,rj,mu) { \ + MAP(pc,sp,rj,mu); \ + MAP(MD1|pc,sp,rj,mu); \ + MAP(MD2|pc,sp,rj,mu); \ + MAP(MD3|pc,sp,rj,mu); \ + MAP(MD1|MD2|pc,sp,rj,mu); \ + MAP(MD1|MD3|pc,sp,rj,mu); \ + MAP(MD2|MD3|pc,sp,rj,mu); \ + MAP(MD1|MD2|MD3|pc,sp,rj,mu); \ + } + +#define CLEANMAP { \ + int i; \ + for (i=0;i<(sizeof(rom)/sizeof(rom[0]));i++) \ + rom[i] = 0; \ + } +#define SAVEMAPHEX(name) { \ + FILE *f; \ + int i; \ + f=fopen(name,"w"); \ + for(i=0;i<(sizeof(rom)/sizeof(rom[0]));i++) \ + fprintf(f,"%.2X\n",rom[i]); \ + fclose(f); \ + } + +#define SAVEMAPBIN(name) { \ + FILE *f; \ + int i; \ + f=fopen(name,"wb"); \ + fwrite (rom, 1, sizeof(rom), f); \ + fclose(f); \ + } + +int main() +{ + BYTE rom[16384]; + + CLEANMAP; + + MAPANY(PC_LSHIFT,SP_CAPS,0,0); + MAPANY(PC_RSHIFT,SP_CAPS,0,0); + MAPANY(PC_LCTRL,SP_SYMBOL,0,MODIFIER2); // MD2 is CTRL + MAPANY(PC_RCTRL,SP_SYMBOL,0,MODIFIER2); // MD2 is CTRL + MAPANY(PC_LALT,0,JOYFIRE,MODIFIER3); // MD3 is ALT. Also is FIRE for keyboard joystick + MAPANY(PC_RALT,0,JOYFIRE,MODIFIER3); // MD3 is ALT. Also is FIRE for keyboard joystick + + // Basic mapping: each key from PC is mapped to a key in the Spectrum + MAPANY(PC_1,SP_1,0,0); + MAPANY(PC_2,SP_2,0,0); + MAPANY(PC_3,SP_3,0,0); + MAPANY(PC_4,SP_4,0,0); + MAPANY(PC_5,SP_5,0,0); + MAPANY(PC_6,SP_6,0,0); + MAPANY(PC_7,SP_7,0,0); + MAPANY(PC_8,SP_8,0,0); + MAPANY(PC_9,SP_9,0,0); + MAPANY(PC_0,SP_0,0,0); + + MAPANY(PC_Q,SP_Q,0,0); + MAPANY(PC_W,SP_W,0,0); + MAPANY(PC_E,SP_E,0,0); + MAPANY(PC_R,SP_R,0,0); + MAPANY(PC_T,SP_T,0,0); + MAPANY(PC_Y,SP_Y,0,0); + MAPANY(PC_U,SP_U,0,0); + MAPANY(PC_I,SP_I,0,0); + MAPANY(PC_O,SP_O,0,0); + MAPANY(PC_P,SP_P,0,0); + MAPANY(PC_A,SP_A,0,0); + MAPANY(PC_S,SP_S,0,0); + MAPANY(PC_D,SP_D,0,0); + MAPANY(PC_F,SP_F,0,0); + MAPANY(PC_G,SP_G,0,0); + MAPANY(PC_H,SP_H,0,0); + MAPANY(PC_J,SP_J,0,0); + MAPANY(PC_K,SP_K,0,0); + MAPANY(PC_L,SP_L,0,0); + MAPANY(PC_Z,SP_Z,0,0); + MAPANY(PC_X,SP_X,0,0); + MAPANY(PC_C,SP_C,0,0); + MAPANY(PC_V,SP_V,0,0); + MAPANY(PC_B,SP_B,0,0); + MAPANY(PC_N,SP_N,0,0); + MAPANY(PC_M,SP_M,0,0); + + MAPANY(PC_SPACE,SP_SPACE,0,0); + MAPANY(PC_ENTER,SP_ENTER,0,0); + MAPANY(PC_ESC,SP_BREAK,0,0); + MAPANY(PC_CPSLOCK,SP_CPSLOCK,0,0); + MAPANY(PC_TAB,SP_EXTEND,0,0); + MAP(PC_BKSPACE,SP_DELETE,0,0); + MAPANY(PC_UP,SP_UP,0,0); + MAPANY(PC_DOWN,SP_DOWN,0,0); + MAPANY(PC_LEFT,SP_LEFT,0,0); + MAPANY(PC_RIGHT,SP_RIGHT,0,0); + MAPANY(PC_F2,SP_EDIT,0,0); + MAPANY(PC_F3,SP_TRUE,0,0); + MAPANY(PC_F4,SP_INVERSE,0,0); + MAP(PC_F5|MD2|MD3,0,NMI,0); // Ctrl-Alt-F5 for NMI + MAPANY(PC_F10,SP_GRAPH,0,0); // F10 habilita el modo gráfico. Esto es para Antonio, para la BIOS + MAP(PC_DELETE|MD2|MD3,0,URESET,0); // + MAP(PC_KP_DOT|MD2|MD3,0,URESET,0); // Ctrl-Alt-Del for user reset + MAP(PC_BKSPACE|MD2|MD3,0,MRESET,0); // Ctrl-Alt-BkSpace for master reset + + //keypad + MAPANY(PC_KP_1,SP_1,0,0); + MAPANY(PC_KP_2,SP_2,0,0); + MAPANY(PC_KP_3,SP_3,0,0); + MAPANY(PC_KP_4,SP_4,0,0); + MAPANY(PC_KP_5,SP_5,0,0); + MAPANY(PC_KP_6,SP_6,0,0); + MAPANY(PC_KP_7,SP_7,0,0); + MAPANY(PC_KP_8,SP_8,0,0); + MAPANY(PC_KP_9,SP_9,0,0); + MAPANY(PC_KP_0,SP_0,0,0); + MAPANY(PC_KP_DIVIS,SP_SLASH,0,0); + MAPANY(PC_KP_MULT,SP_STAR,0,0); + MAPANY(PC_KP_MINUS,SP_MINUS,0,0); + MAPANY(PC_KP_PLUS,SP_PLUS,0,0); + MAPANY(PC_KP_ENTER,SP_ENTER,0,0); + MAPANY(PC_KP_DOT,SP_DOT,0,0); + + MAPANY(PC_BACKSLA,SP_COLON,0,0); + MAPANY(PC_APOSTRO,SP_DOLLAR,0,0); + MAPANY(PC_OPNBANG,SP_EQUAL,0,0); + MAPANY(PC_GRAVEAC,SP_PAROPEN,0,0); + MAPANY(PC_PLUS,SP_PARCLOS,0,0); + MAPANY(PC_EGNE,SP_SEMICOL,0,0); + MAPANY(PC_ACUTEAC,SP_QUOTE,0,0); + MAPANY(PC_COMMA,SP_COMMA,0,0); + MAPANY(PC_DOT,SP_DOT,0,0); + MAPANY(PC_MINUS,SP_SLASH,0,0); + + MAPANY(PC_HOME,0,JOYUP,0); + MAPANY(PC_END,0,JOYDOWN,0); + MAPANY(PC_DELETE,0,JOYLEFT,0); + MAPANY(PC_PGDOWN,0,JOYRIGHT,0); + +// MAP(PC_F12,0,0,USER1); // Evento de usuario 1 + + // End of mapping. Save .HEX file for Verilog + SAVEMAPHEX("keyb_av_hex.txt"); + // And map file for loading from ESXDOS + SAVEMAPBIN("keymaps\\AV"); +} diff --git a/cores/Spectrum/genkeybmap_es.c b/cores/Spectrum/genkeybmap_es.c index edcf822..3e9daf2 100644 --- a/cores/Spectrum/genkeybmap_es.c +++ b/cores/Spectrum/genkeybmap_es.c @@ -333,7 +333,8 @@ int main() MAPANY(PC_RALT,0,JOYFIRE,MODIFIER3); // MD3 is ALT. Also is FIRE for keyboard joystick MAPANY(PC_LWIN,SP_CAPS,0,0); // CAPS SHIFT - MAPANY(PC_RWIN,SP_SYMBOL,0,0); // SYMBOL SHIFT + MAPANY(PC_RWIN,SP_SYMBOL,0,0); // SYMBOL SHIFT + MAPANY(PC_APPS,SP_SYMBOL,0,0); // SYMBOL SHIFT // Basic mapping: each key from PC is mapped to a key in the Spectrum MAP(PC_1,SP_1,0,0); @@ -482,6 +483,7 @@ int main() MAP(MD3|MD2|MD1|PC_LESS,SP_NOTEQ,0,0); MAP(PC_F12,0,0,USER1); // Evento de usuario 1 + MAP(PC_F2|MD2,0,0,USER2); // Evento de usuario 2 = Core 2 (Ctrl+F2) // End of mapping. Save .HEX file for Verilog SAVEMAPHEX("keyb_es_hex.txt"); diff --git a/cores/Spectrum/genkeybmap_us.c b/cores/Spectrum/genkeybmap_us.c index b6a1208..1655c70 100644 --- a/cores/Spectrum/genkeybmap_us.c +++ b/cores/Spectrum/genkeybmap_us.c @@ -472,6 +472,9 @@ int main() MAP(PC_SLASH,SP_SLASH,0,0); MAP(MD1|PC_SLASH,SP_QUEST,0,0); + MAP(PC_F12,0,0,USER1); // Evento de usuario 1 + MAP(PC_F2|MD2,0,0,USER2); // Evento de usuario 2 = Core 2 (Ctrl+F2) + // End of mapping. Save .HEX file for Verilog //SAVEMAPHEX("keyb_us_hex.txt"); // And map file for loading from ESXDOS diff --git a/cores/Spectrum/keyb_av_hex.txt b/cores/Spectrum/keyb_av_hex.txt new file mode 100644 index 0000000..8fb89cd --- /dev/null +++ b/cores/Spectrum/keyb_av_hex.txt @@ -0,0 +1,16384 @@ +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +01 +64 +00 +00 +00 +00 +00 +00 +01 +61 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +01 +82 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +01 +68 +00 +00 +01 +E2 +00 +00 +E2 +02 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +01 +80 +00 +01 +00 +00 +00 +00 +00 +00 +00 +E2 +00 +40 +00 +41 +00 +00 +00 +61 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +02 +00 +00 +00 +22 +00 +00 +00 +21 +00 +00 +00 +42 +00 +00 +00 +62 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +08 +00 +00 +00 +04 +00 +00 +00 +24 +00 +00 +00 +44 +00 +00 +00 +68 +00 +00 +00 +64 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +E1 +00 +00 +00 +10 +00 +00 +00 +28 +00 +00 +00 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+00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 diff --git a/cores/Spectrum/keyb_es_hex.txt b/cores/Spectrum/keyb_es_hex.txt index d8c1f95..5062666 100644 --- a/cores/Spectrum/keyb_es_hex.txt +++ b/cores/Spectrum/keyb_es_hex.txt @@ -1211,7 +1211,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -3259,7 +3259,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -4118,11 +4118,11 @@ C1 00 00 00 -01 -61 00 00 00 +02 +00 00 00 00 @@ -5307,7 +5307,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -7355,7 +7355,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -9403,7 +9403,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -11451,7 +11451,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -13499,7 +13499,7 @@ E2 00 00 00 -00 +E2 00 00 00 @@ -15547,7 +15547,7 @@ E2 00 00 00 -00 +E2 00 00 00 diff --git a/cores/Spectrum/keymaps/AV b/cores/Spectrum/keymaps/AV new file mode 100644 index 0000000000000000000000000000000000000000..e29c6feb7fd5698f95873c465fabeec3b4cb12b5 GIT binary patch literal 16384 zcmeI2F;2rU6ozfop<|B#h=GwK0AgU|3aL7D>=D|EfsreK7#O)iQHPFPp%w#UkHF_N zQQS)Kgeuhy`k(a2&-Qcj@;^KO66ZF}57vEOG~<4n_(SJ>a4sA*V~mWQulm7Vx-0x- zeK`~3Pr(Ve27ORl7pDWxzzyITuF3NfVc%%;r}6z<}UKYz)uWt{%ecp{~ua;{&#t= z*)EH_6Yh^@gi@rn6L|;3fb`!ihVi7^D`h4 delta 86 ycmZo@U~Fh$+_0BrvH(~1W)0S<>=1@%EX(FrK?`Om4<;;&!O(??n8FyWH<$p6Fd9Pu diff --git a/cores/Spectrum/keymaps/US b/cores/Spectrum/keymaps/US index 586ca778165aa3ae3ae63ea1940309818950f42c..8f309cc5e2bb7e2026bb41c9363a208a8321483f 100644 GIT binary patch delta 28 jcmZo@U~Fh$oFLCAuu= begin_hcint && vc == begin_vcint) && (hc <= end_hcint && vc == end_vcint)) + vretrace_int_n = 1'b0; + + raster_int_n = 1'b1; + if (rasterint_enable == 1'b1 && hc >= 256 && hc <= 319) begin + if (raster_line == 9'd0 && vc == end_count_v) + raster_int_n = 1'b0; + if (raster_line != 9'd0 && vc == (raster_line - 9'd1)) + raster_int_n = 1'b0; + end + end + + always @* begin + ro = ri; + go = gi; + bo = bi; + hsync = 1'b1; + vsync = 1'b1; + if ( (hc >= begin_hblank && hc <= end_hblank) || (vc >= begin_vblank && vc <= end_vblank) ) begin + ro = 3'b000; + go = 3'b000; + bo = 3'b000; + if (hc >= begin_hsync && hc <= end_hsync) + hsync = 1'b0; + if (vc >= begin_vsync && vc <= end_vsync) + vsync = 1'b0; + end + end +endmodule diff --git a/cores/Spectrum/par_usage_statistics.html b/cores/Spectrum/par_usage_statistics.html index 35d8594..312db8c 100644 --- a/cores/Spectrum/par_usage_statistics.html +++ b/cores/Spectrum/par_usage_statistics.html @@ -1,31 +1,32 @@ - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - + +
Par Statistics
Total Non-vccgnd Signals=3241
Total Non-vccgnd Design Pins=13509
Total Non-vccgnd Conns=13509
Total Non-vccgnd Timing Constrained Conns=12464
Phase 1 CPU=7.9 sec
Phase 2 CPU=9.0 sec
Phase 3 CPU=17.3 sec
Phase 4 CPU=19.5 sec
Phase 5 CPU=49.3 sec
Phase 6 CPU=64.7 sec
Phase 7 CPU=64.7 sec
Phase 8 CPU=64.7 sec
Phase 9 CPU=65.7 sec
Phase 10 CPU=67.0 sec
AvgWirelenPerPin Fanout 1=3.0
AvgWirelenPerPin Fanout 2=3.0
AvgWirelenPerPin Fanout 3=5.0
AvgWirelenPerPin Fanout 4=5.5
AvgWirelenPerPin Fanout 10=4.6
AvgWirelenPerPin Fanout 50=3.3
AvgWirelenPerPin Fanout 100=5.4
Total Non-vccgnd Signals=4226
Total Non-vccgnd Design Pins=16414
Total Non-vccgnd Conns=16414
Total Non-vccgnd Timing Constrained Conns=15400
Phase 1 CPU=17.3 sec
Phase 2 CPU=20.2 sec
Phase 3 CPU=43.7 sec
Phase 4 CPU=45.4 sec
Phase 5 CPU=69.8 sec
Phase 6 CPU=69.8 sec
Phase 7 CPU=69.8 sec
Phase 8 CPU=69.8 sec
Phase 9 CPU=70.8 sec
Phase 10 CPU=73.1 sec
AvgWirelenPerPin Fanout 1=2.0
AvgWirelenPerPin Fanout 2=2.5
AvgWirelenPerPin Fanout 3=3.0
AvgWirelenPerPin Fanout 4=3.3
AvgWirelenPerPin Fanout 10=3.2
AvgWirelenPerPin Fanout 50=2.9
AvgWirelenPerPin Fanout 100=8.8
AvgWirelenPerPin Fanout 500=3.3
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
IRR Gamma=10.5109
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=8.5515
diff --git a/cores/Spectrum/pines_zxuno.ucf b/cores/Spectrum/pines_zxuno.ucf index 8e5da71..10ecc30 100644 --- a/cores/Spectrum/pines_zxuno.ucf +++ b/cores/Spectrum/pines_zxuno.ucf @@ -1,84 +1,85 @@ # Clocks & debug NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33; -NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33; +NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33; NET "clk50mhz" PERIOD=20 ns; NET "sysclk" PERIOD=35 ns; # Video output -NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33; -NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33; -NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33; +NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33; +NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33; +NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33; NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33; NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33; NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33; -NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33; -NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33; -NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33; -NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33; -#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33; -NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33; -NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33; +NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33; +NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33; +NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33; +NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33; #87 +NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33; +NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33; +NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33; # Sound input/output -NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33; +NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33; NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33; -NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33; +NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33; # Keyboard and mouse -NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN -NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN -NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN -NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN +NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN +NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN +NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN +NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN # SRAM -NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33; -NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33; -NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33; -NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33; -NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33; -NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33; -NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33; -NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33; -NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33; -NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33; -NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33; -NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33; -NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33; -NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33; -NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33; -NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33; -NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33; -NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33; -NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33; +NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33; +NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33; +NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33; +NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33; +NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33; +NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33; +NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33; +NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33; +NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33; +NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33; +NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33; +NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33; +NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33; +NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33; +NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33; +NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33; +NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33; +NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33; +NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33; +#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33; +#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33; -NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33; -NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33; -NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33; -NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33; -NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33; -NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33; -NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33; -NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33; +NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33; +NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33; +NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33; +NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33; +NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33; +NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33; +NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33; +NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33; -NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33; +NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33; # SPI Flash NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33; -NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33; +NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33; NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33; NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33; -#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33; -#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33; # SD/MMC NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33; -NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33; +NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33; NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33; NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33; # JOYSTICK -NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6 -NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4 -NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3 -NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2 -NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7 +NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6 +NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4 +NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3 +NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2 +NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7 +#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5 diff --git a/cores/Spectrum/pines_zxuno_Ap.ucf b/cores/Spectrum/pines_zxuno_Ap.ucf new file mode 100644 index 0000000..7f7fd8f --- /dev/null +++ b/cores/Spectrum/pines_zxuno_Ap.ucf @@ -0,0 +1,84 @@ +# Clocks & debug +NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33; +NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33; +NET "clk50mhz" PERIOD=20 ns; +NET "sysclk" PERIOD=35 ns; + +# Video output +NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33; +NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33; +NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33; +NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33; +NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33; +NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33; +NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33; +NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33; +NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33; +NET "hsync" LOC="P93" | IOSTANDARD = LVCMOS33; +NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33; +NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33; +NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33; + +# Sound input/output +NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33; +NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33; +NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33; + +# Keyboard and mouse +NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN +NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN +NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN +NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN + +# SRAM +NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33; +NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33; +NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33; +NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33; +NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33; +NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33; +NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33; +NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33; +NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33; +NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33; +NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33; +NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33; +NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33; +NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33; +NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33; +NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33; +NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33; +NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33; +NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33; + +NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33; +NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33; +NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33; +NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33; +NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33; +NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33; +NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33; +NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33; + +NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33; + +# SPI Flash +NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33; +NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33; +NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33; +NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33; +#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33; +#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33; + +# SD/MMC +NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33; +NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33; +NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33; +NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33; + +# JOYSTICK +NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6 +NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4 +NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3 +NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2 +NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7 diff --git a/cores/Spectrum/pines_zxuno_v3.ucf b/cores/Spectrum/pines_zxuno_v3.ucf new file mode 100644 index 0000000..5879eec --- /dev/null +++ b/cores/Spectrum/pines_zxuno_v3.ucf @@ -0,0 +1,88 @@ +# Clocks & debug +NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33; +NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33; +NET "clk50mhz" PERIOD=20 ns; +NET "sysclk" PERIOD=35 ns; + +# Video output +NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33; +NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33; +NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33; +NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33; +NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33; +NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33; +NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33; +NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33; +NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33; +NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33; +NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33; +NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33; +NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33; + +# Sound input/output +NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33; +NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33; +NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33; + +# Keyboard and mouse +NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN +NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN +NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN +NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN + +# SRAM +NET "sram_addr<0>" LOC="P143" | IOSTANDARD = LVCMOS33; +NET "sram_addr<1>" LOC="P142" | IOSTANDARD = LVCMOS33; +NET "sram_addr<2>" LOC="P141" | IOSTANDARD = LVCMOS33; +NET "sram_addr<3>" LOC="P140" | IOSTANDARD = LVCMOS33; +NET "sram_addr<4>" LOC="P139" | IOSTANDARD = LVCMOS33; +NET "sram_addr<5>" LOC="P104" | IOSTANDARD = LVCMOS33; +NET "sram_addr<6>" LOC="P102" | IOSTANDARD = LVCMOS33; +NET "sram_addr<7>" LOC="P101" | IOSTANDARD = LVCMOS33; +NET "sram_addr<8>" LOC="P100" | IOSTANDARD = LVCMOS33; +NET "sram_addr<9>" LOC="P99" | IOSTANDARD = LVCMOS33; +NET "sram_addr<10>" LOC="P112" | IOSTANDARD = LVCMOS33; +NET "sram_addr<11>" LOC="P114" | IOSTANDARD = LVCMOS33; +NET "sram_addr<12>" LOC="P115" | IOSTANDARD = LVCMOS33; +NET "sram_addr<13>" LOC="P116" | IOSTANDARD = LVCMOS33; +NET "sram_addr<14>" LOC="P117" | IOSTANDARD = LVCMOS33; +NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33; +NET "sram_addr<16>" LOC="P133" | IOSTANDARD = LVCMOS33; +NET "sram_addr<17>" LOC="P134" | IOSTANDARD = LVCMOS33; +NET "sram_addr<18>" LOC="P137" | IOSTANDARD = LVCMOS33; +#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33; +#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33; + +NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33; +NET "sram_data<1>" LOC="P126" | IOSTANDARD = LVCMOS33; +NET "sram_data<2>" LOC="P123" | IOSTANDARD = LVCMOS33; +NET "sram_data<3>" LOC="P120" | IOSTANDARD = LVCMOS33; +NET "sram_data<4>" LOC="P119" | IOSTANDARD = LVCMOS33; +NET "sram_data<5>" LOC="P121" | IOSTANDARD = LVCMOS33; +NET "sram_data<6>" LOC="P124" | IOSTANDARD = LVCMOS33; +NET "sram_data<7>" LOC="P127" | IOSTANDARD = LVCMOS33; + +NET "sram_we_n" LOC="P118" | IOSTANDARD = LVCMOS33; + +# SPI Flash +NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33; +NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33; +NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33; +NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33; +#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33; +#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33; + +# SD/MMC +NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33; +NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33; +NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33; +NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33; + +# JOYSTICK +NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6 +NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4 +NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3 +NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2 +NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7 +#NET "btn2" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5 + diff --git a/cores/Spectrum/pines_zxuno_v4.ucf b/cores/Spectrum/pines_zxuno_v4.ucf new file mode 100644 index 0000000..10ecc30 --- /dev/null +++ b/cores/Spectrum/pines_zxuno_v4.ucf @@ -0,0 +1,85 @@ +# Clocks & debug +NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33; +NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33; +NET "clk50mhz" PERIOD=20 ns; +NET "sysclk" PERIOD=35 ns; + +# Video output +NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33; +NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33; +NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33; +NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33; +NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33; +NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33; +NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33; +NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33; +NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33; +NET "hsync" LOC="P87" | IOSTANDARD = LVCMOS33; #87 +NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33; +NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33; +NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33; + +# Sound input/output +NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33; +NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33; +NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33; + +# Keyboard and mouse +NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN +NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN +NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN +NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN + +# SRAM +NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33; +NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33; +NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33; +NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33; +NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33; +NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33; +NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33; +NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33; +NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33; +NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33; +NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33; +NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33; +NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33; +NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33; +NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33; +NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33; +NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33; +NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33; +NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33; +#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33; +#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33; + +NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33; +NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33; +NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33; +NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33; +NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33; +NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33; +NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33; +NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33; + +NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33; + +# SPI Flash +NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33; +NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33; +NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33; +NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33; + +# SD/MMC +NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33; +NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33; +NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33; +NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33; + +# JOYSTICK +NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6 +NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4 +NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3 +NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2 +NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7 +#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5 diff --git a/cores/Spectrum/pll_drp.v b/cores/Spectrum/pll_drp.v new file mode 100644 index 0000000..41be9f7 --- /dev/null +++ b/cores/Spectrum/pll_drp.v @@ -0,0 +1,1729 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Karl Kurbjun and Carl Ribbing +// Date: 12/10/2009 +// Design Name: PLL DRP +// Module Name: pll_drp.v +// Version: 1.1 +// Target Devices: Spartan 6 Family +// Tool versions: L.68 (lin) +// Description: This calls the DRP register calculation functions and +// provides a state machine to perform PLL reconfiguration +// based on the calulated values stored in a initialized ROM. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2008 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps + +// Change parameters using http://goo.gl/Os0cKi + +module pll_drp + #( + //*********************************************************************** + // State 1 Parameters - These are for the first reconfiguration state. + // 50 Hz, Salida RGB/VGA + //*********************************************************************** + + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S1_CLKFBOUT_MULT = 9, + parameter S1_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S1_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S1_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S1_CLKOUT0_DIVIDE = 16, + parameter S1_CLKOUT0_PHASE = 0, + parameter S1_CLKOUT0_DUTY = 50000, + + parameter S1_CLKOUT1_DIVIDE = 32, + parameter S1_CLKOUT1_PHASE = 0, + parameter S1_CLKOUT1_DUTY = 50000, + + parameter S1_CLKOUT2_DIVIDE = 64, + parameter S1_CLKOUT2_PHASE = 0, + parameter S1_CLKOUT2_DUTY = 50000, + + parameter S1_CLKOUT3_DIVIDE = 128, + parameter S1_CLKOUT3_PHASE = 0, + parameter S1_CLKOUT3_DUTY = 50000, + + parameter S1_CLKOUT4_DIVIDE = 128, + parameter S1_CLKOUT4_PHASE = 0, + parameter S1_CLKOUT4_DUTY = 50000, + + parameter S1_CLKOUT5_DIVIDE = 128, + parameter S1_CLKOUT5_PHASE = 0, + parameter S1_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 2 Parameters - These are for the second reconfiguration state. + // 51 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S2_CLKFBOUT_MULT = 8, + parameter S2_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S2_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S2_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S2_CLKOUT0_DIVIDE = 14, + parameter S2_CLKOUT0_PHASE = 0, + parameter S2_CLKOUT0_DUTY = 50000, + + parameter S2_CLKOUT1_DIVIDE = 28, + parameter S2_CLKOUT1_PHASE = 0, + parameter S2_CLKOUT1_DUTY = 50000, + + parameter S2_CLKOUT2_DIVIDE = 56, + parameter S2_CLKOUT2_PHASE = 0, + parameter S2_CLKOUT2_DUTY = 50000, + + parameter S2_CLKOUT3_DIVIDE = 112, + parameter S2_CLKOUT3_PHASE = 0, + parameter S2_CLKOUT3_DUTY = 50000, + + parameter S2_CLKOUT4_DIVIDE = 112, + parameter S2_CLKOUT4_PHASE = 0, + parameter S2_CLKOUT4_DUTY = 50000, + + parameter S2_CLKOUT5_DIVIDE = 112, + parameter S2_CLKOUT5_PHASE = 0, + parameter S2_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 3 Parameters - These are for the second reconfiguration state. + // 53.50 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S3_CLKFBOUT_MULT = 9, + parameter S3_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S3_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S3_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S3_CLKOUT0_DIVIDE = 15, + parameter S3_CLKOUT0_PHASE = 0, + parameter S3_CLKOUT0_DUTY = 50000, + + parameter S3_CLKOUT1_DIVIDE = 30, + parameter S3_CLKOUT1_PHASE = 0, + parameter S3_CLKOUT1_DUTY = 50000, + + parameter S3_CLKOUT2_DIVIDE = 60, + parameter S3_CLKOUT2_PHASE = 0, + parameter S3_CLKOUT2_DUTY = 50000, + + parameter S3_CLKOUT3_DIVIDE = 120, + parameter S3_CLKOUT3_PHASE = 0, + parameter S3_CLKOUT3_DUTY = 50000, + + parameter S3_CLKOUT4_DIVIDE = 120, + parameter S3_CLKOUT4_PHASE = 0, + parameter S3_CLKOUT4_DUTY = 50000, + + parameter S3_CLKOUT5_DIVIDE = 120, + parameter S3_CLKOUT5_PHASE = 0, + parameter S3_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 4 Parameters - These are for the second reconfiguration state. + // 55.80 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S4_CLKFBOUT_MULT = 10, + parameter S4_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S4_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S4_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S4_CLKOUT0_DIVIDE = 16, + parameter S4_CLKOUT0_PHASE = 0, + parameter S4_CLKOUT0_DUTY = 50000, + + parameter S4_CLKOUT1_DIVIDE = 32, + parameter S4_CLKOUT1_PHASE = 0, + parameter S4_CLKOUT1_DUTY = 50000, + + parameter S4_CLKOUT2_DIVIDE = 64, + parameter S4_CLKOUT2_PHASE = 0, + parameter S4_CLKOUT2_DUTY = 50000, + + parameter S4_CLKOUT3_DIVIDE = 128, + parameter S4_CLKOUT3_PHASE = 0, + parameter S4_CLKOUT3_DUTY = 50000, + + parameter S4_CLKOUT4_DIVIDE = 128, + parameter S4_CLKOUT4_PHASE = 0, + parameter S4_CLKOUT4_DUTY = 50000, + + parameter S4_CLKOUT5_DIVIDE = 128, + parameter S4_CLKOUT5_PHASE = 0, + parameter S4_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 5 Parameters - These are for the second reconfiguration state. + // 57.39 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S5_CLKFBOUT_MULT = 9, + parameter S5_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S5_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S5_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S5_CLKOUT0_DIVIDE = 14, + parameter S5_CLKOUT0_PHASE = 0, + parameter S5_CLKOUT0_DUTY = 50000, + + parameter S5_CLKOUT1_DIVIDE = 28, + parameter S5_CLKOUT1_PHASE = 0, + parameter S5_CLKOUT1_DUTY = 50000, + + parameter S5_CLKOUT2_DIVIDE = 56, + parameter S5_CLKOUT2_PHASE = 0, + parameter S5_CLKOUT2_DUTY = 50000, + + parameter S5_CLKOUT3_DIVIDE = 112, + parameter S5_CLKOUT3_PHASE = 0, + parameter S5_CLKOUT3_DUTY = 50000, + + parameter S5_CLKOUT4_DIVIDE = 112, + parameter S5_CLKOUT4_PHASE = 0, + parameter S5_CLKOUT4_DUTY = 50000, + + parameter S5_CLKOUT5_DIVIDE = 112, + parameter S5_CLKOUT5_PHASE = 0, + parameter S5_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 6 Parameters - These are for the second reconfiguration state. + // 59.52 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S6_CLKFBOUT_MULT = 8, + parameter S6_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S6_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S6_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S6_CLKOUT0_DIVIDE = 12, + parameter S6_CLKOUT0_PHASE = 0, + parameter S6_CLKOUT0_DUTY = 50000, + + parameter S6_CLKOUT1_DIVIDE = 24, + parameter S6_CLKOUT1_PHASE = 0, + parameter S6_CLKOUT1_DUTY = 50000, + + parameter S6_CLKOUT2_DIVIDE = 48, + parameter S6_CLKOUT2_PHASE = 0, + parameter S6_CLKOUT2_DUTY = 50000, + + parameter S6_CLKOUT3_DIVIDE = 96, + parameter S6_CLKOUT3_PHASE = 0, + parameter S6_CLKOUT3_DUTY = 50000, + + parameter S6_CLKOUT4_DIVIDE = 96, + parameter S6_CLKOUT4_PHASE = 0, + parameter S6_CLKOUT4_DUTY = 50000, + + parameter S6_CLKOUT5_DIVIDE = 96, + parameter S6_CLKOUT5_PHASE = 0, + parameter S6_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 7 Parameters - These are for the second reconfiguration state. + // 61.8 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S7_CLKFBOUT_MULT = 9, + parameter S7_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S7_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S7_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S7_CLKOUT0_DIVIDE = 13, + parameter S7_CLKOUT0_PHASE = 0, + parameter S7_CLKOUT0_DUTY = 50000, + + parameter S7_CLKOUT1_DIVIDE = 26, + parameter S7_CLKOUT1_PHASE = 0, + parameter S7_CLKOUT1_DUTY = 50000, + + parameter S7_CLKOUT2_DIVIDE = 52, + parameter S7_CLKOUT2_PHASE = 0, + parameter S7_CLKOUT2_DUTY = 50000, + + parameter S7_CLKOUT3_DIVIDE = 104, + parameter S7_CLKOUT3_PHASE = 0, + parameter S7_CLKOUT3_DUTY = 50000, + + parameter S7_CLKOUT4_DIVIDE = 104, + parameter S7_CLKOUT4_PHASE = 0, + parameter S7_CLKOUT4_DUTY = 50000, + + parameter S7_CLKOUT5_DIVIDE = 104, + parameter S7_CLKOUT5_PHASE = 0, + parameter S7_CLKOUT5_DUTY = 50000, + + //*********************************************************************** + // State 8 Parameters - These are for the second reconfiguration state. + // 63.77 Hz, Salida VGA + //*********************************************************************** + // These parameters have an effect on the feedback path. A change on + // these parameters will effect all of the clock outputs. + // + // The paramaters are composed of: + // _MULT: This can be from 1 to 64. It has an effect on the VCO + // frequency which consequently, effects all of the clock + // outputs. + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000. + parameter S8_CLKFBOUT_MULT = 10, + parameter S8_CLKFBOUT_PHASE = 0, + + // The bandwidth parameter effects the phase error and the jitter filter + // capability of the MMCM. For more information on this parameter see the + // Device user guide. + parameter S8_BANDWIDTH = "LOW", + // The divclk parameter allows th einput clock to be divided before it + // reaches the phase and frequency comparitor. This can be set between + // 1 and 128. + parameter S8_DIVCLK_DIVIDE = 1, + + // The following parameters describe the configuration that each clock + // output should have once the reconfiguration for state one has + // completed. + // + // The parameters are composed of: + // _DIVIDE: This can be from 1 to 128 + // _PHASE: This is the phase multiplied by 1000. For example if + // a phase of 24.567 deg was desired the input value would be + // 24567. The range for the phase is from -360000 to 360000 + // _DUTY: This is the duty cycle multiplied by 100,000. For example if + // a duty cycle of .24567 was desired the input would be + // 24567. + parameter S8_CLKOUT0_DIVIDE = 14, + parameter S8_CLKOUT0_PHASE = 0, + parameter S8_CLKOUT0_DUTY = 50000, + + parameter S8_CLKOUT1_DIVIDE = 28, + parameter S8_CLKOUT1_PHASE = 0, + parameter S8_CLKOUT1_DUTY = 50000, + + parameter S8_CLKOUT2_DIVIDE = 56, + parameter S8_CLKOUT2_PHASE = 0, + parameter S8_CLKOUT2_DUTY = 50000, + + parameter S8_CLKOUT3_DIVIDE = 112, + parameter S8_CLKOUT3_PHASE = 0, + parameter S8_CLKOUT3_DUTY = 50000, + + parameter S8_CLKOUT4_DIVIDE = 112, + parameter S8_CLKOUT4_PHASE = 0, + parameter S8_CLKOUT4_DUTY = 50000, + + parameter S8_CLKOUT5_DIVIDE = 112, + parameter S8_CLKOUT5_PHASE = 0, + parameter S8_CLKOUT5_DUTY = 50000 + + ) ( + // These signals are controlled by user logic interface and are covered + // in more detail within the XAPP. + input wire [2:0] SADDR, + input wire SEN, + input wire SCLK, + input wire RST, + output reg SRDY, + + // These signals are to be connected to the PLL_ADV by port name. + // Their use matches the PLL port description in the Device User Guide. + input wire [15:0] DO, + input wire DRDY, + input wire LOCKED, + output reg DWE, + output reg DEN, + output reg [4:0] DADDR, + output reg [15:0] DI, + output wire DCLK, + output reg RST_PLL + ); + + // 100 ps delay for behavioral simulations + localparam TCQ = 100; + + // Make sure the memory is implemented as distributed (does not work on 11.2) + //(* rom_style = "distributed" *) + reg [36:0] rom [0:183]; + reg [7:0] rom_addr; + reg [36:0] rom_do; + + reg next_srdy; + + reg [7:0] next_rom_addr; + reg [4:0] next_daddr; + reg next_dwe; + reg next_den; + reg next_rst_pll; + reg [15:0] next_di; + + // Integer used to initialize remainder of unused ROM + integer ii; + + // Pass SCLK to DCLK for the PLL + assign DCLK = SCLK; + // include the PLL reconfiguration functions. This contains the constant + // functions that are used in the calculations below. This file is + // required. + `include "pll_drp_func.h" + + //************************************************************************** + // State 1 Calculations + //************************************************************************** + localparam [22:0] S1_CLKFBOUT = + s6_pll_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S1_CLKFBOUT2 = + s6_pll_count_calc(S1_CLKFBOUT_MULT, S1_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S1_DIGITAL_FILT = + s6_pll_filter_lookup(S1_CLKFBOUT_MULT, S1_BANDWIDTH); + + localparam [39:0] S1_LOCK = + s6_pll_lock_lookup(S1_CLKFBOUT_MULT); + + localparam [22:0] S1_DIVCLK = + s6_pll_count_calc(S1_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S1_CLKOUT0 = + s6_pll_count_calc(S1_CLKOUT0_DIVIDE, S1_CLKOUT0_PHASE, S1_CLKOUT0_DUTY); + + localparam [22:0] S1_CLKOUT1 = + s6_pll_count_calc(S1_CLKOUT1_DIVIDE, S1_CLKOUT1_PHASE, S1_CLKOUT1_DUTY); + + localparam [22:0] S1_CLKOUT2 = + s6_pll_count_calc(S1_CLKOUT2_DIVIDE, S1_CLKOUT2_PHASE, S1_CLKOUT2_DUTY); + + localparam [22:0] S1_CLKOUT3 = + s6_pll_count_calc(S1_CLKOUT3_DIVIDE, S1_CLKOUT3_PHASE, S1_CLKOUT3_DUTY); + + localparam [22:0] S1_CLKOUT4 = + s6_pll_count_calc(S1_CLKOUT4_DIVIDE, S1_CLKOUT4_PHASE, S1_CLKOUT4_DUTY); + + localparam [22:0] S1_CLKOUT5 = + s6_pll_count_calc(S1_CLKOUT5_DIVIDE, S1_CLKOUT5_PHASE, S1_CLKOUT5_DUTY); + + //************************************************************************** + // State 2 Calculations + //************************************************************************** + localparam [22:0] S2_CLKFBOUT = + s6_pll_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S2_CLKFBOUT2 = + s6_pll_count_calc(S2_CLKFBOUT_MULT, S2_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S2_DIGITAL_FILT = + s6_pll_filter_lookup(S2_CLKFBOUT_MULT, S2_BANDWIDTH); + + localparam [39:0] S2_LOCK = + s6_pll_lock_lookup(S2_CLKFBOUT_MULT); + + localparam [22:0] S2_DIVCLK = + s6_pll_count_calc(S2_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S2_CLKOUT0 = + s6_pll_count_calc(S2_CLKOUT0_DIVIDE, S2_CLKOUT0_PHASE, S2_CLKOUT0_DUTY); + + localparam [22:0] S2_CLKOUT1 = + s6_pll_count_calc(S2_CLKOUT1_DIVIDE, S2_CLKOUT1_PHASE, S2_CLKOUT1_DUTY); + + localparam [22:0] S2_CLKOUT2 = + s6_pll_count_calc(S2_CLKOUT2_DIVIDE, S2_CLKOUT2_PHASE, S2_CLKOUT2_DUTY); + + localparam [22:0] S2_CLKOUT3 = + s6_pll_count_calc(S2_CLKOUT3_DIVIDE, S2_CLKOUT3_PHASE, S2_CLKOUT3_DUTY); + + localparam [22:0] S2_CLKOUT4 = + s6_pll_count_calc(S2_CLKOUT4_DIVIDE, S2_CLKOUT4_PHASE, S2_CLKOUT4_DUTY); + + localparam [22:0] S2_CLKOUT5 = + s6_pll_count_calc(S2_CLKOUT5_DIVIDE, S2_CLKOUT5_PHASE, S2_CLKOUT5_DUTY); + + //************************************************************************** + // State 3 Calculations + //************************************************************************** + localparam [22:0] S3_CLKFBOUT = + s6_pll_count_calc(S3_CLKFBOUT_MULT, S3_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S3_CLKFBOUT2 = + s6_pll_count_calc(S3_CLKFBOUT_MULT, S3_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S3_DIGITAL_FILT = + s6_pll_filter_lookup(S3_CLKFBOUT_MULT, S3_BANDWIDTH); + + localparam [39:0] S3_LOCK = + s6_pll_lock_lookup(S3_CLKFBOUT_MULT); + + localparam [22:0] S3_DIVCLK = + s6_pll_count_calc(S3_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S3_CLKOUT0 = + s6_pll_count_calc(S3_CLKOUT0_DIVIDE, S3_CLKOUT0_PHASE, S3_CLKOUT0_DUTY); + + localparam [22:0] S3_CLKOUT1 = + s6_pll_count_calc(S3_CLKOUT1_DIVIDE, S3_CLKOUT1_PHASE, S3_CLKOUT1_DUTY); + + localparam [22:0] S3_CLKOUT2 = + s6_pll_count_calc(S3_CLKOUT2_DIVIDE, S3_CLKOUT2_PHASE, S3_CLKOUT2_DUTY); + + localparam [22:0] S3_CLKOUT3 = + s6_pll_count_calc(S3_CLKOUT3_DIVIDE, S3_CLKOUT3_PHASE, S3_CLKOUT3_DUTY); + + localparam [22:0] S3_CLKOUT4 = + s6_pll_count_calc(S3_CLKOUT4_DIVIDE, S3_CLKOUT4_PHASE, S3_CLKOUT4_DUTY); + + localparam [22:0] S3_CLKOUT5 = + s6_pll_count_calc(S3_CLKOUT5_DIVIDE, S3_CLKOUT5_PHASE, S3_CLKOUT5_DUTY); + + //************************************************************************** + // State 4 Calculations + //************************************************************************** + localparam [22:0] S4_CLKFBOUT = + s6_pll_count_calc(S4_CLKFBOUT_MULT, S4_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S4_CLKFBOUT2 = + s6_pll_count_calc(S4_CLKFBOUT_MULT, S4_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S4_DIGITAL_FILT = + s6_pll_filter_lookup(S4_CLKFBOUT_MULT, S4_BANDWIDTH); + + localparam [39:0] S4_LOCK = + s6_pll_lock_lookup(S4_CLKFBOUT_MULT); + + localparam [22:0] S4_DIVCLK = + s6_pll_count_calc(S4_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S4_CLKOUT0 = + s6_pll_count_calc(S4_CLKOUT0_DIVIDE, S4_CLKOUT0_PHASE, S4_CLKOUT0_DUTY); + + localparam [22:0] S4_CLKOUT1 = + s6_pll_count_calc(S4_CLKOUT1_DIVIDE, S4_CLKOUT1_PHASE, S4_CLKOUT1_DUTY); + + localparam [22:0] S4_CLKOUT2 = + s6_pll_count_calc(S4_CLKOUT2_DIVIDE, S4_CLKOUT2_PHASE, S4_CLKOUT2_DUTY); + + localparam [22:0] S4_CLKOUT3 = + s6_pll_count_calc(S4_CLKOUT3_DIVIDE, S4_CLKOUT3_PHASE, S4_CLKOUT3_DUTY); + + localparam [22:0] S4_CLKOUT4 = + s6_pll_count_calc(S4_CLKOUT4_DIVIDE, S4_CLKOUT4_PHASE, S4_CLKOUT4_DUTY); + + localparam [22:0] S4_CLKOUT5 = + s6_pll_count_calc(S4_CLKOUT5_DIVIDE, S4_CLKOUT5_PHASE, S4_CLKOUT5_DUTY); + + //************************************************************************** + // State 5 Calculations + //************************************************************************** + localparam [22:0] S5_CLKFBOUT = + s6_pll_count_calc(S5_CLKFBOUT_MULT, S5_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S5_CLKFBOUT2 = + s6_pll_count_calc(S5_CLKFBOUT_MULT, S5_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S5_DIGITAL_FILT = + s6_pll_filter_lookup(S5_CLKFBOUT_MULT, S5_BANDWIDTH); + + localparam [39:0] S5_LOCK = + s6_pll_lock_lookup(S5_CLKFBOUT_MULT); + + localparam [22:0] S5_DIVCLK = + s6_pll_count_calc(S5_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S5_CLKOUT0 = + s6_pll_count_calc(S5_CLKOUT0_DIVIDE, S5_CLKOUT0_PHASE, S5_CLKOUT0_DUTY); + + localparam [22:0] S5_CLKOUT1 = + s6_pll_count_calc(S5_CLKOUT1_DIVIDE, S5_CLKOUT1_PHASE, S5_CLKOUT1_DUTY); + + localparam [22:0] S5_CLKOUT2 = + s6_pll_count_calc(S5_CLKOUT2_DIVIDE, S5_CLKOUT2_PHASE, S5_CLKOUT2_DUTY); + + localparam [22:0] S5_CLKOUT3 = + s6_pll_count_calc(S5_CLKOUT3_DIVIDE, S5_CLKOUT3_PHASE, S5_CLKOUT3_DUTY); + + localparam [22:0] S5_CLKOUT4 = + s6_pll_count_calc(S5_CLKOUT4_DIVIDE, S5_CLKOUT4_PHASE, S5_CLKOUT4_DUTY); + + localparam [22:0] S5_CLKOUT5 = + s6_pll_count_calc(S5_CLKOUT5_DIVIDE, S5_CLKOUT5_PHASE, S5_CLKOUT5_DUTY); + + //************************************************************************** + // State 6 Calculations + //************************************************************************** + localparam [22:0] S6_CLKFBOUT = + s6_pll_count_calc(S6_CLKFBOUT_MULT, S6_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S6_CLKFBOUT2 = + s6_pll_count_calc(S6_CLKFBOUT_MULT, S6_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S6_DIGITAL_FILT = + s6_pll_filter_lookup(S6_CLKFBOUT_MULT, S6_BANDWIDTH); + + localparam [39:0] S6_LOCK = + s6_pll_lock_lookup(S6_CLKFBOUT_MULT); + + localparam [22:0] S6_DIVCLK = + s6_pll_count_calc(S6_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S6_CLKOUT0 = + s6_pll_count_calc(S6_CLKOUT0_DIVIDE, S6_CLKOUT0_PHASE, S6_CLKOUT0_DUTY); + + localparam [22:0] S6_CLKOUT1 = + s6_pll_count_calc(S6_CLKOUT1_DIVIDE, S6_CLKOUT1_PHASE, S6_CLKOUT1_DUTY); + + localparam [22:0] S6_CLKOUT2 = + s6_pll_count_calc(S6_CLKOUT2_DIVIDE, S6_CLKOUT2_PHASE, S6_CLKOUT2_DUTY); + + localparam [22:0] S6_CLKOUT3 = + s6_pll_count_calc(S6_CLKOUT3_DIVIDE, S6_CLKOUT3_PHASE, S6_CLKOUT3_DUTY); + + localparam [22:0] S6_CLKOUT4 = + s6_pll_count_calc(S6_CLKOUT4_DIVIDE, S6_CLKOUT4_PHASE, S6_CLKOUT4_DUTY); + + localparam [22:0] S6_CLKOUT5 = + s6_pll_count_calc(S6_CLKOUT5_DIVIDE, S6_CLKOUT5_PHASE, S6_CLKOUT5_DUTY); + + //************************************************************************** + // State 7 Calculations + //************************************************************************** + localparam [22:0] S7_CLKFBOUT = + s6_pll_count_calc(S7_CLKFBOUT_MULT, S7_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S7_CLKFBOUT2 = + s6_pll_count_calc(S7_CLKFBOUT_MULT, S7_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S7_DIGITAL_FILT = + s6_pll_filter_lookup(S7_CLKFBOUT_MULT, S7_BANDWIDTH); + + localparam [39:0] S7_LOCK = + s6_pll_lock_lookup(S7_CLKFBOUT_MULT); + + localparam [22:0] S7_DIVCLK = + s6_pll_count_calc(S7_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S7_CLKOUT0 = + s6_pll_count_calc(S7_CLKOUT0_DIVIDE, S7_CLKOUT0_PHASE, S7_CLKOUT0_DUTY); + + localparam [22:0] S7_CLKOUT1 = + s6_pll_count_calc(S7_CLKOUT1_DIVIDE, S7_CLKOUT1_PHASE, S7_CLKOUT1_DUTY); + + localparam [22:0] S7_CLKOUT2 = + s6_pll_count_calc(S7_CLKOUT2_DIVIDE, S7_CLKOUT2_PHASE, S7_CLKOUT2_DUTY); + + localparam [22:0] S7_CLKOUT3 = + s6_pll_count_calc(S7_CLKOUT3_DIVIDE, S7_CLKOUT3_PHASE, S7_CLKOUT3_DUTY); + + localparam [22:0] S7_CLKOUT4 = + s6_pll_count_calc(S7_CLKOUT4_DIVIDE, S7_CLKOUT4_PHASE, S7_CLKOUT4_DUTY); + + localparam [22:0] S7_CLKOUT5 = + s6_pll_count_calc(S7_CLKOUT5_DIVIDE, S7_CLKOUT5_PHASE, S7_CLKOUT5_DUTY); + + //************************************************************************** + // State 8 Calculations + //************************************************************************** + localparam [22:0] S8_CLKFBOUT = + s6_pll_count_calc(S8_CLKFBOUT_MULT, S8_CLKFBOUT_PHASE, 50000); + + localparam [22:0] S8_CLKFBOUT2 = + s6_pll_count_calc(S8_CLKFBOUT_MULT, S8_CLKFBOUT_PHASE, 50000); + + localparam [9:0] S8_DIGITAL_FILT = + s6_pll_filter_lookup(S8_CLKFBOUT_MULT, S8_BANDWIDTH); + + localparam [39:0] S8_LOCK = + s6_pll_lock_lookup(S8_CLKFBOUT_MULT); + + localparam [22:0] S8_DIVCLK = + s6_pll_count_calc(S8_DIVCLK_DIVIDE, 0, 50000); + + localparam [22:0] S8_CLKOUT0 = + s6_pll_count_calc(S8_CLKOUT0_DIVIDE, S8_CLKOUT0_PHASE, S8_CLKOUT0_DUTY); + + localparam [22:0] S8_CLKOUT1 = + s6_pll_count_calc(S8_CLKOUT1_DIVIDE, S8_CLKOUT1_PHASE, S8_CLKOUT1_DUTY); + + localparam [22:0] S8_CLKOUT2 = + s6_pll_count_calc(S8_CLKOUT2_DIVIDE, S8_CLKOUT2_PHASE, S8_CLKOUT2_DUTY); + + localparam [22:0] S8_CLKOUT3 = + s6_pll_count_calc(S8_CLKOUT3_DIVIDE, S8_CLKOUT3_PHASE, S8_CLKOUT3_DUTY); + + localparam [22:0] S8_CLKOUT4 = + s6_pll_count_calc(S8_CLKOUT4_DIVIDE, S8_CLKOUT4_PHASE, S8_CLKOUT4_DUTY); + + localparam [22:0] S8_CLKOUT5 = + s6_pll_count_calc(S8_CLKOUT5_DIVIDE, S8_CLKOUT5_PHASE, S8_CLKOUT5_DUTY); + + initial begin + // rom entries contain (in order) the address, a bitmask, and a bitset + //*********************************************************************** + // State 1 Initialization + //*********************************************************************** + + rom[0] = {5'h05, 16'h50FF, S1_CLKOUT0[19], 1'b0, S1_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S1_CLKOUT0[16], S1_CLKOUT0[17], S1_CLKOUT0[15], S1_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[1] = {5'h06, 16'h010B, S1_CLKOUT1[4], S1_CLKOUT1[5], S1_CLKOUT1[3], S1_CLKOUT1[12], //bits 15 down to 12 + S1_CLKOUT1[1], S1_CLKOUT1[2], S1_CLKOUT1[19], 1'b0, S1_CLKOUT1[17], S1_CLKOUT1[16], //bits 11 down to 6 + S1_CLKOUT1[14], S1_CLKOUT1[15], 1'b0, S1_CLKOUT0[13], 2'b00}; //bits 5 down to 0 + + rom[2] = {5'h07, 16'hE02C, 3'b000, S1_CLKOUT1[11], S1_CLKOUT1[9], S1_CLKOUT1[10], //bits 15 down to 10 + S1_CLKOUT1[8], S1_CLKOUT1[7], S1_CLKOUT1[6], S1_CLKOUT1[20], 1'b0, S1_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S1_CLKOUT1[21], S1_CLKOUT1[22]}; //bits 3 down to 0 + + rom[3] = {5'h08, 16'h4001, S1_CLKOUT2[22], 1'b0, S1_CLKOUT2[5], S1_CLKOUT2[21], //bits 15 downto 12 + S1_CLKOUT2[12], S1_CLKOUT2[4], S1_CLKOUT2[3], S1_CLKOUT2[2], S1_CLKOUT2[0], S1_CLKOUT2[19], //bits 11 down to 6 + S1_CLKOUT2[17], S1_CLKOUT2[18], S1_CLKOUT2[15], S1_CLKOUT2[16], S1_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[4] = {5'h09, 16'h0D03, S1_CLKOUT3[14], S1_CLKOUT3[15], S1_CLKOUT0[21], S1_CLKOUT0[22], 2'b00, S1_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S1_CLKOUT2[9], S1_CLKOUT2[8], S1_CLKOUT2[6], S1_CLKOUT2[7], S1_CLKOUT2[13], S1_CLKOUT2[20], 2'b00}; //bits 7 downto 0 + + rom[5] = {5'h0A, 16'hB001, 1'b0, S1_CLKOUT3[13], 2'b00, S1_CLKOUT3[21], S1_CLKOUT3[22], S1_CLKOUT3[5], S1_CLKOUT3[4], //bits 15 downto 8 + S1_CLKOUT3[12], S1_CLKOUT3[2], S1_CLKOUT3[0], S1_CLKOUT3[1], S1_CLKOUT3[18], S1_CLKOUT3[19], //bits 7 downto 2 + S1_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[6] = {5'h0B, 16'h0110, S1_CLKOUT0[5], S1_CLKOUT4[19], S1_CLKOUT4[14], S1_CLKOUT4[17], //bits 15 downto 12 + S1_CLKOUT4[15], S1_CLKOUT4[16], S1_CLKOUT0[4], 1'b0, S1_CLKOUT3[11], S1_CLKOUT3[10], //bits 11 downto 6 + S1_CLKOUT3[9], 1'b0, S1_CLKOUT3[7], S1_CLKOUT3[8], S1_CLKOUT3[20], S1_CLKOUT3[6]}; //bits 5 downto 0 + + rom[7] = {5'h0C, 16'h0B00, S1_CLKOUT4[7], S1_CLKOUT4[8], S1_CLKOUT4[20], S1_CLKOUT4[6], 1'b0, S1_CLKOUT4[13], //bits 15 downto 10 + 2'b00, S1_CLKOUT4[22], S1_CLKOUT4[21], S1_CLKOUT4[4], S1_CLKOUT4[5], S1_CLKOUT4[3], //bits 9 downto 3 + S1_CLKOUT4[12], S1_CLKOUT4[1], S1_CLKOUT4[2]}; //bits 2 downto 0 + + rom[8] = {5'h0D, 16'h0008, S1_CLKOUT5[2], S1_CLKOUT5[3], S1_CLKOUT5[0], S1_CLKOUT5[1], S1_CLKOUT5[18], //bits 15 downto 11 + S1_CLKOUT5[19], S1_CLKOUT5[17], S1_CLKOUT5[16], S1_CLKOUT5[15], S1_CLKOUT0[3], //bits 10 downto 6 + S1_CLKOUT0[0], S1_CLKOUT0[2], 1'b0, S1_CLKOUT4[11], S1_CLKOUT4[9], S1_CLKOUT4[10]}; //bits 5 downto 0 + + rom[9] = {5'h0E, 16'h00D0, S1_CLKOUT5[10], S1_CLKOUT5[11], S1_CLKOUT5[8], S1_CLKOUT5[9], S1_CLKOUT5[6], //bits 15 downto 11 + S1_CLKOUT5[7], S1_CLKOUT5[20], S1_CLKOUT5[13], 2'b00, S1_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S1_CLKOUT5[5], S1_CLKOUT5[21], S1_CLKOUT5[12], S1_CLKOUT5[4]}; //bits 3 downto 0 + + rom[10] = {5'h0F, 16'h0003, S1_CLKFBOUT[4], S1_CLKFBOUT[5], S1_CLKFBOUT[3], S1_CLKFBOUT[12], S1_CLKFBOUT[1], //bits 15 downto 11 + S1_CLKFBOUT[2], S1_CLKFBOUT[0], S1_CLKFBOUT[19], S1_CLKFBOUT[18], S1_CLKFBOUT[17], //bits 10 downto 6 + S1_CLKFBOUT[15], S1_CLKFBOUT[16], S1_CLKOUT0[12], S1_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[11] = {5'h10, 16'h800C, 1'b0, S1_CLKOUT0[9], S1_CLKOUT0[11], S1_CLKOUT0[10], S1_CLKFBOUT[10], S1_CLKFBOUT[11], //bits 15 downto 10 + S1_CLKFBOUT[9], S1_CLKFBOUT[8], S1_CLKFBOUT[7], S1_CLKFBOUT[6], S1_CLKFBOUT[13], //bits 9 downto 5 + S1_CLKFBOUT[20], 2'b00, S1_CLKFBOUT[21], S1_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[12] = {5'h11, 16'hFC00, 6'h00, S1_CLKOUT3[3], S1_CLKOUT3[16], S1_CLKOUT2[11], S1_CLKOUT2[1], S1_CLKOUT1[18], //bits 15 downto 6 + S1_CLKOUT1[0], S1_CLKOUT0[6], S1_CLKOUT0[20], S1_CLKOUT0[8], S1_CLKOUT0[7]}; //bits 5 downto 0 + + rom[13] = {5'h12, 16'hF0FF, 4'h0, S1_CLKOUT5[14], S1_CLKFBOUT[14], S1_CLKOUT4[0], S1_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[14] = {5'h13, 16'h5120, S1_DIVCLK[11], 1'b0, S1_DIVCLK[10], 1'b0, S1_DIVCLK[7], S1_DIVCLK[8], //bits 15 downto 10 + S1_DIVCLK[0], 1'b0, S1_DIVCLK[5], S1_DIVCLK[2], 1'b0, S1_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[15] = {5'h14, 16'h2FFF, S1_LOCK[1], S1_LOCK[2], 1'b0, S1_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[16] = {5'h15, 16'hBFF4, 1'b0, S1_DIVCLK[12], 10'h000, S1_LOCK[38], 1'b0, S1_LOCK[32], S1_LOCK[39]}; //bits 15 downto 0 + + rom[17] = {5'h16, 16'h0A55, S1_LOCK[15], S1_LOCK[13], S1_LOCK[27], S1_LOCK[16], 1'b0, S1_LOCK[10], //bits 15 downto 10 + 1'b0, S1_DIVCLK[9], S1_DIVCLK[1], 1'b0, S1_DIVCLK[6], 1'b0, S1_DIVCLK[3], //bits 9 downto 3 + 1'b0, S1_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[18] = {5'h17, 16'hFFD0, 10'h000, S1_LOCK[17], 1'b0, S1_LOCK[8], S1_LOCK[9], S1_LOCK[23], S1_LOCK[22]}; //bits 15 downto 0 + + rom[19] = {5'h18, 16'h1039, S1_DIGITAL_FILT[6], S1_DIGITAL_FILT[7], S1_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S1_DIGITAL_FILT[2], S1_DIGITAL_FILT[1], S1_DIGITAL_FILT[3], S1_DIGITAL_FILT[9], //bits 11 downto 8 + S1_DIGITAL_FILT[8], S1_LOCK[26], 3'h0, S1_LOCK[19], S1_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[20] = {5'h19, 16'h0000, S1_LOCK[24], S1_LOCK[25], S1_LOCK[21], S1_LOCK[14], S1_LOCK[11], //bits 15 downto 11 + S1_LOCK[12], S1_LOCK[20], S1_LOCK[6], S1_LOCK[35], S1_LOCK[36], //bits 10 downto 6 + S1_LOCK[37], S1_LOCK[3], S1_LOCK[33], S1_LOCK[31], S1_LOCK[34], S1_LOCK[30]}; //bits 5 downto 0 + + rom[21] = {5'h1A, 16'hFFFC, 14'h0000, S1_LOCK[28], S1_LOCK[29]}; //bits 15 downto 0 + + rom[22] = {5'h1D, 16'h2FFF, S1_LOCK[7], S1_LOCK[4], 1'b0, S1_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 2 Initialization + //*********************************************************************** + + rom[23] = {5'h05, 16'h50FF, S2_CLKOUT0[19], 1'b0, S2_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S2_CLKOUT0[16], S2_CLKOUT0[17], S2_CLKOUT0[15], S2_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[24] = {5'h06, 16'h010B, S2_CLKOUT1[4], S2_CLKOUT1[5], S2_CLKOUT1[3], S2_CLKOUT1[12], //bits 15 down to 12 + S2_CLKOUT1[1], S2_CLKOUT1[2], S2_CLKOUT1[19], 1'b0, S2_CLKOUT1[17], S2_CLKOUT1[16], //bits 11 down to 6 + S2_CLKOUT1[14], S2_CLKOUT1[15], 1'b0, S2_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[25] = {5'h07, 16'hE02C, 3'h0, S2_CLKOUT1[11], S2_CLKOUT1[9], S2_CLKOUT1[10], //bits 15 down to 10 + S2_CLKOUT1[8], S2_CLKOUT1[7], S2_CLKOUT1[6], S2_CLKOUT1[20], 1'b0, S2_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S2_CLKOUT1[21], S2_CLKOUT1[22]}; //bits 3 down to 0 + + rom[26] = {5'h08, 16'h4001, S2_CLKOUT2[22], 1'b0, S2_CLKOUT2[5], S2_CLKOUT2[21], //bits 15 downto 12 + S2_CLKOUT2[12], S2_CLKOUT2[4], S2_CLKOUT2[3], S2_CLKOUT2[2], S2_CLKOUT2[0], S2_CLKOUT2[19], //bits 11 down to 6 + S2_CLKOUT2[17], S2_CLKOUT2[18], S2_CLKOUT2[15], S2_CLKOUT2[16], S2_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[27] = {5'h09, 16'h0D03, S2_CLKOUT3[14], S2_CLKOUT3[15], S2_CLKOUT0[21], S2_CLKOUT0[22], 2'h0, S2_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S2_CLKOUT2[9], S2_CLKOUT2[8], S2_CLKOUT2[6], S2_CLKOUT2[7], S2_CLKOUT2[13], S2_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[28] = {5'h0A, 16'hB001, 1'b0, S2_CLKOUT3[13], 2'h0, S2_CLKOUT3[21], S2_CLKOUT3[22], S2_CLKOUT3[5], S2_CLKOUT3[4], //bits 15 downto 8 + S2_CLKOUT3[12], S2_CLKOUT3[2], S2_CLKOUT3[0], S2_CLKOUT3[1], S2_CLKOUT3[18], S2_CLKOUT3[19], //bits 7 downto 2 + S2_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[29] = {5'h0B, 16'h0110, S2_CLKOUT0[5], S2_CLKOUT4[19], S2_CLKOUT4[14], S2_CLKOUT4[17], //bits 15 downto 12 + S2_CLKOUT4[15], S2_CLKOUT4[16], S2_CLKOUT0[4], 1'b0, S2_CLKOUT3[11], S2_CLKOUT3[10], //bits 11 downto 6 + S2_CLKOUT3[9], 1'b0, S2_CLKOUT3[7], S2_CLKOUT3[8], S2_CLKOUT3[20], S2_CLKOUT3[6]}; //bits 5 downto 0 + + rom[30] = {5'h0C, 16'h0B00, S2_CLKOUT4[7], S2_CLKOUT4[8], S2_CLKOUT4[20], S2_CLKOUT4[6], 1'b0, S2_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S2_CLKOUT4[22], S2_CLKOUT4[21], S2_CLKOUT4[4], S2_CLKOUT4[5], S2_CLKOUT4[3], //bits 9 downto 3 + S2_CLKOUT4[12], S2_CLKOUT4[1], S2_CLKOUT4[2]}; //bits 2 downto 0 + + rom[31] = {5'h0D, 16'h0008, S2_CLKOUT5[2], S2_CLKOUT5[3], S2_CLKOUT5[0], S2_CLKOUT5[1], S2_CLKOUT5[18], //bits 15 downto 11 + S2_CLKOUT5[19], S2_CLKOUT5[17], S2_CLKOUT5[16], S2_CLKOUT5[15], S2_CLKOUT0[3], //bits 10 downto 6 + S2_CLKOUT0[0], S2_CLKOUT0[2], 1'b0, S2_CLKOUT4[11], S2_CLKOUT4[9], S2_CLKOUT4[10]}; //bits 5 downto 0 + + rom[32] = {5'h0E, 16'h00D0, S2_CLKOUT5[10], S2_CLKOUT5[11], S2_CLKOUT5[8], S2_CLKOUT5[9], S2_CLKOUT5[6], //bits 15 downto 11 + S2_CLKOUT5[7], S2_CLKOUT5[20], S2_CLKOUT5[13], 2'h0, S2_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S2_CLKOUT5[5], S2_CLKOUT5[21], S2_CLKOUT5[12], S2_CLKOUT5[4]}; //bits 3 downto 0 + + rom[33] = {5'h0F, 16'h0003, S2_CLKFBOUT[4], S2_CLKFBOUT[5], S2_CLKFBOUT[3], S2_CLKFBOUT[12], S2_CLKFBOUT[1], //bits 15 downto 11 + S2_CLKFBOUT[2], S2_CLKFBOUT[0], S2_CLKFBOUT[19], S2_CLKFBOUT[18], S2_CLKFBOUT[17], //bits 10 downto 6 + S2_CLKFBOUT[15], S2_CLKFBOUT[16], S2_CLKOUT0[12], S2_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[34] = {5'h10, 16'h800C, 1'b0, S2_CLKOUT0[9], S2_CLKOUT0[11], S2_CLKOUT0[10], S2_CLKFBOUT[10], S2_CLKFBOUT[11], //bits 15 downto 10 + S2_CLKFBOUT[9], S2_CLKFBOUT[8], S2_CLKFBOUT[7], S2_CLKFBOUT[6], S2_CLKFBOUT[13], //bits 9 downto 5 + S2_CLKFBOUT[20], 2'h0, S2_CLKFBOUT[21], S2_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[35] = {5'h11, 16'hFC00, 6'h00, S2_CLKOUT3[3], S2_CLKOUT3[16], S2_CLKOUT2[11], S2_CLKOUT2[1], S2_CLKOUT1[18], //bits 15 downto 6 + S2_CLKOUT1[0], S2_CLKOUT0[6], S2_CLKOUT0[20], S2_CLKOUT0[8], S2_CLKOUT0[7]}; //bits 5 downto 0 + + rom[36] = {5'h12, 16'hF0FF, 4'h0, S2_CLKOUT5[14], S2_CLKFBOUT[14], S2_CLKOUT4[0], S2_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[37] = {5'h13, 16'h5120, S2_DIVCLK[11], 1'b0, S2_DIVCLK[10], 1'b0, S2_DIVCLK[7], S2_DIVCLK[8], //bits 15 downto 10 + S2_DIVCLK[0], 1'b0, S2_DIVCLK[5], S2_DIVCLK[2], 1'b0, S2_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[38] = {5'h14, 16'h2FFF, S2_LOCK[1], S2_LOCK[2], 1'b0, S2_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[39] = {5'h15, 16'hBFF4, 1'b0, S2_DIVCLK[12], 10'h000, S2_LOCK[38], 1'b0, S2_LOCK[32], S2_LOCK[39]}; //bits 15 downto 0 + + rom[40] = {5'h16, 16'h0A55, S2_LOCK[15], S2_LOCK[13], S2_LOCK[27], S2_LOCK[16], 1'b0, S2_LOCK[10], //bits 15 downto 10 + 1'b0, S2_DIVCLK[9], S2_DIVCLK[1], 1'b0, S2_DIVCLK[6], 1'b0, S2_DIVCLK[3], //bits 9 downto 3 + 1'b0, S2_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[41] = {5'h17, 16'hFFD0, 10'h000, S2_LOCK[17], 1'b0, S2_LOCK[8], S2_LOCK[9], S2_LOCK[23], S2_LOCK[22]}; //bits 15 downto 0 + + rom[42] = {5'h18, 16'h1039, S2_DIGITAL_FILT[6], S2_DIGITAL_FILT[7], S2_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S2_DIGITAL_FILT[2], S2_DIGITAL_FILT[1], S2_DIGITAL_FILT[3], S2_DIGITAL_FILT[9], //bits 11 downto 8 + S2_DIGITAL_FILT[8], S2_LOCK[26], 3'h0, S2_LOCK[19], S2_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[43] = {5'h19, 16'h0000, S2_LOCK[24], S2_LOCK[25], S2_LOCK[21], S2_LOCK[14], S2_LOCK[11], //bits 15 downto 11 + S2_LOCK[12], S2_LOCK[20], S2_LOCK[6], S2_LOCK[35], S2_LOCK[36], //bits 10 downto 6 + S2_LOCK[37], S2_LOCK[3], S2_LOCK[33], S2_LOCK[31], S2_LOCK[34], S2_LOCK[30]}; //bits 5 downto 0 + + rom[44] = {5'h1A, 16'hFFFC, 14'h0000, S2_LOCK[28], S2_LOCK[29]}; //bits 15 downto 0 + + rom[45] = {5'h1D, 16'h2FFF, S2_LOCK[7], S2_LOCK[4], 1'b0, S2_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 3 Initialization + //*********************************************************************** + + rom[46] = {5'h05, 16'h50FF, S3_CLKOUT0[19], 1'b0, S3_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S3_CLKOUT0[16], S3_CLKOUT0[17], S3_CLKOUT0[15], S3_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[47] = {5'h06, 16'h010B, S3_CLKOUT1[4], S3_CLKOUT1[5], S3_CLKOUT1[3], S3_CLKOUT1[12], //bits 15 down to 12 + S3_CLKOUT1[1], S3_CLKOUT1[2], S3_CLKOUT1[19], 1'b0, S3_CLKOUT1[17], S3_CLKOUT1[16], //bits 11 down to 6 + S3_CLKOUT1[14], S3_CLKOUT1[15], 1'b0, S3_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[48] = {5'h07, 16'hE02C, 3'h0, S3_CLKOUT1[11], S3_CLKOUT1[9], S3_CLKOUT1[10], //bits 15 down to 10 + S3_CLKOUT1[8], S3_CLKOUT1[7], S3_CLKOUT1[6], S3_CLKOUT1[20], 1'b0, S3_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S3_CLKOUT1[21], S3_CLKOUT1[22]}; //bits 3 down to 0 + + rom[49] = {5'h08, 16'h4001, S3_CLKOUT2[22], 1'b0, S3_CLKOUT2[5], S3_CLKOUT2[21], //bits 15 downto 12 + S3_CLKOUT2[12], S3_CLKOUT2[4], S3_CLKOUT2[3], S3_CLKOUT2[2], S3_CLKOUT2[0], S3_CLKOUT2[19], //bits 11 down to 6 + S3_CLKOUT2[17], S3_CLKOUT2[18], S3_CLKOUT2[15], S3_CLKOUT2[16], S3_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[50] = {5'h09, 16'h0D03, S3_CLKOUT3[14], S3_CLKOUT3[15], S3_CLKOUT0[21], S3_CLKOUT0[22], 2'h0, S3_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S3_CLKOUT2[9], S3_CLKOUT2[8], S3_CLKOUT2[6], S3_CLKOUT2[7], S3_CLKOUT2[13], S3_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[51] = {5'h0A, 16'hB001, 1'b0, S3_CLKOUT3[13], 2'h0, S3_CLKOUT3[21], S3_CLKOUT3[22], S3_CLKOUT3[5], S3_CLKOUT3[4], //bits 15 downto 8 + S3_CLKOUT3[12], S3_CLKOUT3[2], S3_CLKOUT3[0], S3_CLKOUT3[1], S3_CLKOUT3[18], S3_CLKOUT3[19], //bits 7 downto 2 + S3_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[52] = {5'h0B, 16'h0110, S3_CLKOUT0[5], S3_CLKOUT4[19], S3_CLKOUT4[14], S3_CLKOUT4[17], //bits 15 downto 12 + S3_CLKOUT4[15], S3_CLKOUT4[16], S3_CLKOUT0[4], 1'b0, S3_CLKOUT3[11], S3_CLKOUT3[10], //bits 11 downto 6 + S3_CLKOUT3[9], 1'b0, S3_CLKOUT3[7], S3_CLKOUT3[8], S3_CLKOUT3[20], S3_CLKOUT3[6]}; //bits 5 downto 0 + + rom[53] = {5'h0C, 16'h0B00, S3_CLKOUT4[7], S3_CLKOUT4[8], S3_CLKOUT4[20], S3_CLKOUT4[6], 1'b0, S3_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S3_CLKOUT4[22], S3_CLKOUT4[21], S3_CLKOUT4[4], S3_CLKOUT4[5], S3_CLKOUT4[3], //bits 9 downto 3 + S3_CLKOUT4[12], S3_CLKOUT4[1], S3_CLKOUT4[2]}; //bits 2 downto 0 + + rom[54] = {5'h0D, 16'h0008, S3_CLKOUT5[2], S3_CLKOUT5[3], S3_CLKOUT5[0], S3_CLKOUT5[1], S3_CLKOUT5[18], //bits 15 downto 11 + S3_CLKOUT5[19], S3_CLKOUT5[17], S3_CLKOUT5[16], S3_CLKOUT5[15], S3_CLKOUT0[3], //bits 10 downto 6 + S3_CLKOUT0[0], S3_CLKOUT0[2], 1'b0, S3_CLKOUT4[11], S3_CLKOUT4[9], S3_CLKOUT4[10]}; //bits 5 downto 0 + + rom[55] = {5'h0E, 16'h00D0, S3_CLKOUT5[10], S3_CLKOUT5[11], S3_CLKOUT5[8], S3_CLKOUT5[9], S3_CLKOUT5[6], //bits 15 downto 11 + S3_CLKOUT5[7], S3_CLKOUT5[20], S3_CLKOUT5[13], 2'h0, S3_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S3_CLKOUT5[5], S3_CLKOUT5[21], S3_CLKOUT5[12], S3_CLKOUT5[4]}; //bits 3 downto 0 + + rom[56] = {5'h0F, 16'h0003, S3_CLKFBOUT[4], S3_CLKFBOUT[5], S3_CLKFBOUT[3], S3_CLKFBOUT[12], S3_CLKFBOUT[1], //bits 15 downto 11 + S3_CLKFBOUT[2], S3_CLKFBOUT[0], S3_CLKFBOUT[19], S3_CLKFBOUT[18], S3_CLKFBOUT[17], //bits 10 downto 6 + S3_CLKFBOUT[15], S3_CLKFBOUT[16], S3_CLKOUT0[12], S3_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[57] = {5'h10, 16'h800C, 1'b0, S3_CLKOUT0[9], S3_CLKOUT0[11], S3_CLKOUT0[10], S3_CLKFBOUT[10], S3_CLKFBOUT[11], //bits 15 downto 10 + S3_CLKFBOUT[9], S3_CLKFBOUT[8], S3_CLKFBOUT[7], S3_CLKFBOUT[6], S3_CLKFBOUT[13], //bits 9 downto 5 + S3_CLKFBOUT[20], 2'h0, S3_CLKFBOUT[21], S3_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[58] = {5'h11, 16'hFC00, 6'h00, S3_CLKOUT3[3], S3_CLKOUT3[16], S3_CLKOUT2[11], S3_CLKOUT2[1], S3_CLKOUT1[18], //bits 15 downto 6 + S3_CLKOUT1[0], S3_CLKOUT0[6], S3_CLKOUT0[20], S3_CLKOUT0[8], S3_CLKOUT0[7]}; //bits 5 downto 0 + + rom[59] = {5'h12, 16'hF0FF, 4'h0, S3_CLKOUT5[14], S3_CLKFBOUT[14], S3_CLKOUT4[0], S3_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[60] = {5'h13, 16'h5120, S3_DIVCLK[11], 1'b0, S3_DIVCLK[10], 1'b0, S3_DIVCLK[7], S3_DIVCLK[8], //bits 15 downto 10 + S3_DIVCLK[0], 1'b0, S3_DIVCLK[5], S3_DIVCLK[2], 1'b0, S3_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[61] = {5'h14, 16'h2FFF, S3_LOCK[1], S3_LOCK[2], 1'b0, S3_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[62] = {5'h15, 16'hBFF4, 1'b0, S3_DIVCLK[12], 10'h000, S3_LOCK[38], 1'b0, S3_LOCK[32], S3_LOCK[39]}; //bits 15 downto 0 + + rom[63] = {5'h16, 16'h0A55, S3_LOCK[15], S3_LOCK[13], S3_LOCK[27], S3_LOCK[16], 1'b0, S3_LOCK[10], //bits 15 downto 10 + 1'b0, S3_DIVCLK[9], S3_DIVCLK[1], 1'b0, S3_DIVCLK[6], 1'b0, S3_DIVCLK[3], //bits 9 downto 3 + 1'b0, S3_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[64] = {5'h17, 16'hFFD0, 10'h000, S3_LOCK[17], 1'b0, S3_LOCK[8], S3_LOCK[9], S3_LOCK[23], S3_LOCK[22]}; //bits 15 downto 0 + + rom[65] = {5'h18, 16'h1039, S3_DIGITAL_FILT[6], S3_DIGITAL_FILT[7], S3_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S3_DIGITAL_FILT[2], S3_DIGITAL_FILT[1], S3_DIGITAL_FILT[3], S3_DIGITAL_FILT[9], //bits 11 downto 8 + S3_DIGITAL_FILT[8], S3_LOCK[26], 3'h0, S3_LOCK[19], S3_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[66] = {5'h19, 16'h0000, S3_LOCK[24], S3_LOCK[25], S3_LOCK[21], S3_LOCK[14], S3_LOCK[11], //bits 15 downto 11 + S3_LOCK[12], S3_LOCK[20], S3_LOCK[6], S3_LOCK[35], S3_LOCK[36], //bits 10 downto 6 + S3_LOCK[37], S3_LOCK[3], S3_LOCK[33], S3_LOCK[31], S3_LOCK[34], S3_LOCK[30]}; //bits 5 downto 0 + + rom[67] = {5'h1A, 16'hFFFC, 14'h0000, S3_LOCK[28], S3_LOCK[29]}; //bits 15 downto 0 + + rom[68] = {5'h1D, 16'h2FFF, S3_LOCK[7], S3_LOCK[4], 1'b0, S3_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 4 Initialization + //*********************************************************************** + + rom[69] = {5'h05, 16'h50FF, S4_CLKOUT0[19], 1'b0, S4_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S4_CLKOUT0[16], S4_CLKOUT0[17], S4_CLKOUT0[15], S4_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[70] = {5'h06, 16'h010B, S4_CLKOUT1[4], S4_CLKOUT1[5], S4_CLKOUT1[3], S4_CLKOUT1[12], //bits 15 down to 12 + S4_CLKOUT1[1], S4_CLKOUT1[2], S4_CLKOUT1[19], 1'b0, S4_CLKOUT1[17], S4_CLKOUT1[16], //bits 11 down to 6 + S4_CLKOUT1[14], S4_CLKOUT1[15], 1'b0, S4_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[71] = {5'h07, 16'hE02C, 3'h0, S4_CLKOUT1[11], S4_CLKOUT1[9], S4_CLKOUT1[10], //bits 15 down to 10 + S4_CLKOUT1[8], S4_CLKOUT1[7], S4_CLKOUT1[6], S4_CLKOUT1[20], 1'b0, S4_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S4_CLKOUT1[21], S4_CLKOUT1[22]}; //bits 3 down to 0 + + rom[72] = {5'h08, 16'h4001, S4_CLKOUT2[22], 1'b0, S4_CLKOUT2[5], S4_CLKOUT2[21], //bits 15 downto 12 + S4_CLKOUT2[12], S4_CLKOUT2[4], S4_CLKOUT2[3], S4_CLKOUT2[2], S4_CLKOUT2[0], S4_CLKOUT2[19], //bits 11 down to 6 + S4_CLKOUT2[17], S4_CLKOUT2[18], S4_CLKOUT2[15], S4_CLKOUT2[16], S4_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[73] = {5'h09, 16'h0D03, S4_CLKOUT3[14], S4_CLKOUT3[15], S4_CLKOUT0[21], S4_CLKOUT0[22], 2'h0, S4_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S4_CLKOUT2[9], S4_CLKOUT2[8], S4_CLKOUT2[6], S4_CLKOUT2[7], S4_CLKOUT2[13], S4_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[74] = {5'h0A, 16'hB001, 1'b0, S4_CLKOUT3[13], 2'h0, S4_CLKOUT3[21], S4_CLKOUT3[22], S4_CLKOUT3[5], S4_CLKOUT3[4], //bits 15 downto 8 + S4_CLKOUT3[12], S4_CLKOUT3[2], S4_CLKOUT3[0], S4_CLKOUT3[1], S4_CLKOUT3[18], S4_CLKOUT3[19], //bits 7 downto 2 + S4_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[75] = {5'h0B, 16'h0110, S4_CLKOUT0[5], S4_CLKOUT4[19], S4_CLKOUT4[14], S4_CLKOUT4[17], //bits 15 downto 12 + S4_CLKOUT4[15], S4_CLKOUT4[16], S4_CLKOUT0[4], 1'b0, S4_CLKOUT3[11], S4_CLKOUT3[10], //bits 11 downto 6 + S4_CLKOUT3[9], 1'b0, S4_CLKOUT3[7], S4_CLKOUT3[8], S4_CLKOUT3[20], S4_CLKOUT3[6]}; //bits 5 downto 0 + + rom[76] = {5'h0C, 16'h0B00, S4_CLKOUT4[7], S4_CLKOUT4[8], S4_CLKOUT4[20], S4_CLKOUT4[6], 1'b0, S4_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S4_CLKOUT4[22], S4_CLKOUT4[21], S4_CLKOUT4[4], S4_CLKOUT4[5], S4_CLKOUT4[3], //bits 9 downto 3 + S4_CLKOUT4[12], S4_CLKOUT4[1], S4_CLKOUT4[2]}; //bits 2 downto 0 + + rom[77] = {5'h0D, 16'h0008, S4_CLKOUT5[2], S4_CLKOUT5[3], S4_CLKOUT5[0], S4_CLKOUT5[1], S4_CLKOUT5[18], //bits 15 downto 11 + S4_CLKOUT5[19], S4_CLKOUT5[17], S4_CLKOUT5[16], S4_CLKOUT5[15], S4_CLKOUT0[3], //bits 10 downto 6 + S4_CLKOUT0[0], S4_CLKOUT0[2], 1'b0, S4_CLKOUT4[11], S4_CLKOUT4[9], S4_CLKOUT4[10]}; //bits 5 downto 0 + + rom[78] = {5'h0E, 16'h00D0, S4_CLKOUT5[10], S4_CLKOUT5[11], S4_CLKOUT5[8], S4_CLKOUT5[9], S4_CLKOUT5[6], //bits 15 downto 11 + S4_CLKOUT5[7], S4_CLKOUT5[20], S4_CLKOUT5[13], 2'h0, S4_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S4_CLKOUT5[5], S4_CLKOUT5[21], S4_CLKOUT5[12], S4_CLKOUT5[4]}; //bits 3 downto 0 + + rom[79] = {5'h0F, 16'h0003, S4_CLKFBOUT[4], S4_CLKFBOUT[5], S4_CLKFBOUT[3], S4_CLKFBOUT[12], S4_CLKFBOUT[1], //bits 15 downto 11 + S4_CLKFBOUT[2], S4_CLKFBOUT[0], S4_CLKFBOUT[19], S4_CLKFBOUT[18], S4_CLKFBOUT[17], //bits 10 downto 6 + S4_CLKFBOUT[15], S4_CLKFBOUT[16], S4_CLKOUT0[12], S4_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[80] = {5'h10, 16'h800C, 1'b0, S4_CLKOUT0[9], S4_CLKOUT0[11], S4_CLKOUT0[10], S4_CLKFBOUT[10], S4_CLKFBOUT[11], //bits 15 downto 10 + S4_CLKFBOUT[9], S4_CLKFBOUT[8], S4_CLKFBOUT[7], S4_CLKFBOUT[6], S4_CLKFBOUT[13], //bits 9 downto 5 + S4_CLKFBOUT[20], 2'h0, S4_CLKFBOUT[21], S4_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[81] = {5'h11, 16'hFC00, 6'h00, S4_CLKOUT3[3], S4_CLKOUT3[16], S4_CLKOUT2[11], S4_CLKOUT2[1], S4_CLKOUT1[18], //bits 15 downto 6 + S4_CLKOUT1[0], S4_CLKOUT0[6], S4_CLKOUT0[20], S4_CLKOUT0[8], S4_CLKOUT0[7]}; //bits 5 downto 0 + + rom[82] = {5'h12, 16'hF0FF, 4'h0, S4_CLKOUT5[14], S4_CLKFBOUT[14], S4_CLKOUT4[0], S4_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[83] = {5'h13, 16'h5120, S4_DIVCLK[11], 1'b0, S4_DIVCLK[10], 1'b0, S4_DIVCLK[7], S4_DIVCLK[8], //bits 15 downto 10 + S4_DIVCLK[0], 1'b0, S4_DIVCLK[5], S4_DIVCLK[2], 1'b0, S4_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[84] = {5'h14, 16'h2FFF, S4_LOCK[1], S4_LOCK[2], 1'b0, S4_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[85] = {5'h15, 16'hBFF4, 1'b0, S4_DIVCLK[12], 10'h000, S4_LOCK[38], 1'b0, S4_LOCK[32], S4_LOCK[39]}; //bits 15 downto 0 + + rom[86] = {5'h16, 16'h0A55, S4_LOCK[15], S4_LOCK[13], S4_LOCK[27], S4_LOCK[16], 1'b0, S4_LOCK[10], //bits 15 downto 10 + 1'b0, S4_DIVCLK[9], S4_DIVCLK[1], 1'b0, S4_DIVCLK[6], 1'b0, S4_DIVCLK[3], //bits 9 downto 3 + 1'b0, S4_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[87] = {5'h17, 16'hFFD0, 10'h000, S4_LOCK[17], 1'b0, S4_LOCK[8], S4_LOCK[9], S4_LOCK[23], S4_LOCK[22]}; //bits 15 downto 0 + + rom[88] = {5'h18, 16'h1039, S4_DIGITAL_FILT[6], S4_DIGITAL_FILT[7], S4_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S4_DIGITAL_FILT[2], S4_DIGITAL_FILT[1], S4_DIGITAL_FILT[3], S4_DIGITAL_FILT[9], //bits 11 downto 8 + S4_DIGITAL_FILT[8], S4_LOCK[26], 3'h0, S4_LOCK[19], S4_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[89] = {5'h19, 16'h0000, S4_LOCK[24], S4_LOCK[25], S4_LOCK[21], S4_LOCK[14], S4_LOCK[11], //bits 15 downto 11 + S4_LOCK[12], S4_LOCK[20], S4_LOCK[6], S4_LOCK[35], S4_LOCK[36], //bits 10 downto 6 + S4_LOCK[37], S4_LOCK[3], S4_LOCK[33], S4_LOCK[31], S4_LOCK[34], S4_LOCK[30]}; //bits 5 downto 0 + + rom[90] = {5'h1A, 16'hFFFC, 14'h0000, S4_LOCK[28], S4_LOCK[29]}; //bits 15 downto 0 + + rom[91] = {5'h1D, 16'h2FFF, S4_LOCK[7], S4_LOCK[4], 1'b0, S4_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 5 Initialization + //*********************************************************************** + + rom[92] = {5'h05, 16'h50FF, S5_CLKOUT0[19], 1'b0, S5_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S5_CLKOUT0[16], S5_CLKOUT0[17], S5_CLKOUT0[15], S5_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[93] = {5'h06, 16'h010B, S5_CLKOUT1[4], S5_CLKOUT1[5], S5_CLKOUT1[3], S5_CLKOUT1[12], //bits 15 down to 12 + S5_CLKOUT1[1], S5_CLKOUT1[2], S5_CLKOUT1[19], 1'b0, S5_CLKOUT1[17], S5_CLKOUT1[16], //bits 11 down to 6 + S5_CLKOUT1[14], S5_CLKOUT1[15], 1'b0, S5_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[94] = {5'h07, 16'hE02C, 3'h0, S5_CLKOUT1[11], S5_CLKOUT1[9], S5_CLKOUT1[10], //bits 15 down to 10 + S5_CLKOUT1[8], S5_CLKOUT1[7], S5_CLKOUT1[6], S5_CLKOUT1[20], 1'b0, S5_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S5_CLKOUT1[21], S5_CLKOUT1[22]}; //bits 3 down to 0 + + rom[95] = {5'h08, 16'h4001, S5_CLKOUT2[22], 1'b0, S5_CLKOUT2[5], S5_CLKOUT2[21], //bits 15 downto 12 + S5_CLKOUT2[12], S5_CLKOUT2[4], S5_CLKOUT2[3], S5_CLKOUT2[2], S5_CLKOUT2[0], S5_CLKOUT2[19], //bits 11 down to 6 + S5_CLKOUT2[17], S5_CLKOUT2[18], S5_CLKOUT2[15], S5_CLKOUT2[16], S5_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[96] = {5'h09, 16'h0D03, S5_CLKOUT3[14], S5_CLKOUT3[15], S5_CLKOUT0[21], S5_CLKOUT0[22], 2'h0, S5_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S5_CLKOUT2[9], S5_CLKOUT2[8], S5_CLKOUT2[6], S5_CLKOUT2[7], S5_CLKOUT2[13], S5_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[97] = {5'h0A, 16'hB001, 1'b0, S5_CLKOUT3[13], 2'h0, S5_CLKOUT3[21], S5_CLKOUT3[22], S5_CLKOUT3[5], S5_CLKOUT3[4], //bits 15 downto 8 + S5_CLKOUT3[12], S5_CLKOUT3[2], S5_CLKOUT3[0], S5_CLKOUT3[1], S5_CLKOUT3[18], S5_CLKOUT3[19], //bits 7 downto 2 + S5_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[98] = {5'h0B, 16'h0110, S5_CLKOUT0[5], S5_CLKOUT4[19], S5_CLKOUT4[14], S5_CLKOUT4[17], //bits 15 downto 12 + S5_CLKOUT4[15], S5_CLKOUT4[16], S5_CLKOUT0[4], 1'b0, S5_CLKOUT3[11], S5_CLKOUT3[10], //bits 11 downto 6 + S5_CLKOUT3[9], 1'b0, S5_CLKOUT3[7], S5_CLKOUT3[8], S5_CLKOUT3[20], S5_CLKOUT3[6]}; //bits 5 downto 0 + + rom[99] = {5'h0C, 16'h0B00, S5_CLKOUT4[7], S5_CLKOUT4[8], S5_CLKOUT4[20], S5_CLKOUT4[6], 1'b0, S5_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S5_CLKOUT4[22], S5_CLKOUT4[21], S5_CLKOUT4[4], S5_CLKOUT4[5], S5_CLKOUT4[3], //bits 9 downto 3 + S5_CLKOUT4[12], S5_CLKOUT4[1], S5_CLKOUT4[2]}; //bits 2 downto 0 + + rom[100] = {5'h0D, 16'h0008, S5_CLKOUT5[2], S5_CLKOUT5[3], S5_CLKOUT5[0], S5_CLKOUT5[1], S5_CLKOUT5[18], //bits 15 downto 11 + S5_CLKOUT5[19], S5_CLKOUT5[17], S5_CLKOUT5[16], S5_CLKOUT5[15], S5_CLKOUT0[3], //bits 10 downto 6 + S5_CLKOUT0[0], S5_CLKOUT0[2], 1'b0, S5_CLKOUT4[11], S5_CLKOUT4[9], S5_CLKOUT4[10]}; //bits 5 downto 0 + + rom[101] = {5'h0E, 16'h00D0, S5_CLKOUT5[10], S5_CLKOUT5[11], S5_CLKOUT5[8], S5_CLKOUT5[9], S5_CLKOUT5[6], //bits 15 downto 11 + S5_CLKOUT5[7], S5_CLKOUT5[20], S5_CLKOUT5[13], 2'h0, S5_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S5_CLKOUT5[5], S5_CLKOUT5[21], S5_CLKOUT5[12], S5_CLKOUT5[4]}; //bits 3 downto 0 + + rom[102] = {5'h0F, 16'h0003, S5_CLKFBOUT[4], S5_CLKFBOUT[5], S5_CLKFBOUT[3], S5_CLKFBOUT[12], S5_CLKFBOUT[1], //bits 15 downto 11 + S5_CLKFBOUT[2], S5_CLKFBOUT[0], S5_CLKFBOUT[19], S5_CLKFBOUT[18], S5_CLKFBOUT[17], //bits 10 downto 6 + S5_CLKFBOUT[15], S5_CLKFBOUT[16], S5_CLKOUT0[12], S5_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[103] = {5'h10, 16'h800C, 1'b0, S5_CLKOUT0[9], S5_CLKOUT0[11], S5_CLKOUT0[10], S5_CLKFBOUT[10], S5_CLKFBOUT[11], //bits 15 downto 10 + S5_CLKFBOUT[9], S5_CLKFBOUT[8], S5_CLKFBOUT[7], S5_CLKFBOUT[6], S5_CLKFBOUT[13], //bits 9 downto 5 + S5_CLKFBOUT[20], 2'h0, S5_CLKFBOUT[21], S5_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[104] = {5'h11, 16'hFC00, 6'h00, S5_CLKOUT3[3], S5_CLKOUT3[16], S5_CLKOUT2[11], S5_CLKOUT2[1], S5_CLKOUT1[18], //bits 15 downto 6 + S5_CLKOUT1[0], S5_CLKOUT0[6], S5_CLKOUT0[20], S5_CLKOUT0[8], S5_CLKOUT0[7]}; //bits 5 downto 0 + + rom[105] = {5'h12, 16'hF0FF, 4'h0, S5_CLKOUT5[14], S5_CLKFBOUT[14], S5_CLKOUT4[0], S5_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[106] = {5'h13, 16'h5120, S5_DIVCLK[11], 1'b0, S5_DIVCLK[10], 1'b0, S5_DIVCLK[7], S5_DIVCLK[8], //bits 15 downto 10 + S5_DIVCLK[0], 1'b0, S5_DIVCLK[5], S5_DIVCLK[2], 1'b0, S5_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[107] = {5'h14, 16'h2FFF, S5_LOCK[1], S5_LOCK[2], 1'b0, S5_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[108] = {5'h15, 16'hBFF4, 1'b0, S5_DIVCLK[12], 10'h000, S5_LOCK[38], 1'b0, S5_LOCK[32], S5_LOCK[39]}; //bits 15 downto 0 + + rom[109] = {5'h16, 16'h0A55, S5_LOCK[15], S5_LOCK[13], S5_LOCK[27], S5_LOCK[16], 1'b0, S5_LOCK[10], //bits 15 downto 10 + 1'b0, S5_DIVCLK[9], S5_DIVCLK[1], 1'b0, S5_DIVCLK[6], 1'b0, S5_DIVCLK[3], //bits 9 downto 3 + 1'b0, S5_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[110] = {5'h17, 16'hFFD0, 10'h000, S5_LOCK[17], 1'b0, S5_LOCK[8], S5_LOCK[9], S5_LOCK[23], S5_LOCK[22]}; //bits 15 downto 0 + + rom[111] = {5'h18, 16'h1039, S5_DIGITAL_FILT[6], S5_DIGITAL_FILT[7], S5_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S5_DIGITAL_FILT[2], S5_DIGITAL_FILT[1], S5_DIGITAL_FILT[3], S5_DIGITAL_FILT[9], //bits 11 downto 8 + S5_DIGITAL_FILT[8], S5_LOCK[26], 3'h0, S5_LOCK[19], S5_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[112] = {5'h19, 16'h0000, S5_LOCK[24], S5_LOCK[25], S5_LOCK[21], S5_LOCK[14], S5_LOCK[11], //bits 15 downto 11 + S5_LOCK[12], S5_LOCK[20], S5_LOCK[6], S5_LOCK[35], S5_LOCK[36], //bits 10 downto 6 + S5_LOCK[37], S5_LOCK[3], S5_LOCK[33], S5_LOCK[31], S5_LOCK[34], S5_LOCK[30]}; //bits 5 downto 0 + + rom[113] = {5'h1A, 16'hFFFC, 14'h0000, S5_LOCK[28], S5_LOCK[29]}; //bits 15 downto 0 + + rom[114] = {5'h1D, 16'h2FFF, S5_LOCK[7], S5_LOCK[4], 1'b0, S5_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 6 Initialization + //*********************************************************************** + + rom[115] = {5'h05, 16'h50FF, S6_CLKOUT0[19], 1'b0, S6_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S6_CLKOUT0[16], S6_CLKOUT0[17], S6_CLKOUT0[15], S6_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[116] = {5'h06, 16'h010B, S6_CLKOUT1[4], S6_CLKOUT1[5], S6_CLKOUT1[3], S6_CLKOUT1[12], //bits 15 down to 12 + S6_CLKOUT1[1], S6_CLKOUT1[2], S6_CLKOUT1[19], 1'b0, S6_CLKOUT1[17], S6_CLKOUT1[16], //bits 11 down to 6 + S6_CLKOUT1[14], S6_CLKOUT1[15], 1'b0, S6_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[117] = {5'h07, 16'hE02C, 3'h0, S6_CLKOUT1[11], S6_CLKOUT1[9], S6_CLKOUT1[10], //bits 15 down to 10 + S6_CLKOUT1[8], S6_CLKOUT1[7], S6_CLKOUT1[6], S6_CLKOUT1[20], 1'b0, S6_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S6_CLKOUT1[21], S6_CLKOUT1[22]}; //bits 3 down to 0 + + rom[118] = {5'h08, 16'h4001, S6_CLKOUT2[22], 1'b0, S6_CLKOUT2[5], S6_CLKOUT2[21], //bits 15 downto 12 + S6_CLKOUT2[12], S6_CLKOUT2[4], S6_CLKOUT2[3], S6_CLKOUT2[2], S6_CLKOUT2[0], S6_CLKOUT2[19], //bits 11 down to 6 + S6_CLKOUT2[17], S6_CLKOUT2[18], S6_CLKOUT2[15], S6_CLKOUT2[16], S6_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[119] = {5'h09, 16'h0D03, S6_CLKOUT3[14], S6_CLKOUT3[15], S6_CLKOUT0[21], S6_CLKOUT0[22], 2'h0, S6_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S6_CLKOUT2[9], S6_CLKOUT2[8], S6_CLKOUT2[6], S6_CLKOUT2[7], S6_CLKOUT2[13], S6_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[120] = {5'h0A, 16'hB001, 1'b0, S6_CLKOUT3[13], 2'h0, S6_CLKOUT3[21], S6_CLKOUT3[22], S6_CLKOUT3[5], S6_CLKOUT3[4], //bits 15 downto 8 + S6_CLKOUT3[12], S6_CLKOUT3[2], S6_CLKOUT3[0], S6_CLKOUT3[1], S6_CLKOUT3[18], S6_CLKOUT3[19], //bits 7 downto 2 + S6_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[121] = {5'h0B, 16'h0110, S6_CLKOUT0[5], S6_CLKOUT4[19], S6_CLKOUT4[14], S6_CLKOUT4[17], //bits 15 downto 12 + S6_CLKOUT4[15], S6_CLKOUT4[16], S6_CLKOUT0[4], 1'b0, S6_CLKOUT3[11], S6_CLKOUT3[10], //bits 11 downto 6 + S6_CLKOUT3[9], 1'b0, S6_CLKOUT3[7], S6_CLKOUT3[8], S6_CLKOUT3[20], S6_CLKOUT3[6]}; //bits 5 downto 0 + + rom[122] = {5'h0C, 16'h0B00, S6_CLKOUT4[7], S6_CLKOUT4[8], S6_CLKOUT4[20], S6_CLKOUT4[6], 1'b0, S6_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S6_CLKOUT4[22], S6_CLKOUT4[21], S6_CLKOUT4[4], S6_CLKOUT4[5], S6_CLKOUT4[3], //bits 9 downto 3 + S6_CLKOUT4[12], S6_CLKOUT4[1], S6_CLKOUT4[2]}; //bits 2 downto 0 + + rom[123] = {5'h0D, 16'h0008, S6_CLKOUT5[2], S6_CLKOUT5[3], S6_CLKOUT5[0], S6_CLKOUT5[1], S6_CLKOUT5[18], //bits 15 downto 11 + S6_CLKOUT5[19], S6_CLKOUT5[17], S6_CLKOUT5[16], S6_CLKOUT5[15], S6_CLKOUT0[3], //bits 10 downto 6 + S6_CLKOUT0[0], S6_CLKOUT0[2], 1'b0, S6_CLKOUT4[11], S6_CLKOUT4[9], S6_CLKOUT4[10]}; //bits 5 downto 0 + + rom[124] = {5'h0E, 16'h00D0, S6_CLKOUT5[10], S6_CLKOUT5[11], S6_CLKOUT5[8], S6_CLKOUT5[9], S6_CLKOUT5[6], //bits 15 downto 11 + S6_CLKOUT5[7], S6_CLKOUT5[20], S6_CLKOUT5[13], 2'h0, S6_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S6_CLKOUT5[5], S6_CLKOUT5[21], S6_CLKOUT5[12], S6_CLKOUT5[4]}; //bits 3 downto 0 + + rom[125] = {5'h0F, 16'h0003, S6_CLKFBOUT[4], S6_CLKFBOUT[5], S6_CLKFBOUT[3], S6_CLKFBOUT[12], S6_CLKFBOUT[1], //bits 15 downto 11 + S6_CLKFBOUT[2], S6_CLKFBOUT[0], S6_CLKFBOUT[19], S6_CLKFBOUT[18], S6_CLKFBOUT[17], //bits 10 downto 6 + S6_CLKFBOUT[15], S6_CLKFBOUT[16], S6_CLKOUT0[12], S6_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[126] = {5'h10, 16'h800C, 1'b0, S6_CLKOUT0[9], S6_CLKOUT0[11], S6_CLKOUT0[10], S6_CLKFBOUT[10], S6_CLKFBOUT[11], //bits 15 downto 10 + S6_CLKFBOUT[9], S6_CLKFBOUT[8], S6_CLKFBOUT[7], S6_CLKFBOUT[6], S6_CLKFBOUT[13], //bits 9 downto 5 + S6_CLKFBOUT[20], 2'h0, S6_CLKFBOUT[21], S6_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[127] = {5'h11, 16'hFC00, 6'h00, S6_CLKOUT3[3], S6_CLKOUT3[16], S6_CLKOUT2[11], S6_CLKOUT2[1], S6_CLKOUT1[18], //bits 15 downto 6 + S6_CLKOUT1[0], S6_CLKOUT0[6], S6_CLKOUT0[20], S6_CLKOUT0[8], S6_CLKOUT0[7]}; //bits 5 downto 0 + + rom[128] = {5'h12, 16'hF0FF, 4'h0, S6_CLKOUT5[14], S6_CLKFBOUT[14], S6_CLKOUT4[0], S6_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[129] = {5'h13, 16'h5120, S6_DIVCLK[11], 1'b0, S6_DIVCLK[10], 1'b0, S6_DIVCLK[7], S6_DIVCLK[8], //bits 15 downto 10 + S6_DIVCLK[0], 1'b0, S6_DIVCLK[5], S6_DIVCLK[2], 1'b0, S6_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[130] = {5'h14, 16'h2FFF, S6_LOCK[1], S6_LOCK[2], 1'b0, S6_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[131] = {5'h15, 16'hBFF4, 1'b0, S6_DIVCLK[12], 10'h000, S6_LOCK[38], 1'b0, S6_LOCK[32], S6_LOCK[39]}; //bits 15 downto 0 + + rom[132] = {5'h16, 16'h0A55, S6_LOCK[15], S6_LOCK[13], S6_LOCK[27], S6_LOCK[16], 1'b0, S6_LOCK[10], //bits 15 downto 10 + 1'b0, S6_DIVCLK[9], S6_DIVCLK[1], 1'b0, S6_DIVCLK[6], 1'b0, S6_DIVCLK[3], //bits 9 downto 3 + 1'b0, S6_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[133] = {5'h17, 16'hFFD0, 10'h000, S6_LOCK[17], 1'b0, S6_LOCK[8], S6_LOCK[9], S6_LOCK[23], S6_LOCK[22]}; //bits 15 downto 0 + + rom[134] = {5'h18, 16'h1039, S6_DIGITAL_FILT[6], S6_DIGITAL_FILT[7], S6_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S6_DIGITAL_FILT[2], S6_DIGITAL_FILT[1], S6_DIGITAL_FILT[3], S6_DIGITAL_FILT[9], //bits 11 downto 8 + S6_DIGITAL_FILT[8], S6_LOCK[26], 3'h0, S6_LOCK[19], S6_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[135] = {5'h19, 16'h0000, S6_LOCK[24], S6_LOCK[25], S6_LOCK[21], S6_LOCK[14], S6_LOCK[11], //bits 15 downto 11 + S6_LOCK[12], S6_LOCK[20], S6_LOCK[6], S6_LOCK[35], S6_LOCK[36], //bits 10 downto 6 + S6_LOCK[37], S6_LOCK[3], S6_LOCK[33], S6_LOCK[31], S6_LOCK[34], S6_LOCK[30]}; //bits 5 downto 0 + + rom[136] = {5'h1A, 16'hFFFC, 14'h0000, S6_LOCK[28], S6_LOCK[29]}; //bits 15 downto 0 + + rom[137] = {5'h1D, 16'h2FFF, S6_LOCK[7], S6_LOCK[4], 1'b0, S6_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 7 Initialization + //*********************************************************************** + + rom[138] = {5'h05, 16'h50FF, S7_CLKOUT0[19], 1'b0, S7_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S7_CLKOUT0[16], S7_CLKOUT0[17], S7_CLKOUT0[15], S7_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[139] = {5'h06, 16'h010B, S7_CLKOUT1[4], S7_CLKOUT1[5], S7_CLKOUT1[3], S7_CLKOUT1[12], //bits 15 down to 12 + S7_CLKOUT1[1], S7_CLKOUT1[2], S7_CLKOUT1[19], 1'b0, S7_CLKOUT1[17], S7_CLKOUT1[16], //bits 11 down to 6 + S7_CLKOUT1[14], S7_CLKOUT1[15], 1'b0, S7_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[140] = {5'h07, 16'hE02C, 3'h0, S7_CLKOUT1[11], S7_CLKOUT1[9], S7_CLKOUT1[10], //bits 15 down to 10 + S7_CLKOUT1[8], S7_CLKOUT1[7], S7_CLKOUT1[6], S7_CLKOUT1[20], 1'b0, S7_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S7_CLKOUT1[21], S7_CLKOUT1[22]}; //bits 3 down to 0 + + rom[141] = {5'h08, 16'h4001, S7_CLKOUT2[22], 1'b0, S7_CLKOUT2[5], S7_CLKOUT2[21], //bits 15 downto 12 + S7_CLKOUT2[12], S7_CLKOUT2[4], S7_CLKOUT2[3], S7_CLKOUT2[2], S7_CLKOUT2[0], S7_CLKOUT2[19], //bits 11 down to 6 + S7_CLKOUT2[17], S7_CLKOUT2[18], S7_CLKOUT2[15], S7_CLKOUT2[16], S7_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[142] = {5'h09, 16'h0D03, S7_CLKOUT3[14], S7_CLKOUT3[15], S7_CLKOUT0[21], S7_CLKOUT0[22], 2'h0, S7_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S7_CLKOUT2[9], S7_CLKOUT2[8], S7_CLKOUT2[6], S7_CLKOUT2[7], S7_CLKOUT2[13], S7_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[143] = {5'h0A, 16'hB001, 1'b0, S7_CLKOUT3[13], 2'h0, S7_CLKOUT3[21], S7_CLKOUT3[22], S7_CLKOUT3[5], S7_CLKOUT3[4], //bits 15 downto 8 + S7_CLKOUT3[12], S7_CLKOUT3[2], S7_CLKOUT3[0], S7_CLKOUT3[1], S7_CLKOUT3[18], S7_CLKOUT3[19], //bits 7 downto 2 + S7_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[144] = {5'h0B, 16'h0110, S7_CLKOUT0[5], S7_CLKOUT4[19], S7_CLKOUT4[14], S7_CLKOUT4[17], //bits 15 downto 12 + S7_CLKOUT4[15], S7_CLKOUT4[16], S7_CLKOUT0[4], 1'b0, S7_CLKOUT3[11], S7_CLKOUT3[10], //bits 11 downto 6 + S7_CLKOUT3[9], 1'b0, S7_CLKOUT3[7], S7_CLKOUT3[8], S7_CLKOUT3[20], S7_CLKOUT3[6]}; //bits 5 downto 0 + + rom[145] = {5'h0C, 16'h0B00, S7_CLKOUT4[7], S7_CLKOUT4[8], S7_CLKOUT4[20], S7_CLKOUT4[6], 1'b0, S7_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S7_CLKOUT4[22], S7_CLKOUT4[21], S7_CLKOUT4[4], S7_CLKOUT4[5], S7_CLKOUT4[3], //bits 9 downto 3 + S7_CLKOUT4[12], S7_CLKOUT4[1], S7_CLKOUT4[2]}; //bits 2 downto 0 + + rom[146] = {5'h0D, 16'h0008, S7_CLKOUT5[2], S7_CLKOUT5[3], S7_CLKOUT5[0], S7_CLKOUT5[1], S7_CLKOUT5[18], //bits 15 downto 11 + S7_CLKOUT5[19], S7_CLKOUT5[17], S7_CLKOUT5[16], S7_CLKOUT5[15], S7_CLKOUT0[3], //bits 10 downto 6 + S7_CLKOUT0[0], S7_CLKOUT0[2], 1'b0, S7_CLKOUT4[11], S7_CLKOUT4[9], S7_CLKOUT4[10]}; //bits 5 downto 0 + + rom[147] = {5'h0E, 16'h00D0, S7_CLKOUT5[10], S7_CLKOUT5[11], S7_CLKOUT5[8], S7_CLKOUT5[9], S7_CLKOUT5[6], //bits 15 downto 11 + S7_CLKOUT5[7], S7_CLKOUT5[20], S7_CLKOUT5[13], 2'h0, S7_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S7_CLKOUT5[5], S7_CLKOUT5[21], S7_CLKOUT5[12], S7_CLKOUT5[4]}; //bits 3 downto 0 + + rom[148] = {5'h0F, 16'h0003, S7_CLKFBOUT[4], S7_CLKFBOUT[5], S7_CLKFBOUT[3], S7_CLKFBOUT[12], S7_CLKFBOUT[1], //bits 15 downto 11 + S7_CLKFBOUT[2], S7_CLKFBOUT[0], S7_CLKFBOUT[19], S7_CLKFBOUT[18], S7_CLKFBOUT[17], //bits 10 downto 6 + S7_CLKFBOUT[15], S7_CLKFBOUT[16], S7_CLKOUT0[12], S7_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[149] = {5'h10, 16'h800C, 1'b0, S7_CLKOUT0[9], S7_CLKOUT0[11], S7_CLKOUT0[10], S7_CLKFBOUT[10], S7_CLKFBOUT[11], //bits 15 downto 10 + S7_CLKFBOUT[9], S7_CLKFBOUT[8], S7_CLKFBOUT[7], S7_CLKFBOUT[6], S7_CLKFBOUT[13], //bits 9 downto 5 + S7_CLKFBOUT[20], 2'h0, S7_CLKFBOUT[21], S7_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[150] = {5'h11, 16'hFC00, 6'h00, S7_CLKOUT3[3], S7_CLKOUT3[16], S7_CLKOUT2[11], S7_CLKOUT2[1], S7_CLKOUT1[18], //bits 15 downto 6 + S7_CLKOUT1[0], S7_CLKOUT0[6], S7_CLKOUT0[20], S7_CLKOUT0[8], S7_CLKOUT0[7]}; //bits 5 downto 0 + + rom[151] = {5'h12, 16'hF0FF, 4'h0, S7_CLKOUT5[14], S7_CLKFBOUT[14], S7_CLKOUT4[0], S7_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[152] = {5'h13, 16'h5120, S7_DIVCLK[11], 1'b0, S7_DIVCLK[10], 1'b0, S7_DIVCLK[7], S7_DIVCLK[8], //bits 15 downto 10 + S7_DIVCLK[0], 1'b0, S7_DIVCLK[5], S7_DIVCLK[2], 1'b0, S7_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[153] = {5'h14, 16'h2FFF, S7_LOCK[1], S7_LOCK[2], 1'b0, S7_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[154] = {5'h15, 16'hBFF4, 1'b0, S7_DIVCLK[12], 10'h000, S7_LOCK[38], 1'b0, S7_LOCK[32], S7_LOCK[39]}; //bits 15 downto 0 + + rom[155] = {5'h16, 16'h0A55, S7_LOCK[15], S7_LOCK[13], S7_LOCK[27], S7_LOCK[16], 1'b0, S7_LOCK[10], //bits 15 downto 10 + 1'b0, S7_DIVCLK[9], S7_DIVCLK[1], 1'b0, S7_DIVCLK[6], 1'b0, S7_DIVCLK[3], //bits 9 downto 3 + 1'b0, S7_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[156] = {5'h17, 16'hFFD0, 10'h000, S7_LOCK[17], 1'b0, S7_LOCK[8], S7_LOCK[9], S7_LOCK[23], S7_LOCK[22]}; //bits 15 downto 0 + + rom[157] = {5'h18, 16'h1039, S7_DIGITAL_FILT[6], S7_DIGITAL_FILT[7], S7_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S7_DIGITAL_FILT[2], S7_DIGITAL_FILT[1], S7_DIGITAL_FILT[3], S7_DIGITAL_FILT[9], //bits 11 downto 8 + S7_DIGITAL_FILT[8], S7_LOCK[26], 3'h0, S7_LOCK[19], S7_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[158] = {5'h19, 16'h0000, S7_LOCK[24], S7_LOCK[25], S7_LOCK[21], S7_LOCK[14], S7_LOCK[11], //bits 15 downto 11 + S7_LOCK[12], S7_LOCK[20], S7_LOCK[6], S7_LOCK[35], S7_LOCK[36], //bits 10 downto 6 + S7_LOCK[37], S7_LOCK[3], S7_LOCK[33], S7_LOCK[31], S7_LOCK[34], S7_LOCK[30]}; //bits 5 downto 0 + + rom[159] = {5'h1A, 16'hFFFC, 14'h0000, S7_LOCK[28], S7_LOCK[29]}; //bits 15 downto 0 + + rom[160] = {5'h1D, 16'h2FFF, S7_LOCK[7], S7_LOCK[4], 1'b0, S7_LOCK[5], 12'h000}; //bits 15 downto 0 + + //*********************************************************************** + // State 8 Initialization + //*********************************************************************** + + rom[161] = {5'h05, 16'h50FF, S8_CLKOUT0[19], 1'b0, S8_CLKOUT0[18], 1'b0,//bits 15 down to 12 + S8_CLKOUT0[16], S8_CLKOUT0[17], S8_CLKOUT0[15], S8_CLKOUT0[14], 8'h00};//bits 11 downto 0 + + rom[162] = {5'h06, 16'h010B, S8_CLKOUT1[4], S8_CLKOUT1[5], S8_CLKOUT1[3], S8_CLKOUT1[12], //bits 15 down to 12 + S8_CLKOUT1[1], S8_CLKOUT1[2], S8_CLKOUT1[19], 1'b0, S8_CLKOUT1[17], S8_CLKOUT1[16], //bits 11 down to 6 + S8_CLKOUT1[14], S8_CLKOUT1[15], 1'b0, S8_CLKOUT0[13], 2'h0}; //bits 5 down to 0 + + rom[163] = {5'h07, 16'hE02C, 3'h0, S8_CLKOUT1[11], S8_CLKOUT1[9], S8_CLKOUT1[10], //bits 15 down to 10 + S8_CLKOUT1[8], S8_CLKOUT1[7], S8_CLKOUT1[6], S8_CLKOUT1[20], 1'b0, S8_CLKOUT1[13], //bits 9 down to 4 + 2'b00, S8_CLKOUT1[21], S8_CLKOUT1[22]}; //bits 3 down to 0 + + rom[164] = {5'h08, 16'h4001, S8_CLKOUT2[22], 1'b0, S8_CLKOUT2[5], S8_CLKOUT2[21], //bits 15 downto 12 + S8_CLKOUT2[12], S8_CLKOUT2[4], S8_CLKOUT2[3], S8_CLKOUT2[2], S8_CLKOUT2[0], S8_CLKOUT2[19], //bits 11 down to 6 + S8_CLKOUT2[17], S8_CLKOUT2[18], S8_CLKOUT2[15], S8_CLKOUT2[16], S8_CLKOUT2[14], 1'b0}; //bits 5 down to 0 + + rom[165] = {5'h09, 16'h0D03, S8_CLKOUT3[14], S8_CLKOUT3[15], S8_CLKOUT0[21], S8_CLKOUT0[22], 2'h0, S8_CLKOUT2[10], 1'b0, //bits 15 downto 8 + S8_CLKOUT2[9], S8_CLKOUT2[8], S8_CLKOUT2[6], S8_CLKOUT2[7], S8_CLKOUT2[13], S8_CLKOUT2[20], 2'h0}; //bits 7 downto 0 + + rom[166] = {5'h0A, 16'hB001, 1'b0, S8_CLKOUT3[13], 2'h0, S8_CLKOUT3[21], S8_CLKOUT3[22], S8_CLKOUT3[5], S8_CLKOUT3[4], //bits 15 downto 8 + S8_CLKOUT3[12], S8_CLKOUT3[2], S8_CLKOUT3[0], S8_CLKOUT3[1], S8_CLKOUT3[18], S8_CLKOUT3[19], //bits 7 downto 2 + S8_CLKOUT3[17], 1'b0}; //bits 1 downto 0 + + rom[167] = {5'h0B, 16'h0110, S8_CLKOUT0[5], S8_CLKOUT4[19], S8_CLKOUT4[14], S8_CLKOUT4[17], //bits 15 downto 12 + S8_CLKOUT4[15], S8_CLKOUT4[16], S8_CLKOUT0[4], 1'b0, S8_CLKOUT3[11], S8_CLKOUT3[10], //bits 11 downto 6 + S8_CLKOUT3[9], 1'b0, S8_CLKOUT3[7], S8_CLKOUT3[8], S8_CLKOUT3[20], S8_CLKOUT3[6]}; //bits 5 downto 0 + + rom[168] = {5'h0C, 16'h0B00, S8_CLKOUT4[7], S8_CLKOUT4[8], S8_CLKOUT4[20], S8_CLKOUT4[6], 1'b0, S8_CLKOUT4[13], //bits 15 downto 10 + 2'h0, S8_CLKOUT4[22], S8_CLKOUT4[21], S8_CLKOUT4[4], S8_CLKOUT4[5], S8_CLKOUT4[3], //bits 9 downto 3 + S8_CLKOUT4[12], S8_CLKOUT4[1], S8_CLKOUT4[2]}; //bits 2 downto 0 + + rom[169] = {5'h0D, 16'h0008, S8_CLKOUT5[2], S8_CLKOUT5[3], S8_CLKOUT5[0], S8_CLKOUT5[1], S8_CLKOUT5[18], //bits 15 downto 11 + S8_CLKOUT5[19], S8_CLKOUT5[17], S8_CLKOUT5[16], S8_CLKOUT5[15], S8_CLKOUT0[3], //bits 10 downto 6 + S8_CLKOUT0[0], S8_CLKOUT0[2], 1'b0, S8_CLKOUT4[11], S8_CLKOUT4[9], S8_CLKOUT4[10]}; //bits 5 downto 0 + + rom[170] = {5'h0E, 16'h00D0, S8_CLKOUT5[10], S8_CLKOUT5[11], S8_CLKOUT5[8], S8_CLKOUT5[9], S8_CLKOUT5[6], //bits 15 downto 11 + S8_CLKOUT5[7], S8_CLKOUT5[20], S8_CLKOUT5[13], 2'h0, S8_CLKOUT5[22], 1'b0, //bits 10 downto 4 + S8_CLKOUT5[5], S8_CLKOUT5[21], S8_CLKOUT5[12], S8_CLKOUT5[4]}; //bits 3 downto 0 + + rom[171] = {5'h0F, 16'h0003, S8_CLKFBOUT[4], S8_CLKFBOUT[5], S8_CLKFBOUT[3], S8_CLKFBOUT[12], S8_CLKFBOUT[1], //bits 15 downto 11 + S8_CLKFBOUT[2], S8_CLKFBOUT[0], S8_CLKFBOUT[19], S8_CLKFBOUT[18], S8_CLKFBOUT[17], //bits 10 downto 6 + S8_CLKFBOUT[15], S8_CLKFBOUT[16], S8_CLKOUT0[12], S8_CLKOUT0[1], 2'b00}; //bits 5 downto 0 + + rom[172] = {5'h10, 16'h800C, 1'b0, S8_CLKOUT0[9], S8_CLKOUT0[11], S8_CLKOUT0[10], S8_CLKFBOUT[10], S8_CLKFBOUT[11], //bits 15 downto 10 + S8_CLKFBOUT[9], S8_CLKFBOUT[8], S8_CLKFBOUT[7], S8_CLKFBOUT[6], S8_CLKFBOUT[13], //bits 9 downto 5 + S8_CLKFBOUT[20], 2'h0, S8_CLKFBOUT[21], S8_CLKFBOUT[22]}; //bits 4 downto 0 + + rom[173] = {5'h11, 16'hFC00, 6'h00, S8_CLKOUT3[3], S8_CLKOUT3[16], S8_CLKOUT2[11], S8_CLKOUT2[1], S8_CLKOUT1[18], //bits 15 downto 6 + S8_CLKOUT1[0], S8_CLKOUT0[6], S8_CLKOUT0[20], S8_CLKOUT0[8], S8_CLKOUT0[7]}; //bits 5 downto 0 + + rom[174] = {5'h12, 16'hF0FF, 4'h0, S8_CLKOUT5[14], S8_CLKFBOUT[14], S8_CLKOUT4[0], S8_CLKOUT4[18], 8'h00}; //bits 15 downto 0 + + rom[175] = {5'h13, 16'h5120, S8_DIVCLK[11], 1'b0, S8_DIVCLK[10], 1'b0, S8_DIVCLK[7], S8_DIVCLK[8], //bits 15 downto 10 + S8_DIVCLK[0], 1'b0, S8_DIVCLK[5], S8_DIVCLK[2], 1'b0, S8_DIVCLK[13], 4'h0}; //bits 9 downto 0 + + rom[176] = {5'h14, 16'h2FFF, S8_LOCK[1], S8_LOCK[2], 1'b0, S8_LOCK[0], 12'h000}; //bits 15 downto 0 + + rom[177] = {5'h15, 16'hBFF4, 1'b0, S8_DIVCLK[12], 10'h000, S8_LOCK[38], 1'b0, S8_LOCK[32], S8_LOCK[39]}; //bits 15 downto 0 + + rom[178] = {5'h16, 16'h0A55, S8_LOCK[15], S8_LOCK[13], S8_LOCK[27], S8_LOCK[16], 1'b0, S8_LOCK[10], //bits 15 downto 10 + 1'b0, S8_DIVCLK[9], S8_DIVCLK[1], 1'b0, S8_DIVCLK[6], 1'b0, S8_DIVCLK[3], //bits 9 downto 3 + 1'b0, S8_DIVCLK[4], 1'b0}; //bits 2 downto 0 + + rom[179] = {5'h17, 16'hFFD0, 10'h000, S8_LOCK[17], 1'b0, S8_LOCK[8], S8_LOCK[9], S8_LOCK[23], S8_LOCK[22]}; //bits 15 downto 0 + + rom[180] = {5'h18, 16'h1039, S8_DIGITAL_FILT[6], S8_DIGITAL_FILT[7], S8_DIGITAL_FILT[0], 1'b0, //bits 15 downto 12 + S8_DIGITAL_FILT[2], S8_DIGITAL_FILT[1], S8_DIGITAL_FILT[3], S8_DIGITAL_FILT[9], //bits 11 downto 8 + S8_DIGITAL_FILT[8], S8_LOCK[26], 3'h0, S8_LOCK[19], S8_LOCK[18], 1'b0}; //bits 7 downto 0 + + rom[181] = {5'h19, 16'h0000, S8_LOCK[24], S8_LOCK[25], S8_LOCK[21], S8_LOCK[14], S8_LOCK[11], //bits 15 downto 11 + S8_LOCK[12], S8_LOCK[20], S8_LOCK[6], S8_LOCK[35], S8_LOCK[36], //bits 10 downto 6 + S8_LOCK[37], S8_LOCK[3], S8_LOCK[33], S8_LOCK[31], S8_LOCK[34], S8_LOCK[30]}; //bits 5 downto 0 + + rom[182] = {5'h1A, 16'hFFFC, 14'h0000, S8_LOCK[28], S8_LOCK[29]}; //bits 15 downto 0 + + rom[183] = {5'h1D, 16'h2FFF, S8_LOCK[7], S8_LOCK[4], 1'b0, S8_LOCK[5], 12'h000}; //bits 15 downto 0 + + // Initialize the rest of the ROM +// for(ii = 46; ii < 64; ii = ii +1) begin +// rom[ii] = 0; +// end + end + + // Output the initialized rom value based on rom_addr each clock cycle + always @(posedge SCLK) begin + rom_do<= #TCQ rom[rom_addr]; + end + + //************************************************************************** + // Everything below is associated whith the state machine that is used to + // Read/Modify/Write to the PLL. + //************************************************************************** + + // State sync + reg [3:0] current_state = RESTART; + reg [3:0] next_state = RESTART; + + // State Definitions + localparam RESTART = 4'h1; + localparam WAIT_LOCK = 4'h2; + localparam WAIT_SEN = 4'h3; + localparam ADDRESS = 4'h4; + localparam WAIT_A_DRDY = 4'h5; + localparam BITMASK = 4'h6; + localparam BITSET = 4'h7; + localparam WRITE = 4'h8; + localparam WAIT_DRDY = 4'h9; + + // These variables are used to keep track of the number of iterations that + // each state takes to reconfigure + // STATE_COUNT_CONST is used to reset the counters and should match the + // number of registers necessary to reconfigure each state. + localparam STATE_COUNT_CONST = 23; + reg [4:0] state_count = STATE_COUNT_CONST; + reg [4:0] next_state_count = STATE_COUNT_CONST; + + // This block assigns the next register value from the state machine below + always @(posedge SCLK) begin + DADDR <= #TCQ next_daddr; + DWE <= #TCQ next_dwe; + DEN <= #TCQ next_den; + RST_PLL <= #TCQ next_rst_pll; + DI <= #TCQ next_di; + + SRDY <= #TCQ next_srdy; + + rom_addr <= #TCQ next_rom_addr; + state_count <= #TCQ next_state_count; + end + + // This block assigns the next state, reset is syncronous. + always @(posedge SCLK) begin + if(RST) begin + current_state <= #TCQ RESTART; + end else begin + current_state <= #TCQ next_state; + end + end + + always @* begin + // Setup the default values + next_srdy = 1'b0; + next_daddr = DADDR; + next_dwe = 1'b0; + next_den = 1'b0; + next_rst_pll = RST_PLL; + next_di = DI; + next_rom_addr = rom_addr; + next_state_count = state_count; + + case (current_state) + // If RST is asserted reset the machine + RESTART: begin + next_daddr = 5'h00; + next_di = 16'h0000; + next_rom_addr = 8'h00; + next_rst_pll = 1'b1; + next_state = WAIT_LOCK; + end + + // Waits for the PLL to assert LOCKED - once it does asserts SRDY + WAIT_LOCK: begin + // Make sure reset is de-asserted + next_rst_pll = 1'b0; + // Reset the number of registers left to write for the next + // reconfiguration event. + next_state_count = STATE_COUNT_CONST; + + if(LOCKED) begin + // PLL is locked, go on to wait for the SEN signal + next_state = WAIT_SEN; + // Assert SRDY to indicate that the reconfiguration module is + // ready + next_srdy = 1'b1; + end else begin + // Keep waiting, locked has not asserted yet + next_state = WAIT_LOCK; + end + end + + // Wait for the next SEN pulse and set the ROM addr appropriately + // based on SADDR + WAIT_SEN: begin + if(SEN) begin + // SEN was asserted + case (SADDR) + 3'd0 : next_rom_addr = STATE_COUNT_CONST * 0; + 3'd1 : next_rom_addr = STATE_COUNT_CONST * 1; + 3'd2 : next_rom_addr = STATE_COUNT_CONST * 2; + 3'd3 : next_rom_addr = STATE_COUNT_CONST * 3; + 3'd4 : next_rom_addr = STATE_COUNT_CONST * 4; + 3'd5 : next_rom_addr = STATE_COUNT_CONST * 5; + 3'd6 : next_rom_addr = STATE_COUNT_CONST * 6; + 3'd7 : next_rom_addr = STATE_COUNT_CONST * 7; + default : next_rom_addr = STATE_COUNT_CONST * 0; + endcase + // Go on to address the PLL + next_state = ADDRESS; + end else begin + // Keep waiting for SEN to be asserted + next_state = WAIT_SEN; + end + end + + // Set the address on the PLL and assert DEN to read the value + ADDRESS: begin + // Reset the DCM through the reconfiguration + next_rst_pll = 1'b1; + // Enable a read from the PLL and set the PLL address + next_den = 1'b1; + next_daddr = rom_do[36:32]; + + // Wait for the data to be ready + next_state = WAIT_A_DRDY; + end + + // Wait for DRDY to assert after addressing the PLL + WAIT_A_DRDY: begin + if(DRDY) begin + // Data is ready, mask out the bits to save + next_state = BITMASK; + end else begin + // Keep waiting till data is ready + next_state = WAIT_A_DRDY; + end + end + + // Zero out the bits that are not set in the mask stored in rom + BITMASK: begin + // Do the mask + next_di = rom_do[31:16] & DO; + // Go on to set the bits + next_state = BITSET; + end + + // After the input is masked, OR the bits with calculated value in rom + BITSET: begin + // Set the bits that need to be assigned + next_di = rom_do[15:0] | DI; + // Set the next address to read from ROM + next_rom_addr = rom_addr + 1'b1; + // Go on to write the data to the PLL + next_state = WRITE; + end + + // DI is setup so assert DWE, DEN, and RST_PLL. Subtract one from the + // state count and go to wait for DRDY. + WRITE: begin + // Set WE and EN on PLL + next_dwe = 1'b1; + next_den = 1'b1; + + // Decrement the number of registers left to write + next_state_count = state_count - 1'b1; + // Wait for the write to complete + next_state = WAIT_DRDY; + end + + // Wait for DRDY to assert from the PLL. If the state count is not 0 + // jump to ADDRESS (continue reconfiguration). If state count is + // 0 wait for lock. + WAIT_DRDY: begin + if(DRDY) begin + // Write is complete + if(state_count > 0) begin + // If there are more registers to write keep going + next_state = ADDRESS; + end else begin + // There are no more registers to write so wait for the PLL + // to lock + next_state = WAIT_LOCK; + end + end else begin + // Keep waiting for write to complete + next_state = WAIT_DRDY; + end + end + + // If in an unknown state reset the machine + default: begin + next_state = RESTART; + end + endcase + end + +endmodule diff --git a/cores/Spectrum/pll_drp_func.h b/cores/Spectrum/pll_drp_func.h new file mode 100644 index 0000000..2184f32 --- /dev/null +++ b/cores/Spectrum/pll_drp_func.h @@ -0,0 +1,641 @@ +//***************************************************************************** +// Company: Xilinx +// Engineer: Karl Kurbjun and Carl Ribbing +// Design Name: PLL DRP +// Module Name: pll_drp_func.h +// Project Name: +// Target Devices: Virtex 5 and Spartan 6 Family +// Tool versions: L.50 (lin) +// Description: This header provides the functions necessary to calculate +// the DRP register values for the V5 PLL +//***************************************************************************** + +// Define debug to provide extra messages durring elaboration +//`define DEBUG 1 + +// FRAC_PRECISION describes the width of the fractional portion of the fixed +// point numbers. +`define FRAC_PRECISION 10 +// FIXED_WIDTH describes the total size for fixed point calculations(int+frac). +// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs +// greater than 32 +`define FIXED_WIDTH 32 + +// This function takes a fixed point number and rounds it to the nearest +// fractional precision bit. +function [`FIXED_WIDTH:1] round_frac + ( + // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number + input [`FIXED_WIDTH:1] decimal, + + // This describes the precision of the fraction, for example a value + // of 1 would modify the fractional so that instead of being a .16 + // fractional, it would be a .1 (rounded to the nearest 0.5 in turn) + input [`FIXED_WIDTH:1] precision + ); + + begin + +`ifdef DEBUG + $display("round_frac - decimal: %h, precision: %h", decimal, precision); +`endif + // If the fractional precision bit is high then round up + if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin + round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision)); + end else begin + round_frac = decimal; + end +`ifdef DEBUG + $display("round_frac: %h", round_frac); +`endif + end +endfunction + +// This function calculates high_time, low_time, w_edge, and no_count +// of a non-fractional counter based on the divide and duty cycle +// +// NOTE: high_time and low_time are returned as integers between 0 and 63 +// inclusive. 64 should equal 6'b000000 (in other words it is okay to +// ignore the overflow) +function [13:0] pll_divider + ( + input [7:0] divide, // Max divide is 128 + input [31:0] duty_cycle // Duty cycle is multiplied by 100,000 + ); + + reg [`FIXED_WIDTH:1] duty_cycle_fix; + + // High/Low time is initially calculated with a wider integer to prevent a + // calculation error when it overflows to 64. + reg [6:0] high_time; + reg [6:0] low_time; + reg w_edge; + reg no_count; + + reg [`FIXED_WIDTH:1] temp; + + begin + // Duty Cycle must be between 0 and 1,000 + if(duty_cycle <=0 || duty_cycle >= 100000) begin + $display("ERROR: duty_cycle: %f is invalid", duty_cycle); + $finish; + end + + // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point + duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000; + +`ifdef DEBUG + $display("duty_cycle_fix: %h", duty_cycle_fix); +`endif + + // If the divide is 1 nothing needs to be set except the no_count bit. + // Other values are dummies + if(divide == 7'h01) begin + high_time = 7'h01; + w_edge = 1'b0; + low_time = 7'h01; + no_count = 1'b1; + end else begin + temp = round_frac(duty_cycle_fix*divide, 1); + + // comes from above round_frac + high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; + // If the duty cycle * divide rounded is .5 or greater then this bit + // is set. + w_edge = temp[`FRAC_PRECISION]; // comes from round_frac + + // If the high time comes out to 0, it needs to be set to at least 1 + // and w_edge set to 0 + if(high_time == 7'h00) begin + high_time = 7'h01; + w_edge = 1'b0; + end + + if(high_time == divide) begin + high_time = divide - 1; + w_edge = 1'b1; + end + + // Calculate low_time based on the divide setting and set no_count to + // 0 as it is only used when divide is 1. + low_time = divide - high_time; + no_count = 1'b0; + end + + // Set the return value. + pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]}; + end +endfunction + +// This function calculates delay_time and phase_mux based on the divide and +// phase +function [16:0] pll_phase + ( + // divide must be an integer (use fractional if not) + // assumed that divide already checked to be valid + input [7:0] divide, // Max divide is 128 + + // Phase is given in degrees (-360,000 to 360,000) + input signed [31:0] phase + ); + + reg [`FIXED_WIDTH:1] phase_in_cycles; + reg [`FIXED_WIDTH:1] phase_fixed; + reg [5:0] delay_time; + reg [2:0] phase_mux; + + reg [`FIXED_WIDTH:1] temp; + + begin +`ifdef DEBUG + $display("pll_phase-divide:%d,phase:%d", + divide, phase); +`endif + + if ((phase < -360000) || (phase > 360000)) begin + $display("ERROR: phase of $phase is not between -360000 and 360000"); + $finish; + end + + // If phase is less than 0, convert it to a positive phase shift + // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point + if(phase < 0) begin + phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000; + end else begin + phase_fixed = ( phase << `FRAC_PRECISION ) / 1000; + end + + // Put phase in terms of decimal number of vco clock cycles + phase_in_cycles = ( phase_fixed * divide ) / 360; + +`ifdef DEBUG + $display("phase_in_cycles: %h", phase_in_cycles); +`endif + + temp = round_frac(phase_in_cycles, 3); + + phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2]; + delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1]; + +`ifdef DEBUG + $display("temp: %h", temp); +`endif + + // Setup the return value + pll_phase={phase_mux, delay_time}; + end +endfunction + +// This function takes the divide value and outputs the necessary lock values +function [39:0] v5_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b00110_00110_1111101000_1111101001_0000000001, + 40'b01000_01000_1111101000_1111101001_0000000001, + 40'b01011_01011_1111101000_1111101001_0000000001, + 40'b01110_01110_1111101000_1111101001_0000000001, + 40'b10001_10001_1111101000_1111101001_0000000001, + 40'b10011_10011_1111101000_1111101001_0000000001, + 40'b10110_10110_1111101000_1111101001_0000000001, + 40'b11001_11001_1111101000_1111101001_0000000001, + 40'b11100_11100_1111101000_1111101001_0000000001, + 40'b11111_11111_1110000100_1111101001_0000000001, + 40'b11111_11111_1100111001_1111101001_0000000001, + 40'b11111_11111_1011101110_1111101001_0000000001, + 40'b11111_11111_1010111100_1111101001_0000000001, + 40'b11111_11111_1010001010_1111101001_0000000001, + 40'b11111_11111_1001110001_1111101001_0000000001, + 40'b11111_11111_1000111111_1111101001_0000000001, + 40'b11111_11111_1000100110_1111101001_0000000001, + 40'b11111_11111_1000001101_1111101001_0000000001, + 40'b11111_11111_0111110100_1111101001_0000000001, + 40'b11111_11111_0111011011_1111101001_0000000001, + 40'b11111_11111_0111000010_1111101001_0000000001, + 40'b11111_11111_0110101001_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0110010000_1111101001_0000000001, + 40'b11111_11111_0101110111_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101011110_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0101000101_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100101100_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0100010011_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001, + 40'b11111_11111_0011111010_1111101001_0000000001 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + v5_pll_lock_lookup = lookup[ ((divide-1)*40) +: 40]; + end +endfunction + +function [39:0] s6_pll_lock_lookup + ( + input [6:0] divide // Max divide is 64 + ); + + reg [2559:0] lookup; + + begin + lookup = { + // This table is composed of: + // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt + 40'b01001_00111_1111101000_1111101001_0000000001,//1 + 40'b01001_00111_1111101000_1111101001_0000000001,//2 + 40'b01101_01011_1111101000_1111101001_0000000001,//3 + 40'b10010_10000_1111101000_1111101001_0000000001,//4 + 40'b10110_10100_1111101000_1111101001_0000000001,//5 + 40'b11010_11000_1111101000_1111101001_0000000001,//6 + 40'b11111_11101_1111101000_1111101001_0000000001,//7 + 40'b11111_11101_1111101000_1111101001_0000000001,//8 + 40'b11111_11101_1111101000_1111101001_0000000001,//9 + 40'b11111_11101_1111101000_1111101001_0000000001,//10 + 40'b11111_11101_1110000100_1111101001_0000000001,//11 + 40'b11111_11101_1100111001_1111101001_0000000001,//12 + 40'b11111_11101_1011101110_1111101001_0000000001,//13 + 40'b11111_11101_1010111100_1111101001_0000000001,//14 + 40'b11111_11101_1010001010_1111101001_0000000001,//15 + 40'b11111_11101_1001110001_1111101001_0000000001,//16 + 40'b11111_11101_1000111111_1111101001_0000000001,//17 + 40'b11111_11101_1000100110_1111101001_0000000001,//18 + 40'b11111_11101_1000001101_1111101001_0000000001,//19 + 40'b11111_11101_0111110100_1111101001_0000000001,//20 + 40'b11111_11101_0111011011_1111101001_0000000001,//21 + 40'b11111_11101_0111000010_1111101001_0000000001,//22 + 40'b11111_11101_0110101001_1111101001_0000000001,//23 + 40'b11111_11101_0110010000_1111101001_0000000001,//24 + 40'b11111_11101_0110010000_1111101001_0000000001,//25 + 40'b11111_11101_0101110111_1111101001_0000000001,//26 + 40'b11111_11101_0101011110_1111101001_0000000001,//27 + 40'b11111_11101_0101011110_1111101001_0000000001,//28 + 40'b11111_11101_0101000101_1111101001_0000000001,//29 + 40'b11111_11101_0101000101_1111101001_0000000001,//30 + 40'b11111_11101_0100101100_1111101001_0000000001,//31 + 40'b11111_11101_0100101100_1111101001_0000000001,//32 + 40'b11111_11101_0100101100_1111101001_0000000001,//33 + 40'b11111_11101_0100010011_1111101001_0000000001,//34 + 40'b11111_11101_0100010011_1111101001_0000000001,//35 + 40'b11111_11101_0100010011_1111101001_0000000001,//36 + 40'b11111_11101_0011111010_1111101001_0000000001,//37 + 40'b11111_11101_0011111010_1111101001_0000000001,//38 + 40'b11111_11101_0011111010_1111101001_0000000001,//39 + 40'b11111_11101_0011111010_1111101001_0000000001,//40 + 40'b11111_11101_0011111010_1111101001_0000000001,//41 + 40'b11111_11101_0011111010_1111101001_0000000001,//42 + 40'b11111_11101_0011111010_1111101001_0000000001,//43 + 40'b11111_11101_0011111010_1111101001_0000000001,//44 + 40'b11111_11101_0011111010_1111101001_0000000001,//45 + 40'b11111_11101_0011111010_1111101001_0000000001,//46 + 40'b11111_11101_0011111010_1111101001_0000000001,//47 + 40'b11111_11101_0011111010_1111101001_0000000001,//48 + 40'b11111_11101_0011111010_1111101001_0000000001,//49 + 40'b11111_11101_0011111010_1111101001_0000000001,//50 + 40'b11111_11101_0011111010_1111101001_0000000001,//51 + 40'b11111_11101_0011111010_1111101001_0000000001,//52 + 40'b11111_11101_0011111010_1111101001_0000000001,//53 + 40'b11111_11101_0011111010_1111101001_0000000001,//54 + 40'b11111_11101_0011111010_1111101001_0000000001,//55 + 40'b11111_11101_0011111010_1111101001_0000000001,//56 + 40'b11111_11101_0011111010_1111101001_0000000001,//57 + 40'b11111_11101_0011111010_1111101001_0000000001,//58 + 40'b11111_11101_0011111010_1111101001_0000000001,//59 + 40'b11111_11101_0011111010_1111101001_0000000001,//60 + 40'b11111_11101_0011111010_1111101001_0000000001,//61 + 40'b11111_11101_0011111010_1111101001_0000000001,//62 + 40'b11111_11101_0011111010_1111101001_0000000001,//63 + 40'b11111_11101_0011111010_1111101001_0000000001//64 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + s6_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40]; + + $display("lock_lookup: %b", s6_pll_lock_lookup); + end +endfunction + +// This function takes the divide value and the bandwidth setting of the PLL +// and outputs the digital filter settings necessary. +function [9:0] v5_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup; + + reg [19:0] lookup_entry; + + begin + lookup = { + // This table is composed as: + // High bndwidth__Low bndwidth + // RES_LFHF_CP__RES_LFHF_CP + 20'b1111_00_0101__0001_11_0111, // 1 + 20'b1111_00_1111__0001_11_0101, // 2 + 20'b1101_00_1111__0001_11_1110, // 3 + 20'b1001_00_1111__0001_11_0110, // 4 + 20'b1110_00_1111__0001_11_1010, // 5 + 20'b0001_00_1111__0001_11_1100, // 6 + 20'b0001_00_1111__0001_11_1100, // 7 + 20'b0110_00_1111__0001_11_1100, // 8 + 20'b1010_00_1111__0001_11_1100, // 9 + 20'b1010_00_1111__0001_11_0010, // 10 + 20'b1010_00_1111__0001_11_0010, // 11 + 20'b1100_00_1110__0001_11_0010, // 12 + 20'b1100_00_1111__0001_11_1100, // 13 + 20'b1100_00_1111__0001_11_0100, // 14 + 20'b1100_00_1111__0001_11_0100, // 15 + 20'b1100_00_1111__0001_11_0100, // 16 + 20'b1100_00_1111__0001_11_0100, // 17 + 20'b1100_00_1111__0001_11_0100, // 18 + 20'b1100_00_1111__0001_11_0100, // 19 + 20'b1100_00_1111__0001_11_0100, // 20 + 20'b1100_00_1110__0001_11_0100, // 21 + 20'b1100_00_1110__0001_11_0100, // 22 + 20'b1100_00_1110__0001_11_0100, // 23 + 20'b1010_00_1111__0001_11_1000, // 24 + 20'b1100_00_1101__0001_11_1000, // 25 + 20'b0010_00_1100__0001_11_1000, // 26 + 20'b1100_00_1101__0001_11_1000, // 27 + 20'b1100_00_1101__0001_11_1000, // 28 + 20'b1010_00_1111__0001_11_1000, // 29 + 20'b1010_00_1111__0001_11_1000, // 30 + 20'b1010_00_1111__0001_11_1000, // 31 + 20'b0010_00_0111__0001_11_1000, // 32 + 20'b1100_00_1100__0001_11_1000, // 33 + 20'b1100_00_1100__0001_11_1000, // 34 + 20'b1010_00_1110__0001_11_1000, // 35 + 20'b0010_00_0110__0001_11_1000, // 36 + 20'b0010_00_0110__0001_11_1000, // 37 + 20'b0010_00_0110__0010_11_0100, // 38 + 20'b1100_00_0111__0010_11_0100, // 39 + 20'b0010_00_0110__0010_11_0100, // 40 + 20'b0100_00_0100__0010_11_0100, // 41 + 20'b0100_00_0100__0010_11_0100, // 42 + 20'b0100_00_0100__0010_11_0100, // 43 + 20'b0100_00_0100__0010_11_0100, // 44 + 20'b0100_00_0100__0010_11_0100, // 45 + 20'b0100_00_0100__0010_11_0100, // 46 + 20'b1000_00_0011__0010_11_0100, // 47 + 20'b1000_00_0011__0010_11_1000, // 48 + 20'b1000_00_0011__0010_11_1000, // 49 + 20'b1000_00_0011__0010_11_1000, // 50 + 20'b1000_00_0011__0010_11_1000, // 51 + 20'b1000_00_0011__0010_11_1000, // 52 + 20'b1000_00_0011__0010_11_1000, // 53 + 20'b1000_00_0011__0010_11_1000, // 54 + 20'b1000_00_0011__0010_11_1000, // 55 + 20'b1000_00_0011__0010_11_1000, // 56 + 20'b1000_00_0011__0010_11_1000, // 57 + 20'b1000_00_0011__0010_11_1000, // 58 + 20'b1000_00_0011__0010_11_1000, // 59 + 20'b1000_00_0011__0010_11_1000, // 60 + 20'b1000_00_0011__0010_11_1000, // 61 + 20'b1000_00_0011__0010_11_1000, // 62 + 20'b1000_00_0011__0010_11_1000, // 63 + 20'b1000_00_0011__0010_11_1000 // 64 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + lookup_entry = lookup[ ((divide-1)*20) +: 20]; + + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + v5_pll_filter_lookup=lookup_entry[9:0]; + end else begin + // High or optimized bandwidth + v5_pll_filter_lookup=lookup_entry[19:10]; + end + end +endfunction + +function [9:0] s6_pll_filter_lookup + ( + input [6:0] divide, // Max divide is 64 + input [8*9:0] BANDWIDTH + ); + + reg [1279:0] lookup; + + reg [19:0] lookup_entry; + + begin + lookup = { + // This table is composed as: + // High bndwidth__Low bndwidth + // RES_LFHF_CP__RES_LFHF_CP + 20'b1011_11_0010__1101_11_0001,//1 + 20'b1111_11_0101__1110_11_0001,//2 + 20'b1011_11_0110__0001_11_0001,//3 + 20'b1111_11_1110__0110_11_0001,//4 + 20'b1011_11_1110__1010_11_0001,//5 + 20'b1101_11_1110__1100_11_0001,//6 + 20'b0011_11_1111__1100_11_0001,//7 + 20'b0101_11_1111__1100_11_0001,//8 + 20'b1001_11_1111__0010_11_0001,//9 + 20'b1110_11_1110__0010_11_0001,//10 + 20'b1110_11_1111__0100_11_0001,//11 + 20'b0001_11_1111__0100_11_0001,//12 + 20'b0001_11_1111__0100_11_0001,//13 + 20'b0110_11_1110__0100_11_0001,//14 + 20'b0110_11_1110__0100_11_0001,//15 + 20'b1010_11_1110__0100_11_0001,//16 + 20'b1010_11_1110__0100_11_0001,//17 + 20'b1010_11_1111__0100_11_0001,//18 + 20'b1010_11_1111__0100_11_0001,//19 + 20'b1010_11_1111__0100_11_0001,//20 + 20'b1010_11_1111__0100_11_0001,//21 + 20'b1100_11_1101__1000_11_0001,//22 + 20'b1100_11_1101__1000_11_0001,//23 + 20'b1100_11_1110__1000_11_0001,//24 + 20'b1100_11_1110__1000_11_0001,//25 + 20'b1100_11_1111__1000_11_0001,//26 + 20'b1100_11_1111__1000_11_0001,//27 + 20'b1100_11_1111__1000_11_0001,//28 + 20'b1100_11_1111__1000_11_0001,//29 + 20'b1100_11_1111__1000_11_0001,//30 + 20'b0010_11_1110__1000_11_0001,//31 + 20'b0010_11_1110__1000_11_0001,//32 + 20'b1100_11_1111__1000_11_0001,//33 + 20'b1100_11_1111__1000_11_0001,//34 + 20'b0010_11_1101__0100_11_0010,//35 + 20'b0010_11_1101__0100_11_0010,//36 + 20'b0100_11_1111__0100_11_0010,//37 + 20'b0010_11_1100__0100_11_0010,//38 + 20'b0010_11_1100__0100_11_0010,//39 + 20'b0010_11_1100__0100_11_0010,//40 + 20'b1000_11_0100__0100_11_0010,//41 + 20'b1000_11_0100__0100_11_0010,//42 + 20'b1000_11_0100__0100_11_0010,//43 + 20'b0100_11_0101__1000_11_0010,//44 + 20'b0010_11_0111__1000_11_0010,//45 + 20'b1000_11_0011__1000_11_0010,//46 + 20'b1000_11_0011__1000_11_0010,//47 + 20'b1000_11_0011__1000_11_0010,//48 + 20'b1000_11_0011__1000_11_0010,//49 + 20'b1000_11_0011__1000_11_0010,//50 + 20'b1000_11_0011__1000_11_0010,//51 + 20'b1000_11_0011__1000_11_0010,//52 + 20'b1000_11_0011__1000_11_0010,//53 + 20'b1000_11_0011__1000_11_0010,//54 + 20'b1000_11_0011__1000_11_0010,//55 + 20'b1000_11_0011__1000_11_0010,//56 + 20'b0100_11_0011__1000_11_0010,//57 + 20'b0100_11_0011__1000_11_0010,//58 + 20'b0100_11_0011__1000_11_0010,//59 + 20'b0100_11_0011__1000_11_0010,//60 + 20'b0100_11_0011__1000_11_0010,//61 + 20'b0100_11_0011__1000_11_0010,//62 + 20'b0100_11_0011__1000_11_0010,//63 + 20'b0100_11_0011__1000_11_0010//64 + }; + + // Set lookup_entry with the explicit bits from lookup with a part select + lookup_entry = lookup[ ((64-divide)*20) +: 20]; + + if(BANDWIDTH == "LOW") begin + // Low Bandwidth + s6_pll_filter_lookup=lookup_entry[9:0]; + end else begin + // High or optimized bandwidth + s6_pll_filter_lookup=lookup_entry[19:10]; + end + + $display("filter_lookup: %b", s6_pll_filter_lookup); + end + +endfunction + +// This function takes in the divide, phase, and duty cycle settings to +// calculate the upper and lower counter registers. +function [37:0] v5_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [16:0] phase_calc; + + begin +`ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = pll_divider(divide, duty_cycle); + // pm[8:6], dt[5:0] + phase_calc = pll_phase(divide, phase); + + // Return value is the upper and lower address of counter + // Upper address is: + // RESERVED [31:24] + // EDGE [23] + // NOCOUNT [22] + // DELAY_TIME [21:16] + // Lower Address is: + // PHASE_MUX [15:13] + // RESERVED [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], phase_calc[5:0], phase_calc[8:6]); +`endif + + v5_pll_count_calc = + { + // Upper Address + 8'h00, div_calc[13:12], phase_calc[5:0], + // Lower Address + phase_calc[8:6], 1'b0, div_calc[11:0] + }; + end +endfunction + +function [22:0] s6_pll_count_calc + ( + input [7:0] divide, // Max divide is 128 + input signed [31:0] phase, + input [31:0] duty_cycle // Multiplied by 100,000 + ); + + reg [13:0] div_calc; + reg [8:0] phase_calc; + + begin +`ifdef DEBUG + $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d", + divide, phase, duty_cycle); +`endif + + // w_edge[13], no_count[12], high_time[11:6], low_time[5:0] + div_calc = pll_divider(divide, duty_cycle); + // pm[8:6], dt[5:0] + phase_calc = pll_phase(divide, phase); + + // Return value is + // PHASE_MUX [22:20] + // DELAY_TIME [19:14] + // EDGE [13] + // NOCOUNT [12] + // HIGH_TIME [11:6] + // LOW_TIME [5:0] + +`ifdef DEBUG + $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d dt:%d pm:%d", + divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], + div_calc[13], div_calc[12], phase_calc[5:0], phase_calc[8:6]); +`endif + + s6_pll_count_calc = + { + phase_calc[8:0], + div_calc[13:0] + }; + end +endfunction diff --git a/cores/Spectrum/pll_top.v b/cores/Spectrum/pll_top.v new file mode 100644 index 0000000..eb57bf1 --- /dev/null +++ b/cores/Spectrum/pll_top.v @@ -0,0 +1,353 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// Company: Xilinx +// Engineer: Karl Kurbjun and Carl Ribbing +// Date: 2/19/2009 +// Design Name: PLL DRP +// Module Name: top.v +// Version: 1.0 +// Target Devices: Spartan 6 Family +// Tool versions: L.68 (lin) +// Description: This is a basic demonstration of the PLL_DRP +// connectivity to the PLL_ADV. +// +// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR +// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING +// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY +// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +// APPLICATION OR STANDARD, XILINX IS MAKING NO +// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE +// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY +// REQUIRE FOR YOUR IMPLEMENTATION. XILINX +// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH +// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION, +// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES +// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. +// +// (c) Copyright 2008 Xilinx, Inc. +// All rights reserved. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ps/1ps +`default_nettype none + +module pll_top + ( + // SSTEP is the input to start a reconfiguration. It should only be + // pulsed for one clock cycle. + input wire SSTEP, + // STATE determines which state the PLL_ADV will be reconfigured to. A + // value of 0 correlates to state 1, and a value of 1 correlates to state + // 2. + input wire [2:0] STATE, + + // RST will reset the entire reference design including the PLL_ADV + input wire RST, + // CLKIN is the input clock that feeds the PLL_ADV CLKIN as well as the + // clock for the PLL_DRP module + input wire CLKIN, + + // SRDY pulses for one clock cycle after the PLL_ADV is locked and the + // PLL_DRP module is ready to start another re-configuration + output wire SRDY, + + // These are the clock outputs from the PLL_ADV. + output wire CLK0OUT, + output wire CLK1OUT, + output wire CLK2OUT, + output wire CLK3OUT, + output wire CLK4OUT, + output wire CLK5OUT + ); + + // These signals are used as direct connections between the PLL_ADV and the + // PLL_DRP. + wire [15:0] di; + wire [4:0] daddr; + wire [15:0] dout; + wire den; + wire dwe; + wire dclk; + wire rst_pll; + wire drdy; + wire locked; + + // These signals are used for the BUFG's necessary for the design. + wire clkin_bufgout; + + wire clkfb_bufgout; + wire clkfb_bufgin; + + wire clk0_bufgin; + wire clk0_bufgout; + + wire clk1_bufgin; + wire clk1_bufgout; + + wire clk2_bufgin; + wire clk2_bufgout; + + wire clk3_bufgin; + wire clk3_bufgout; + + wire clk4_bufgin; + wire clk4_bufgout; + + wire clk5_bufgin; + wire clk5_bufgout; + + // Global buffers used in design +// BUFG BUFG_IN ( +// .O(clkin_bufgout), +// .I(CLKIN) +// ); + assign clkin_bufgout = CLKIN; + + BUFG BUFG_FB ( + .O(clkfb_bufgout), + .I(clkfb_bufgin) + ); + + BUFG BUFG_CLK0 ( + .O(CLK0OUT), + .I(clk0_bufgin) + ); + + BUFG BUFG_CLK1 ( + .O(CLK1OUT), + .I(clk1_bufgin) + ); + + BUFG BUFG_CLK2 ( + .O(CLK2OUT), + .I(clk2_bufgin) + ); + + BUFG BUFG_CLK3 ( + .O(CLK3OUT), + .I(clk3_bufgin) + ); + + BUFG BUFG_CLK4 ( + .O(CLK4OUT), + .I(clk4_bufgin) + ); + + BUFG BUFG_CLK5 ( + .O(CLK5OUT), + .I(clk5_bufgin) + ); + +// // ODDR registers used to output clocks +// +// ODDR2 #( +// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" +// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 +// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset +// ) ODDR2_CLK0 ( +// .Q(CLK0OUT), // 1-bit DDR output data +// .C0(clk0_bufgout), // 1-bit clock input +// .C1(~clk0_bufgout), // 1-bit clock input +// .CE(1'b1), // 1-bit clock enable input +// .D0(1'b1), // 1-bit data input (associated with C0) +// .D1(1'b0), // 1-bit data input (associated with C1) +// .R(RST), // 1-bit reset input +// .S(1'b0) // 1-bit set input +// ); +// +// ODDR2 #( +// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" +// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 +// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset +// ) ODDR2_CLK1 ( +// .Q(CLK1OUT), // 1-bit DDR output data +// .C0(clk1_bufgout), // 1-bit clock input +// .C1(~clk1_bufgout), // 1-bit clock input +// .CE(1'b1), // 1-bit clock enable input +// .D0(1'b1), // 1-bit data input (associated with C0) +// .D1(1'b0), // 1-bit data input (associated with C1) +// .R(RST), // 1-bit reset input +// .S(1'b0) // 1-bit set input +// ); +// +// ODDR2 #( +// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" +// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 +// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset +// ) ODDR2_CLK2 ( +// .Q(CLK2OUT), // 1-bit DDR output data +// .C0(clk2_bufgout), // 1-bit clock input +// .C1(~clk2_bufgout), // 1-bit clock input +// .CE(1'b1), // 1-bit clock enable input +// .D0(1'b1), // 1-bit data input (associated with C0) +// .D1(1'b0), // 1-bit data input (associated with C1) +// .R(RST), // 1-bit reset input +// .S(1'b0) // 1-bit set input +// ); +// +// ODDR2 #( +// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" +// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 +// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset +// ) ODDR2_CLK3 ( +// .Q(CLK3OUT), // 1-bit DDR output data +// .C0(clk3_bufgout), // 1-bit clock input +// .C1(~clk3_bufgout), // 1-bit clock input +// .CE(1'b1), // 1-bit clock enable input +// .D0(1'b1), // 1-bit data input (associated with C0) +// .D1(1'b0), // 1-bit data input (associated with C1) +// .R(RST), // 1-bit reset input +// .S(1'b0) // 1-bit set input +// ); +// +// ODDR2 #( +// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" +// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 +// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset +// ) ODDR2_CLK4 ( +// .Q(CLK4OUT), // 1-bit DDR output data +// .C0(clk4_bufgout), // 1-bit clock input +// .C1(~clk4_bufgout), // 1-bit clock input +// .CE(1'b1), // 1-bit clock enable input +// .D0(1'b1), // 1-bit data input (associated with C0) +// .D1(1'b0), // 1-bit data input (associated with C1) +// .R(RST), // 1-bit reset input +// .S(1'b0) // 1-bit set input +// ); +// +// ODDR2 #( +// .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" +// .INIT(1'b0), // Sets initial state of the Q output to 1’b0 or 1’b1 +// .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset +// ) ODDR2_CLK5 ( +// .Q(CLK5OUT), // 1-bit DDR output data +// .C0(clk5_bufgout), // 1-bit clock input +// .C1(~clk5_bufgout), // 1-bit clock input +// .CE(1'b1), // 1-bit clock enable input +// .D0(1'b1), // 1-bit data input (associated with C0) +// .D1(1'b0), // 1-bit data input (associated with C1) +// .R(RST), // 1-bit reset input +// .S(1'b0) // 1-bit set input +// ); + + // PLL_ADV that reconfiguration will take place on + PLL_ADV #( + .SIM_DEVICE("SPARTAN6"), + .DIVCLK_DIVIDE(1), // 1 to 52 + + .BANDWIDTH("LOW"), // "HIGH", "LOW" or "OPTIMIZED" + + // CLKFBOUT stuff + .CLKFBOUT_MULT(9), + .CLKFBOUT_PHASE(0.0), + + // Set the clock period (ns) of input clocks and reference jitter + .REF_JITTER(0.100), + .CLKIN1_PERIOD(20.000), + .CLKIN2_PERIOD(20.000), + + // CLKOUT parameters: + // DIVIDE: (1 to 128) + // DUTY_CYCLE: (0.01 to 0.99) - This is dependent on the divide value. + // PHASE: (0.0 to 360.0) - This is dependent on the divide value. + .CLKOUT0_DIVIDE(16), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0.0), + + .CLKOUT1_DIVIDE(32), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0.0), + + .CLKOUT2_DIVIDE(64), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0.0), + + .CLKOUT3_DIVIDE(128), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0.0), + + .CLKOUT4_DIVIDE(128), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0.0), + + .CLKOUT5_DIVIDE(128), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0.0), + + // Set the compensation + .COMPENSATION("SYSTEM_SYNCHRONOUS"), + + // PMCD stuff (not used) + .EN_REL("FALSE"), + .PLL_PMCD_MODE("FALSE"), + .RST_DEASSERT_CLK("CLKIN1") + ) PLL_ADV_inst ( + .CLKFBDCM(), + .CLKFBOUT(clkfb_bufgin), + + // CLK outputs + .CLKOUT0(clk0_bufgin), + .CLKOUT1(clk1_bufgin), + .CLKOUT2(clk2_bufgin), + .CLKOUT3(clk3_bufgin), + .CLKOUT4(clk4_bufgin), + .CLKOUT5(clk5_bufgin), + + // CLKOUTS to DCM + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + + // DRP Ports + .DO(dout), + .DRDY(drdy), + .DADDR(daddr), + .DCLK(dclk), + .DEN(den), + .DI(di), + .DWE(dwe), + + .LOCKED(locked), + .CLKFBIN(clkfb_bufgout), + + // Clock inputs + .CLKIN1(CLKIN), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + + .REL(1'b0), + .RST(rst_pll) + ); + + // PLL_DRP instance that will perform the reconfiguration operations + pll_drp PLL_DRP_inst ( + // Top port connections + .SADDR(STATE), + .SEN(SSTEP), + .RST(RST), + .SRDY(SRDY), + + // Input from IBUFG + .SCLK(clkin_bufgout), + + // Direct connections to the PLL_ADV + .DO(dout), + .DRDY(drdy), + .LOCKED(locked), + .DWE(dwe), + .DEN(den), + .DADDR(daddr), + .DI(di), + .DCLK(dclk), + .RST_PLL(rst_pll) + ); +endmodule diff --git a/cores/Spectrum/ps2_mouse_kempston.v b/cores/Spectrum/ps2_mouse_kempston.v index 973a23e..1430300 100644 --- a/cores/Spectrum/ps2_mouse_kempston.v +++ b/cores/Spectrum/ps2_mouse_kempston.v @@ -67,7 +67,7 @@ module ps2_mouse_kempston ( assign oe_n_kmouse = kmouse_x_req_n & kmouse_y_req_n & kmouse_butt_req_n; /* - | BSY | x | x | x | ERR | RLS | EXT | PEN | + | BSY | 0 | 0 | 0 | ERR | 0 | 0 | DATA_AVL | */ reg reading_mousestatus = 1'b0; always @(posedge clk) begin diff --git a/cores/Spectrum/rom.v b/cores/Spectrum/rom.v index 2ad59db..928d078 100644 --- a/cores/Spectrum/rom.v +++ b/cores/Spectrum/rom.v @@ -24,16 +24,16 @@ module rom ( output reg [7:0] dout ); - reg [7:0] mem[0:127]; + reg [7:0] mem[0:255]; integer i; initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM - for (i=0;i<128;i=i+1) begin + for (i=0;i<256;i=i+1) begin mem[i] = 8'h00; end $readmemh ("bootloader_hex.txt", mem, 0); end always @(posedge clk) begin - dout <= mem[a[6:0]]; + dout <= mem[a[7:0]]; end endmodule diff --git a/cores/Spectrum/scancode_to_speccy.v b/cores/Spectrum/scancode_to_speccy.v index dbcf454..22f0555 100644 --- a/cores/Spectrum/scancode_to_speccy.v +++ b/cores/Spectrum/scancode_to_speccy.v @@ -144,7 +144,10 @@ module scancode_to_speccy ( row[5] <= 5'b11111; row[6] <= 5'b11111; row[7] <= 5'b11111; - state <= IDLE; + if (cpuread == 1'b1 || cpuwrite == 1'b1 || rewind == 1'b1) + state <= CPUTIME; + else + state <= IDLE; end IDLE: begin if (key_is_pending == 1'b1) begin @@ -255,7 +258,7 @@ module scancode_to_speccy ( endcase end end -endmodule +endmodule module keyboard_pressed_status ( input wire clk, @@ -272,6 +275,8 @@ module keyboard_pressed_status ( UPDATING = 2'd1, SCANNING = 2'd2; + reg keybstat_ne[0:255]; // non extended keymap + reg keybstat_ex[0:255]; // extended keymap reg [7:0] addrscan = 8'h00; // keymap bit address reg keypressed_ne = 1'b0; // there is at least one key pressed reg keypressed_ex = 1'b0; // there is at least one extended key pressed @@ -280,52 +285,12 @@ module keyboard_pressed_status ( integer i; initial begin kbclean = 1'b1; + for (i=0;i<256;i=i+1) begin + keybstat_ne[i] = 1'b0; + keybstat_ex[i] = 1'b0; + end end - reg [7:0] addrkeybstat; - reg we_key_ne, we_key_ex; - reg din_key_ne, din_key_ex; - wire dout_key_ne, dout_key_ex; - - keystatmem vector_kb_clean ( - .clk(clk), - .a(addrkeybstat), - .we1(we_key_ne), - .we2(we_key_ex), - .din1(din_key_ne), - .din2(din_key_ex), - .dout1(dout_key_ne), - .dout2(dout_key_ex) - ); - - always @* begin - addrkeybstat = 8'h00; - we_key_ne = 1'b0; - we_key_ex = 1'b0; - din_key_ne = 1'b0; - din_key_ex = 1'b0; - case (state) - RESETTING: - begin - addrkeybstat = addrscan; - we_key_ne = 1'b1; - we_key_ex = 1'b1; - end - UPDATING: - begin - addrkeybstat = scancode; - we_key_ne = ~extended; - we_key_ex = extended; - din_key_ne = ~released; - din_key_ex = ~released; - end - SCANNING: - begin - addrkeybstat = addrscan; - end - endcase - end - always @(posedge clk) begin if (rst == 1'b1) begin state <= RESETTING; @@ -341,6 +306,8 @@ module keyboard_pressed_status ( kbclean <= 1'b1; end else begin + keybstat_ne[addrscan] <= 1'b0; + keybstat_ex[addrscan] <= 1'b0; addrscan <= addrscan + 8'd1; end end @@ -351,6 +318,10 @@ module keyboard_pressed_status ( kbclean <= 1'b0; keypressed_ne <= 1'b0; keypressed_ex <= 1'b0; + if (extended == 1'b0) + keybstat_ne[scancode] <= ~released; + else + keybstat_ex[scancode] <= ~released; end SCANNING: begin @@ -363,40 +334,12 @@ module keyboard_pressed_status ( keypressed_ex <= 1'b0; end else begin - keypressed_ne <= keypressed_ne | dout_key_ne; - keypressed_ex <= keypressed_ex | dout_key_ex; + keypressed_ne <= keypressed_ne | keybstat_ne[addrscan]; + keypressed_ex <= keypressed_ex | keybstat_ex[addrscan]; end end - default: - begin - state <= SCANNING; - end endcase end end endmodule - -module keystatmem ( - input wire clk, - input wire [7:0] a, - input wire we1, - input wire we2, - input wire din1, - input wire din2, - output reg dout1, - output reg dout2 - ); - - reg keybstat_ne[0:255]; // non extended keymap - reg keybstat_ex[0:255]; // extended keymap - - always @(posedge clk) begin - if (we1 == 1'b1) - keybstat_ne[a] <= din1; - if (we2 == 1'b1) - keybstat_ex[a] <= din2; - dout1 <= keybstat_ne[a]; - dout2 <= keybstat_ex[a]; - end -endmodule - \ No newline at end of file + \ No newline at end of file diff --git a/cores/Spectrum/scandoubler_ctrl.v b/cores/Spectrum/scandoubler_ctrl.v new file mode 100644 index 0000000..6903e09 --- /dev/null +++ b/cores/Spectrum/scandoubler_ctrl.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +`default_nettype none + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01:22:53 06/15/2015 +// Design Name: +// Module Name: scratch_register +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module scandoubler_ctrl ( + input wire clk, + input wire [15:0] a, + input wire iorq_n, + input wire wr_n, + input wire [7:0] zxuno_addr, + input wire zxuno_regrd, + input wire zxuno_regwr, + input wire [7:0] din, + output reg [7:0] dout, + output wire oe_n, + output wire vga_enable, + output wire scanlines_enable, + output wire [2:0] freq_option, + output wire turbo_enable + ); + + parameter SCANDBLCTRL = 8'h0B; + parameter PRISMSPEEDCTRL = 16'h8e3b; // PRISM speed control: bits D0-D3. We use TURBO=1 if D0-D3>0 + + assign oe_n = ~(zxuno_addr == SCANDBLCTRL && zxuno_regrd == 1'b1); + + assign vga_enable = scandblctrl[0]; + assign scanlines_enable = scandblctrl[1]; + assign freq_option = scandblctrl[4:2]; + assign turbo_enable = scandblctrl[7]; + + reg [7:0] scandblctrl = 8'h00; // initial value + always @(posedge clk) begin + if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1) + scandblctrl <= din; + else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL) + scandblctrl[7] <= (din[3:0] == 4'b0000)? 1'b0 : 1'b1; + dout <= scandblctrl; + end +endmodule diff --git a/cores/Spectrum/scratch_register.v b/cores/Spectrum/scratch_register.v index acdd67c..47200ac 100644 --- a/cores/Spectrum/scratch_register.v +++ b/cores/Spectrum/scratch_register.v @@ -1,4 +1,6 @@ `timescale 1ns / 1ps +`default_nettype none + ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: diff --git a/cores/Spectrum/timings_pentagon128.png b/cores/Spectrum/timings_pentagon128.png new file mode 100644 index 0000000000000000000000000000000000000000..1921e87ab30449833edc60cc12183d0e4d3313c4 GIT binary patch literal 20113 zcmc({XIN8d7dE;Pd&4qz0TC4y0TmfQnxmr#ii|Rf)aan1LPqM=f|0g0VKOT&#L#j*V_B~ABXJc z&0aYh0DyT8`+q+I0Mo!pI~q{X4)kU_mvCc!$S{0TCi!y@+V85m`gMgP}e$F#ci#*^&YmMfBL+w z9xF~>!d&`g_TO)2{+49*)L_FKjitxe94m5bIuu?Um6VcHk_KfP+*xKWPfkgZmi2R% zRnh8&Lg7?!84SMix$5Vz26%r!2FwM&V}R-4cRN5603viFE&O-VP_KY~W^<4)XhpAK%Q; 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- wire wssclk,sysclk,clk14,clk7,clk3d5; -// relojes los_relojes_del_sistema ( -// .CLKIN_IN(clk50mhz), -// .CLKDV_OUT(wssclk), // 5MHz -// .CLKFX_OUT(sysclk), // 28MHz -// .CLKIN_IBUFG_OUT(), -// .CLK0_OUT(), -// .LOCKED_OUT() -// ); + wire wssclk,sysclk,clk14,clk7,clk3d5,cpuclk; + wire CPUContention; + wire turbo_enable; + wire [2:0] pll_frequency_option; - assign wssclk = 1'b0; // de momento, sin WSS - assign stdn = 1'b0; // fijar norma PAL - assign stdnb = 1'b1; // y conectamos reloj PAL + assign wssclk = 1'b0; // de momento, sin WSS + assign stdn = 1'b0; // fijar norma PAL + assign stdnb = 1'b1; // y conectamos reloj PAL -// pll reloj_maestro -// (// Clock in ports -// .CLK_IN1 (clk50mhz), // IN -// // Clock out ports -// .CLK_OUT1 (sysclk), // OUT -// // Dynamic reconfiguration ports -// .PROGCLK (1'b0), // IN -// .PROGDATA (1'b0), // IN -// .PROGEN (1'b0), // IN -// .PROGDONE ()); // OUT -// -// reg [2:0] divclk = 3'b000; -// always @(posedge sysclk) -// divclk <= divclk + 1; -// assign clk14 = divclk[0]; -// assign clk7 = divclk[1]; -// assign clk3d5 = divclk[2]; - - cuatro_relojes relojes_maestros + clock_generator relojes_maestros (// Clock in ports - .CLK_IN1 (clk50mhz), // IN + .CLK_IN1 (clk50mhz), + .CPUContention (CPUContention), + .pll_option (pll_frequency_option), + .turbo_enable (turbo_enable), // Clock out ports - .CLK_OUT1 (sysclk) , // OUT - .CLK_OUT2 (clk14), // OUT - .CLK_OUT3 (clk7), // OUT - .CLK_OUT4 (clk3d5)); // OUT - + .CLK_OUT1 (sysclk), + .CLK_OUT2 (clk14), + .CLK_OUT3 (clk7), + .CLK_OUT4 (clk3d5), + .cpuclk (cpuclk) + ); wire audio_out; assign audio_out_left = audio_out; assign audio_out_right = audio_out; + + wire [2:0] ri, gi, bi; + wire hsync_pal, vsync_pal; + wire vga_enable, scanlines_enable; + zxuno la_maquina ( .clk(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ahí, para el resto del circuito .wssclk(wssclk), // 5MHz, reloj para el WSS .clk14(clk14), .clk7(clk7), .clk3d5(clk3d5), + .cpuclk(cpuclk), + .CPUContention(CPUContention), .power_on_reset_n(1'b1), // sólo para simulación. Para implementacion, dejar a 1 - .r(r), - .g(g), - .b(b), - .csync(csync), + .r(ri), + .g(gi), + .b(bi), + .hsync(hsync_pal), + .vsync(vsync_pal), .clkps2(clkps2), .dataps2(dataps2), .ear(~ear), // negada porque el hardware tiene un transistor inversor @@ -141,10 +131,32 @@ module tld_zxuno ( .joyleft(joyleft), .joyright(joyright), .joyfire(joyfire), - + .mouseclk(mouseclk), - .mousedata(mousedata) + .mousedata(mousedata), + + .vga_enable(vga_enable), + .scanlines_enable(scanlines_enable), + .freq_option(pll_frequency_option), + .turbo_enable(turbo_enable) ); + + vga_scandoubler #(.CLKVIDEO(14000)) salida_vga ( + .clkvideo(clk14), + .clkvga(sysclk), + .enable_scandoubling(vga_enable), + .disable_scaneffect(~scanlines_enable), + .ri(ri), + .gi(gi), + .bi(bi), + .hsync_ext_n(hsync_pal), + .vsync_ext_n(vsync_pal), + .ro(r), + .go(g), + .bo(b), + .hsync(hsync), + .vsync(vsync) + ); assign testled = (!flash_cs_n || !sd_cs_n); // reg [21:0] monoestable = 22'hFFFFFF; @@ -156,4 +168,6 @@ module tld_zxuno ( // end // assign testled = ~monoestable[21]; + + endmodule diff --git a/cores/Spectrum/ula_radas.v b/cores/Spectrum/ula_radas.v index 64a2355..add2b97 100644 --- a/cores/Spectrum/ula_radas.v +++ b/cores/Spectrum/ula_radas.v @@ -22,42 +22,48 @@ ////////////////////////////////////////////////////////////////////////////////// module ula_radas ( - // Clocks + // Clocks input wire clk14, // 14MHz master clock input wire clk7, input wire wssclk, // 5MHz WSS clock + input wire cpuclk, + output wire CPUContention, input wire rst_n, // reset para volver al modo normal - // CPU interface - input wire [15:0] a, - input wire mreq_n, - input wire iorq_n, - input wire rd_n, - input wire wr_n, - output wire cpuclk, - output reg int_n, - input wire [7:0] din, + // CPU interface + input wire [15:0] a, + input wire mreq_n, + input wire iorq_n, + input wire rd_n, + input wire wr_n, + output wire int_n, + input wire [7:0] din, output reg [7:0] dout, - + input wire rasterint_enable, + input wire vretraceint_disable, + input wire [8:0] raster_line, + output wire raster_int_in_progress, + // VRAM interface - output reg [13:0] va, // 16KB videoram + output reg [13:0] va, // 16KB videoram input wire [7:0] vramdata, // I/O ports - input wire ear, - input wire [4:0] kbd, + input wire ear, + input wire [4:0] kbd, output reg mic, output reg spk, input wire issue2_keyboard, - input wire timming, + input wire [1:0] mode, input wire disable_contention, input wire access_to_contmem, // Video - output wire [2:0] r, - output wire [2:0] g, - output wire [2:0] b, - output wire csync, + output wire [2:0] r, + output wire [2:0] g, + output wire [2:0] b, + output wire hsync, + output wire vsync, output wire y_n ); @@ -76,14 +82,21 @@ module ula_radas ( // Counters from sync module wire [8:0] hc; wire [8:0] vc; + + // Signal when the vertical counter is in the line that we use to make the INT signal + wire in_int_line; reg clkhalf14 = 1'b0; always @(posedge clk14) clkhalf14 <= ~clkhalf14; - pal_sync_generator_sinclair syncs ( + pal_sync_generator syncs ( .clk(clk7), - .timming(timming), + .mode(mode), + .rasterint_enable(rasterint_enable), + .vretraceint_disable(vretraceint_disable), + .raster_line(raster_line), + .raster_int_in_progress(raster_int_in_progress), .ri(ri), .gi(gi), .bi(bi), @@ -92,24 +105,11 @@ module ula_radas ( .ro(r), .go(g), .bo(b), - .csync(csync) + .hsync(hsync), + .vsync(vsync), + .int_n(int_n) ); -// pal_sync_generator_progressive syncs ( -// .clk(clk7), -// .wssclk(wssclk), -// .ri(ri), -// .gi(gi), -// .bi(bi), -// .hcnt(hc), -// .vcnt(vc), -// .ro(r), -// .go(g), -// .bo(b), -// .csync(csync) -// ); - - /////////////////////////////////////////////// // ULA datapath /////////////////////////////////////////////// @@ -500,16 +500,7 @@ module ula_radas ( end end end - - // INT generation - always @* begin - if (vc==BVSYNC && hc>=2 && hc<=65) // 32 T-states INT pulse width - int_n = 1'b0; - else - int_n = 1'b1; - end - - + /////////////////////////////////// // AUXILIARY SIGNALS FOR CONTENTION CONTROL /////////////////////////////////// @@ -598,6 +589,8 @@ module ula_radas ( CancelContention <= 1'b0; end - assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0]; + //assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0]; + + assign CPUContention = (~(MayContend_n | CauseContention_n | CancelContention)); endmodule diff --git a/cores/Spectrum/vga_scandoubler.v b/cores/Spectrum/vga_scandoubler.v new file mode 100644 index 0000000..75f3c72 --- /dev/null +++ b/cores/Spectrum/vga_scandoubler.v @@ -0,0 +1,175 @@ +`timescale 1ns / 1ps +`default_nettype none + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:57:54 11/09/2015 +// Design Name: +// Module Name: vga_scandoubler +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module vga_scandoubler ( + input wire clkvideo, + input wire clkvga, + input wire enable_scandoubling, + input wire disable_scaneffect, // 1 to disable scanlines + input wire [2:0] ri, + input wire [2:0] gi, + input wire [2:0] bi, + input wire hsync_ext_n, + input wire vsync_ext_n, + output reg [2:0] ro, + output reg [2:0] go, + output reg [2:0] bo, + output reg hsync, + output reg vsync + ); + + parameter [31:0] CLKVIDEO = 12000; + + // http://www.epanorama.net/faq/vga2rgb/calc.html + // SVGA 800x600 + // HSYNC = 3.36us VSYNC = 114.32us + + parameter [63:0] HSYNC_COUNT = (CLKVIDEO * 3360 * 2)/1000000; + parameter [63:0] VSYNC_COUNT = (CLKVIDEO * 114320 * 2)/1000000; + + reg [10:0] addrvideo = 11'd0, addrvga = 11'b00000000000; + reg [9:0] totalhor = 10'd0; + + // Para generar scanlines: + wire [2:0] rout, gout, bout; + reg scaneffect = 1'b0; + wire [2:0] ro_vga = (scaneffect | disable_scaneffect)? rout : {1'b0, rout[2:1]}; + wire [2:0] go_vga = (scaneffect | disable_scaneffect)? gout : {1'b0, gout[2:1]}; + wire [2:0] bo_vga = (scaneffect | disable_scaneffect)? bout : {1'b0, bout[2:1]}; + + // Memoria de doble puerto que guarda la información de dos scans + // Cada scan puede ser de hasta 1024 puntos, incluidos aquí los + // puntos en negro que se pintan durante el HBlank + vgascanline_dport memscan ( + .clk(clkvga), + .addrwrite(addrvideo), + .addrread(addrvga), + .we(1'b1), + .din({ri,gi,bi}), + .dout({rout,gout,bout}) + ); + + // Voy alternativamente escribiendo en una mitad o en otra del scan buffer + // Cambio de mitad cada vez que encuentro un pulso de sincronismo horizontal + // En "totalhor" mido el número de ciclos de reloj que hay en un scan + always @(posedge clkvideo) begin + if (hsync_ext_n == 1'b0 && addrvideo[9:7] != 3'b000) begin + totalhor <= addrvideo[9:0]; + addrvideo <= {~addrvideo[10],10'b0000000000}; + end + else + addrvideo <= addrvideo + 11'd1; + end + + // Recorro el scanbuffer al doble de velocidad, generando direcciones para + // el scan buffer. Cada vez que el video original ha terminado una linea, + // cambio de mitad de buffer. Cuando termino de recorrerlo pero aún no + // estoy en un retrazo horizontal, simplemente vuelvo a recorrer el scan buffer + // desde el mismo origen + // Cada vez que termino de recorrer el scan buffer basculo "scaneffect" que + // uso después para mostrar los píxeles a su brillo nominal, o con su brillo + // reducido para un efecto chachi de scanlines en la VGA + always @(posedge clkvga) begin + if (hsync_ext_n == 1'b0 && addrvga[9:7] != 3'b000) begin + addrvga <= {~addrvga[10],10'b000000000}; + scaneffect <= ~scaneffect; + end + else if (addrvga[9:0] == totalhor && hsync_ext_n == 1'b1) begin + addrvga <= {addrvga[10], 10'b000000000}; + scaneffect <= ~scaneffect; + end + else + addrvga <= addrvga + 11'd1; + end + + // El HSYNC de la VGA está bajo sólo durante HSYNC_COUNT ciclos a partir del comienzo + // del barrido de un scanline + reg hsync_vga, vsync_vga; + + always @* begin + if (addrvga[9:0] < HSYNC_COUNT[9:0]) + hsync_vga = 1'b0; + else + hsync_vga = 1'b1; + end + + // El VSYNC de la VGA está bajo sólo durante VSYNC_COUNT ciclos a partir del flanco de + // bajada de la señal de sincronismo vertical original + reg [15:0] cntvsync = 16'hFFFF; + initial vsync_vga = 1'b1; + always @(posedge clkvga) begin + if (vsync_ext_n == 1'b0) begin + if (cntvsync == 16'hFFFF) begin + cntvsync <= 16'd0; + vsync_vga <= 1'b0; + end + else if (cntvsync != 16'hFFFE) begin + if (cntvsync == VSYNC_COUNT[15:0]) begin + vsync_vga <= 1'b1; + cntvsync <= 16'hFFFE; + end + else + cntvsync <= cntvsync + 16'd1; + end + end + else if (vsync_ext_n == 1'b1) + cntvsync <= 16'hFFFF; + end + + always @* begin + if (enable_scandoubling == 1'b0) begin // 15kHz output + ro = ri; + go = gi; + bo = bi; + hsync = hsync_ext_n & vsync_ext_n; + vsync = 1'b1; + end + else begin // VGA output + ro = ro_vga; + go = go_vga; + bo = bo_vga; + hsync = hsync_vga; + vsync = vsync_vga; + end + end + +endmodule + +// Una memoria de doble puerto: uno para leer, y otro para +// escribir. Es de 2048 direcciones: 1024 se emplean para +// guardar un scan, y otros 1024 para el siguiente scan +module vgascanline_dport ( + input wire clk, + input wire [10:0] addrwrite, + input wire [10:0] addrread, + input wire we, + input wire [8:0] din, + output reg [8:0] dout + ); + + reg [8:0] scan[0:2047]; // two scanlines + always @(posedge clk) begin + dout <= scan[addrread]; + if (we == 1'b1) + scan[addrwrite] <= din; + end +endmodule diff --git a/cores/Spectrum/zxuno.gise b/cores/Spectrum/zxuno.gise index 8ca6142..2774368 100644 --- a/cores/Spectrum/zxuno.gise +++ b/cores/Spectrum/zxuno.gise @@ -15,7 +15,7 @@ - + 11.1 @@ -23,67 +23,93 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - @@ -91,35 +117,74 @@ - - - + - + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cores/Spectrum/zxuno.v b/cores/Spectrum/zxuno.v index 73fd9a8..0d7ccfc 100644 --- a/cores/Spectrum/zxuno.v +++ b/cores/Spectrum/zxuno.v @@ -27,13 +27,16 @@ module zxuno ( input wire clk14, input wire clk7, input wire clk3d5, + input wire cpuclk, + output wire CPUContention, input wire power_on_reset_n, // E/S output wire [2:0] r, output wire [2:0] g, output wire [2:0] b, - output wire csync, + output wire hsync, + output wire vsync, inout wire clkps2, inout wire dataps2, input wire ear, @@ -62,10 +65,16 @@ module zxuno ( input wire joyleft, input wire joyright, input wire joyfire, - + // MOUSE inout wire mouseclk, - inout wire mousedata + inout wire mousedata, + + // SCANDOUBLER CTRL + output wire vga_enable, + output wire scanlines_enable, + output wire [2:0] freq_option, + output wire turbo_enable ); // Señales de la CPU @@ -74,7 +83,6 @@ module zxuno ( wire [15:0] cpuaddr; wire [7:0] cpudin; wire [7:0] cpudout; - wire cpuclk; wire [7:0] ula_dout; // Señales acceso RAM por parte de la ULA @@ -128,7 +136,7 @@ module zxuno ( wire [4:0] kbdcol_to_ula; // Configuración ULA - wire timming_ula; + wire [1:0] timing_mode; wire issue2_keyboard; wire disable_contention; wire access_to_screen; @@ -140,6 +148,18 @@ module zxuno ( // Scratch register wire oe_n_scratch; wire [7:0] scratch_dout; + + // Scandoubler control + wire [7:0] scndblctrl_dout; + wire oe_n_scndblctrl; + + // Raster INT control + wire rasterint_enable; + wire vretraceint_disable; + wire [8:0] raster_line; + wire raster_int_in_progress; + wire [7:0] rasterint_dout; + wire oe_n_rasterint; // NMI events wire [7:0] nmievents_dout; @@ -153,6 +173,9 @@ module zxuno ( wire [7:0] mousestatus_dout; wire oe_n_kmouse, oe_n_mousedata, oe_n_mousestatus; + // Multiboot + wire boot_second_core = user_toggles[1]; // KB triggered booting + // Asignación de dato para la CPU segun la decodificación de todos los dispositivos // conectados a ella. assign cpudin = (oe_n_romyram==1'b0)? memory_dout : @@ -165,10 +188,12 @@ module zxuno ( (oe_n_coreid==1'b0)? coreid_dout : (oe_n_keymap==1'b0)? keymap_dout : (oe_n_scratch==1'b0)? scratch_dout : + (oe_n_scndblctrl==1'b0)? scndblctrl_dout : (oe_n_nmievents==1'b0)? nmievents_dout : (oe_n_kmouse==1'b0)? kmouse_dout : (oe_n_mousedata==1'b0)? mousedata_dout : (oe_n_mousestatus==1'b0)? mousestatus_dout : + (oe_n_rasterint==1'b0)? rasterint_dout : ula_dout; tv80n_wrapper el_z80 ( @@ -197,6 +222,8 @@ module zxuno ( .clk14(clk14), // 14MHz master clock .clk7(clk7), .wssclk(wssclk), // 5MHz WSS clock + .cpuclk(cpuclk), + .CPUContention(CPUContention), .rst_n(mrst_n & rst_n & power_on_reset_n), // CPU interface @@ -206,10 +233,13 @@ module zxuno ( .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n), - .cpuclk(cpuclk), .int_n(int_n), .din(cpudout), .dout(ula_dout), + .rasterint_enable(rasterint_enable), + .vretraceint_disable(vretraceint_disable), + .raster_line(raster_line), + .raster_int_in_progress(raster_int_in_progress), // VRAM interface .va(vram_addr), // 16KB videoram @@ -217,18 +247,19 @@ module zxuno ( // I/O ports .ear(ear), - .mic(mic), - .spk(spk), + .mic(mic), + .spk(spk), .kbd(kbdcol_to_ula), - .issue2_keyboard(issue2_keyboard), - .timming(timming_ula), - .disable_contention(disable_contention), + .issue2_keyboard(issue2_keyboard), + .mode(timing_mode), + .disable_contention(disable_contention), // Video .r(r), .g(g), .b(b), - .csync(csync) + .hsync(hsync), + .vsync(vsync) ); zxunoregs addr_reg_zxuno ( @@ -248,7 +279,7 @@ module zxuno ( ); flash_and_sd cacharros_con_spi ( - .clk(clk), + .clk(clk14), .a(cpuaddr), .iorq_n(iorq_n), .rd_n(rd_n), @@ -297,7 +328,7 @@ module zxuno ( .vramaddr(vram_addr), .vramdout(vram_dout), .issue2_keyboard_enabled(issue2_keyboard), - .timming_ula(timming_ula), + .timing_mode(timing_mode), .disable_contention(disable_contention), .access_to_screen(access_to_screen), @@ -380,6 +411,38 @@ module zxuno ( .oe_n(oe_n_scratch) ); + scandoubler_ctrl control_scandoubler ( + .clk(clk), + .a(cpuaddr), + .iorq_n(iorq_n), + .wr_n(wr_n), + .zxuno_addr(zxuno_addr), + .zxuno_regrd(zxuno_regrd), + .zxuno_regwr(zxuno_regwr), + .din(cpudout), + .dout(scndblctrl_dout), + .oe_n(oe_n_scndblctrl), + .vga_enable(vga_enable), + .scanlines_enable(scanlines_enable), + .freq_option(freq_option), + .turbo_enable(turbo_enable) + ); + + rasterint_ctrl control_rasterint ( + .clk(clk), + .rst_n(rst_n & mrst_n & power_on_reset_n), + .zxuno_addr(zxuno_addr), + .zxuno_regrd(zxuno_regrd), + .zxuno_regwr(zxuno_regwr), + .din(cpudout), + .dout(rasterint_dout), + .oe_n(oe_n_rasterint), + .rasterint_enable(rasterint_enable), + .vretraceint_disable(vretraceint_disable), + .raster_line(raster_line), + .raster_int_in_progress(raster_int_in_progress) + ); + nmievents nmi_especial_de_antonio ( .clk(clk), .rst_n(rst_n & mrst_n & power_on_reset_n), @@ -421,6 +484,17 @@ module zxuno ( .oe_n_mousestatus(oe_n_mousestatus) ); + multiboot el_multiboot ( + .clk(clk), + .clk_icap(clk), + .rst_n(rst_n & mrst_n & power_on_reset_n), + .kb_boot_core(boot_second_core), + .zxuno_addr(zxuno_addr), + .zxuno_regwr(zxuno_regwr), + .din(cpudout) + ); + + /////////////////////////////////// // AY-3-8912 SOUND /////////////////////////////////// diff --git a/cores/Spectrum/zxuno.xise b/cores/Spectrum/zxuno.xise index 064fc49..b648f23 100644 --- a/cores/Spectrum/zxuno.xise +++ b/cores/Spectrum/zxuno.xise @@ -9,159 +9,179 @@ - + - + - - - - + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - + + - - + + - - - - - + + - - + + - - - - + + + + - - + + - - + + - - + + - - + + - - + + - - - - + + + + - - + + - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -174,6 +194,7 @@ + @@ -190,7 +211,7 @@ - + @@ -198,7 +219,7 @@ - + @@ -216,32 +237,35 @@ + - + - + - + + + - + - + @@ -258,7 +282,6 @@ - @@ -269,7 +292,7 @@ - + @@ -291,13 +314,15 @@ - + + + @@ -308,6 +333,7 @@ + @@ -342,7 +368,7 @@ - + @@ -357,7 +383,7 @@ - + @@ -369,7 +395,6 @@ - @@ -398,9 +423,8 @@ - + - @@ -417,7 +441,7 @@ - + @@ -440,13 +464,14 @@ - + + @@ -467,7 +492,7 @@ - + @@ -500,9 +525,7 @@ - - - + @@ -513,6 +536,7 @@ +