diff --git a/cores/Spectrum/T80.vhd b/cores/Spectrum/T80.vhd
index 6584b7a..54f7ed2 100644
--- a/cores/Spectrum/T80.vhd
+++ b/cores/Spectrum/T80.vhd
@@ -1,16 +1,3 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
 --
 -- Z80 compatible microprocessor core
 --
@@ -51,33 +38,33 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
+--	http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
 -- File history :
 --
---      0208 : First complete release
+--	0208 : First complete release
 --
---      0210 : Fixed wait and halt
+--	0210 : Fixed wait and halt
 --
---      0211 : Fixed Refresh addition and IM 1
+--	0211 : Fixed Refresh addition and IM 1
 --
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
 --
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
 --
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--	0235 : Added clock enable and IM 2 fix by Mike Johnson
 --
---      0237 : Changed 8080 I/O address output, added IntE output
+--	0237 : Changed 8080 I/O address output, added IntE output
 --
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
 --
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
 --
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
 --
---      0247 : Fixed bus req/ack cycle
+--	0247 : Fixed bus req/ack cycle
 --
 
 library IEEE;
@@ -87,8 +74,8 @@ use work.T80_Pack.all;
 
 entity T80 is
 	generic(
-		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
 		Flag_C : integer := 0;
 		Flag_N : integer := 1;
 		Flag_P : integer := 2;
@@ -99,159 +86,171 @@ entity T80 is
 		Flag_S : integer := 7
 	);
 	port(
-		RESET_n         : in  std_logic;
-		CLK_n           : in  std_logic;
-		CEN             : in  std_logic;
-		WAIT_n          : in  std_logic;
-		INT_n           : in  std_logic;
-		NMI_n           : in  std_logic;
-		BUSRQ_n         : in  std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A               : out std_logic_vector(15 downto 0);
-		DInst           : in  std_logic_vector(7 downto 0);
-		DI              : in  std_logic_vector(7 downto 0);
-		DO              : out std_logic_vector(7 downto 0);
-		MC              : out std_logic_vector(2 downto 0);
-		TS              : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		CEN			: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		IORQ		: out std_logic;
+		NoRead		: out std_logic;
+		Write		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		DInst		: in std_logic_vector(7 downto 0);
+		DI			: in std_logic_vector(7 downto 0);
+		DO			: out std_logic_vector(7 downto 0);
+		MC			: out std_logic_vector(2 downto 0);
+		TS			: out std_logic_vector(2 downto 0);
+		IntCycle_n	: out std_logic;
+		IntE		: out std_logic;
+		Stop		: out std_logic;
+		
+		SavePC      : out std_logic_vector(15 downto 0);
+		SaveINT     : out std_logic_vector(7 downto 0);
+		RestorePC   : in std_logic_vector(15 downto 0);
+		RestoreINT  : in std_logic_vector(7 downto 0);
+		
+		RestorePC_n : in std_logic
 	);
 end T80;
 
 architecture rtl of T80 is
 
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
+	constant aNone	: std_logic_vector(2 downto 0) := "111";
+	constant aBC	: std_logic_vector(2 downto 0) := "000";
+	constant aDE	: std_logic_vector(2 downto 0) := "001";
+	constant aXY	: std_logic_vector(2 downto 0) := "010";
+	constant aIOA	: std_logic_vector(2 downto 0) := "100";
+	constant aSP	: std_logic_vector(2 downto 0) := "101";
+	constant aZI	: std_logic_vector(2 downto 0) := "110";
 
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
+	-- Registers
+	signal ACC, F			: std_logic_vector(7 downto 0);
+	signal Ap, Fp			: std_logic_vector(7 downto 0);
+	signal I				: std_logic_vector(7 downto 0);
+	signal R				: unsigned(7 downto 0);
+	signal SP, PC			: unsigned(15 downto 0);
+	signal RegDIH			: std_logic_vector(7 downto 0);
+	signal RegDIL			: std_logic_vector(7 downto 0);
+	signal RegBusA			: std_logic_vector(15 downto 0);
+	signal RegBusB			: std_logic_vector(15 downto 0);
+	signal RegBusC			: std_logic_vector(15 downto 0);
+	signal RegAddrA_r		: std_logic_vector(2 downto 0);
+	signal RegAddrA			: std_logic_vector(2 downto 0);
+	signal RegAddrB_r		: std_logic_vector(2 downto 0);
+	signal RegAddrB			: std_logic_vector(2 downto 0);
+	signal RegAddrC			: std_logic_vector(2 downto 0);
+	signal RegWEH			: std_logic;
+	signal RegWEL			: std_logic;
+	signal Alternate		: std_logic;
 
 	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
+	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
+	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
+	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
+	signal RegBusA_r		: std_logic_vector(15 downto 0);
 
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
+	signal ID16				: signed(15 downto 0);
+	signal Save_Mux			: std_logic_vector(7 downto 0);
 
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
+	signal TState			: unsigned(2 downto 0);
+	signal MCycle			: std_logic_vector(2 downto 0);
+	signal IntE_FF1			: std_logic;
+	signal IntE_FF2			: std_logic;
+	signal Halt_FF			: std_logic;
+	signal BusReq_s			: std_logic;
+	signal BusAck			: std_logic;
+	signal ClkEn			: std_logic;
+	signal NMI_s			: std_logic;
+	signal INT_s			: std_logic;
+	signal IStatus			: std_logic_vector(1 downto 0);
 
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
+	signal DI_Reg			: std_logic_vector(7 downto 0);
+	signal T_Res			: std_logic;
+	signal XY_State			: std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch	: std_logic;
+	signal XY_Ind			: std_logic;
+	signal No_BTR			: std_logic;
+	signal BTR_r			: std_logic;
+	signal Auto_Wait		: std_logic;
+	signal Auto_Wait_t1		: std_logic;
+	signal Auto_Wait_t2		: std_logic;
+	signal IncDecZ			: std_logic;
 
 	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
+	signal BusB				: std_logic_vector(7 downto 0);
+	signal BusA				: std_logic_vector(7 downto 0);
+	signal ALU_Q			: std_logic_vector(7 downto 0);
+	signal F_Out			: std_logic_vector(7 downto 0);
 
 	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
+	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
+	signal Arith16_r		: std_logic;
+	signal Z16_r			: std_logic;
+	signal ALU_Op_r			: std_logic_vector(3 downto 0);
+	signal Save_ALU_r		: std_logic;
+	signal PreserveC_r		: std_logic;
+	signal MCycles			: std_logic_vector(2 downto 0);
 
 	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
+	signal MCycles_d		: std_logic_vector(2 downto 0);
+	signal TStates			: std_logic_vector(2 downto 0);
+	signal IntCycle			: std_logic;
+	signal NMICycle			: std_logic;
+	signal Inc_PC			: std_logic;
+	signal Inc_WZ			: std_logic;
+	signal IncDec_16		: std_logic_vector(3 downto 0);
+	signal Prefix			: std_logic_vector(1 downto 0);
+	signal Read_To_Acc		: std_logic;
+	signal Read_To_Reg		: std_logic;
+	signal Set_BusB_To		: std_logic_vector(3 downto 0);
+	signal Set_BusA_To		: std_logic_vector(3 downto 0);
+	signal ALU_Op			: std_logic_vector(3 downto 0);
+	signal Save_ALU			: std_logic;
+	signal PreserveC		: std_logic;
+	signal Arith16			: std_logic;
+	signal Set_Addr_To		: std_logic_vector(2 downto 0);
+	signal Jump				: std_logic;
+	signal JumpE			: std_logic;
+	signal JumpXY			: std_logic;
+	signal Call				: std_logic;
+	signal RstP				: std_logic;
+	signal LDZ				: std_logic;
+	signal LDW				: std_logic;
+	signal LDSPHL			: std_logic;
+	signal IORQ_i			: std_logic;
+	signal Special_LD		: std_logic_vector(2 downto 0);
+	signal ExchangeDH		: std_logic;
+	signal ExchangeRp		: std_logic;
+	signal ExchangeAF		: std_logic;
+	signal ExchangeRS		: std_logic;
+	signal I_DJNZ			: std_logic;
+	signal I_CPL			: std_logic;
+	signal I_CCF			: std_logic;
+	signal I_SCF			: std_logic;
+	signal I_RETN			: std_logic;
+	signal I_BT				: std_logic;
+	signal I_BC				: std_logic;
+	signal I_BTR			: std_logic;
+	signal I_RLD			: std_logic;
+	signal I_RRD			: std_logic;
+	signal I_INRC			: std_logic;
+	signal SetDI			: std_logic;
+	signal SetEI			: std_logic;
+	signal IMode			: std_logic_vector(1 downto 0);
+	signal Halt				: std_logic;
 
 begin
 
 	mcode : T80_MCode
 		generic map(
-			Mode   => Mode,
+			Mode => Mode,
 			Flag_C => Flag_C,
 			Flag_N => Flag_N,
 			Flag_P => Flag_P,
@@ -261,64 +260,62 @@ begin
 			Flag_Z => Flag_Z,
 			Flag_S => Flag_S)
 		port map(
-			IR          => IR,
-			ISet        => ISet,
-			MCycle      => MCycle,
-			F           => F,
-			NMICycle    => NMICycle,
-			IntCycle    => IntCycle,
-			XY_State    => XY_State,
-			MCycles     => MCycles_d,
-			TStates     => TStates,
-			Prefix      => Prefix,
-			Inc_PC      => Inc_PC,
-			Inc_WZ      => Inc_WZ,
-			IncDec_16   => IncDec_16,
+			IR => IR,
+			ISet => ISet,
+			MCycle => MCycle,
+			F => F,
+			NMICycle => NMICycle,
+			IntCycle => IntCycle,
+			MCycles => MCycles_d,
+			TStates => TStates,
+			Prefix => Prefix,
+			Inc_PC => Inc_PC,
+			Inc_WZ => Inc_WZ,
+			IncDec_16 => IncDec_16,
 			Read_To_Acc => Read_To_Acc,
 			Read_To_Reg => Read_To_Reg,
 			Set_BusB_To => Set_BusB_To,
 			Set_BusA_To => Set_BusA_To,
-			ALU_Op      => ALU_Op,
-			Save_ALU    => Save_ALU,
-			PreserveC   => PreserveC,
-			Arith16     => Arith16,
+			ALU_Op => ALU_Op,
+			Save_ALU => Save_ALU,
+			PreserveC => PreserveC,
+			Arith16 => Arith16,
 			Set_Addr_To => Set_Addr_To,
-			IORQ        => IORQ_i,
-			Jump        => Jump,
-			JumpE       => JumpE,
-			JumpXY      => JumpXY,
-			Call        => Call,
-			RstP        => RstP,
-			LDZ         => LDZ,
-			LDW         => LDW,
-			LDSPHL      => LDSPHL,
-			Special_LD  => Special_LD,
-			ExchangeDH  => ExchangeDH,
-			ExchangeRp  => ExchangeRp,
-			ExchangeAF  => ExchangeAF,
-			ExchangeRS  => ExchangeRS,
-			I_DJNZ      => I_DJNZ,
-			I_CPL       => I_CPL,
-			I_CCF       => I_CCF,
-			I_SCF       => I_SCF,
-			I_RETN      => I_RETN,
-			I_BT        => I_BT,
-			I_BC        => I_BC,
-			I_BTR       => I_BTR,
-			I_RLD       => I_RLD,
-			I_RRD       => I_RRD,
-			I_INRC      => I_INRC,
-			SetDI       => SetDI,
-			SetEI       => SetEI,
-			IMode       => IMode,
-			Halt        => Halt,
-			NoRead      => NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
+			IORQ => IORQ_i,
+			Jump => Jump,
+			JumpE => JumpE,
+			JumpXY => JumpXY,
+			Call => Call,
+			RstP => RstP,
+			LDZ => LDZ,
+			LDW => LDW,
+			LDSPHL => LDSPHL,
+			Special_LD => Special_LD,
+			ExchangeDH => ExchangeDH,
+			ExchangeRp => ExchangeRp,
+			ExchangeAF => ExchangeAF,
+			ExchangeRS => ExchangeRS,
+			I_DJNZ => I_DJNZ,
+			I_CPL => I_CPL,
+			I_CCF => I_CCF,
+			I_SCF => I_SCF,
+			I_RETN => I_RETN,
+			I_BT => I_BT,
+			I_BC => I_BC,
+			I_BTR => I_BTR,
+			I_RLD => I_RLD,
+			I_RRD => I_RRD,
+			I_INRC => I_INRC,
+			SetDI => SetDI,
+			SetEI => SetEI,
+			IMode => IMode,
+			Halt => Halt,
+			NoRead => NoRead,
+			Write => Write);
 
 	alu : T80_ALU
 		generic map(
-			Mode   => Mode,
+			Mode => Mode,
 			Flag_C => Flag_C,
 			Flag_N => Flag_N,
 			Flag_P => Flag_P,
@@ -329,15 +326,15 @@ begin
 			Flag_S => Flag_S)
 		port map(
 			Arith16 => Arith16_r,
-			Z16     => Z16_r,
-			ALU_Op  => ALU_Op_r,
-			IR      => IR(5 downto 0),
-			ISet    => ISet,
-			BusA    => BusA,
-			BusB    => BusB,
-			F_In    => F,
-			Q       => ALU_Q,
-			F_Out   => F_Out);
+			Z16 => Z16_r,
+			ALU_Op => ALU_Op_r,
+			IR => IR(5 downto 0),
+			ISet => ISet,
+			BusA => BusA,
+			BusB => BusB,
+			F_In => F,
+			Q => ALU_Q,
+			F_Out => F_Out);
 
 	ClkEn <= CEN and not BusAck;
 
@@ -352,41 +349,47 @@ begin
 		DI_Reg when Save_ALU_r = '0' else
 		ALU_Q;
 
-	process (RESET_n, CLK_n)
+	process (RESET_n, RestorePC_n, CLK_n)
 	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
+			
+		if CLK_n'event and CLK_n = '1' then
 
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
+			if RESET_n = '0' then
+				PC <= (others => '0');  -- Program Counter
+				A <= (others => '0');
+				TmpAddr <= (others => '0');
+				IR <= "00000000";
+				ISet <= "00";
+				XY_State <= "00";
+				IStatus <= "00";
+				MCycles <= "000";
+				DO <= "00000000";
 
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
+				ACC <= (others => '1');
+				F <= (others => '1');
+				Ap <= (others => '1');
+				Fp <= (others => '1');
+				I <= (others => '0');
+				R <= (others => '0');
+				SP <= (others => '1');
+				Alternate <= '0';
 
-		elsif CLK_n'event and CLK_n = '1' then
+				Read_To_Reg_r <= "00000";
+				F <= (others => '1');
+				Arith16_r <= '0';
+				BTR_r <= '0';
+				Z16_r <= '0';
+				ALU_Op_r <= "0000";
+				Save_ALU_r <= '0';
+				PreserveC_r <= '0';
+				XY_Ind <= '0';
 
-			if ClkEn = '1' then
+			elsif RestorePC_n = '0' then
+				PC <= unsigned( RestorePC );
+				A <= RestorePC;
+				IStatus <= RestoreInt(1 downto 0);
+				
+			elsif ClkEn = '1' then
 
 			ALU_Op_r <= "0000";
 			Save_ALU_r <= '0';
@@ -394,9 +397,7 @@ begin
 
 			MCycles <= MCycles_d;
 
-      if Mode = 3 then
-        IStatus <= "10";
-			elsif IMode /= "11" then
+			if IMode /= "11" then
 				IStatus <= IMode;
 			end if;
 
@@ -464,10 +465,10 @@ begin
 				if T_Res = '1' then
 					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
 					if Jump = '1' then
-            A(15 downto 8) <= DI_Reg;
-            A(7 downto 0) <= TmpAddr(7 downto 0);
-            PC(15 downto 8) <= unsigned(DI_Reg);
-            PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+						A(15 downto 8) <= DI_Reg;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(DI_Reg);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
 					elsif JumpXY = '1' then
 						A <= RegBusC;
 						PC <= unsigned(RegBusC);
@@ -478,10 +479,10 @@ begin
 						A <= "0000000001100110";
 						PC <= "0000000001100110";
 					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-            A(15 downto 8) <= I;
-            A(7 downto 0) <= TmpAddr(7 downto 0);
-            PC(15 downto 8) <= unsigned(I);
-            PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+						A(15 downto 8) <= I;
+						A(7 downto 0) <= TmpAddr(7 downto 0);
+						PC(15 downto 8) <= unsigned(I);
+						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
 					else
 						case Set_Addr_To is
 						when aXY =>
@@ -616,29 +617,25 @@ begin
 					when "00" =>
 						ACC <= I;
 						F(Flag_P) <= IntE_FF2;
-                  F(Flag_S) <= I(7);
-                  if I(7 downto 0) = "00000000" then
-                     F(Flag_Z) <= '1';
-                  else
-                     F(Flag_Z) <= '0';
-                  end if;
-                  F(Flag_Y) <= I(5);
-                  F(Flag_H) <= '0';
-                  F(Flag_X) <= I(3);
-                  F(Flag_N) <= '0';
+						F(Flag_S) <= I(7);
+						
+						if I = x"00" then 
+							F(Flag_Z) <= '1';
+						else
+							F(Flag_Z) <= '0';
+						end if;
+
 					when "01" =>
 						ACC <= std_logic_vector(R);
 						F(Flag_P) <= IntE_FF2;
-                  F(Flag_S) <= R(7);
-                  if R(7 downto 0) = "00000000" then
-                     F(Flag_Z) <= '1';
-                  else
-                     F(Flag_Z) <= '0';
-                  end if;
-                  F(Flag_Y) <= R(5);
-                  F(Flag_H) <= '0';
-                  F(Flag_X) <= R(3);
-                  F(Flag_N) <= '0';
+						F(Flag_S) <= R(7);
+						
+						if R = x"00" then 
+							F(Flag_Z) <= '1';
+						else
+							F(Flag_Z) <= '0';
+						end if;
+						
 					when "10" =>
 						I <= ACC;
 					when others =>
@@ -675,7 +672,7 @@ begin
 					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
 			end if;
 
-			if TState = 1 then
+			if TState = 1 and Auto_Wait_t1 = '0' then
 				DO <= BusB;
 				if I_RLD = '1' then
 					DO(3 downto 0) <= BusA(3 downto 0);
@@ -706,7 +703,7 @@ begin
 				F(Flag_P) <= IncDecZ;
 			end if;
 
-			if (TState = 1 and Save_ALU_r = '0') or
+			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
 				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
 				case Read_To_Reg_r is
 				when "10111" =>
@@ -721,9 +718,6 @@ begin
 					F <= Save_Mux;
 				when others =>
 				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
 			end if;
 
 		end if;
@@ -781,10 +775,10 @@ begin
 
 	RegAddrA <=
 			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
 			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" and XY_State /= "00" else
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) else
 			-- EX HL,DL
 			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
 			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
@@ -805,7 +799,7 @@ begin
 	begin
 		RegWEH <= '0';
 		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
+		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
 			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
 			case Read_To_Reg_r is
 			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
@@ -925,12 +919,8 @@ begin
 			when "1010" =>
 				BusA <= "00000000";
 			when others =>
-				BusA <= "--------";
+				BusB <= "--------";
 			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
 			end if;
 		end if;
 	end process;
@@ -942,15 +932,16 @@ begin
 ---------------------------------------------------------------------------
 	process (RESET_n,CLK_n)
 	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
 				RFSH_n <= '1';
-			end if;
+				
+			elsif CEN = '1' then
+				if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+					RFSH_n <= '0';
+				else
+					RFSH_n <= '1';
+				end if;
 			end if;
 		end if;
 	end process;
@@ -965,6 +956,10 @@ begin
 	IORQ <= IORQ_i;
 	Stop <= I_DJNZ;
 
+	SavePC <= std_logic_vector( PC );
+	SaveINT <= "0000" & IntE_FF2 & IntE_FF1 & IStatus when MCycle = "001" and TState = "001" and Prefix = "00" and IntCycle = '0' and NMICycle = '0' else
+			"1111" & IntE_FF2 & IntE_FF1 & IStatus;	
+	
 -------------------------------------------------------------------------
 --
 -- Syncronise inputs
@@ -973,22 +968,25 @@ begin
 	process (RESET_n, CLK_n)
 		variable OldNMI_n : std_logic;
 	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
+		if CLK_n'event and CLK_n = '1' then
+		
+			if RESET_n = '0' then
+				BusReq_s <= '0';
+				INT_s <= '0';
 				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
+				OldNMI_n := '0';
+
+			elsif CEN = '1' then
+				BusReq_s <= not BUSRQ_n;
+				INT_s <= not INT_n;
+				if NMICycle = '1' then
+					NMI_s <= '0';
+				elsif NMI_n = '0' and OldNMI_n = '1' then
+					NMI_s <= '1';
+				end if;
+				OldNMI_n := NMI_n;
 			end if;
+			
 		end if;
 	end process;
 
@@ -997,100 +995,123 @@ begin
 -- Main state machine
 --
 -------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
+	process (RESET_n, RestorePC_n, CLK_n)
 	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
+
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+				MCycle <= "001";
+				TState <= "000";
+				Pre_XY_F_M <= "000";
 				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
 				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
+				NMICycle <= '0';
+				IntCycle <= '0';
+				IntE_FF1 <= '0';
+				IntE_FF2 <= '0';
+				No_BTR <= '0';
+				Auto_Wait_t1 <= '0';
+				Auto_Wait_t2 <= '0';
+				M1_n <= '1';
+			
+			elsif RestorePC_n = '0' then
+				MCycle <= "001";
+				TState <= "001";
+				NMICycle <= '0';
+				IntCycle <= '0';
+				IntE_FF1 <= RestoreINT(2);
+				IntE_FF2 <= RestoreINT(3);
+
+				Pre_XY_F_M <= "000";
+				Halt_FF <= '0';
+				BusAck <= '0';
+				No_BTR <= '0';
+				Auto_Wait_t1 <= '0';
+				Auto_Wait_t2 <= '0';
+
+			elsif CEN = '1' then
+				if T_Res = '1' then
+					Auto_Wait_t1 <= '0';
+				else
+					Auto_Wait_t1 <= Auto_Wait or IORQ_i;
+				end if;
+				Auto_Wait_t2 <= Auto_Wait_t1;
+				No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+						(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+						(I_BTR and (not IR(4) or F(Flag_Z)));
+				if TState = 2 then
+					if SetEI = '1' then
+						IntE_FF1 <= '1';
+						IntE_FF2 <= '1';
 					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
+					if I_RETN = '1' then
+						IntE_FF1 <= IntE_FF2;
+					end if;
+				end if;
+				if TState = 3 then
+					if SetDI = '1' then
+						IntE_FF1 <= '0';
+						IntE_FF2 <= '0';
+					end if;
+				end if;
+				if IntCycle = '1' or NMICycle = '1' then
+					Halt_FF <= '0';
+				end if;
+				if MCycle = "001" and TState = 2 and Wait_n = '1' then
+					M1_n <= '1';
+				end if;
+				if BusReq_s = '1' and BusAck = '1' then
+				else
+					BusAck <= '0';
+					if TState = 2 and Wait_n = '0' then
+					elsif T_Res = '1' then
+						if Halt = '1' then
+							Halt_FF <= '1';
+						end if;
+						if BusReq_s = '1' then
+							BusAck <= '1';
 						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+							TState <= "001";
+							
+							if NextIs_XY_Fetch = '1' then
+								MCycle <= "110";
+								Pre_XY_F_M <= MCycle;
+								if IR = "00110110" and Mode = 0 then
+									Pre_XY_F_M <= "010";
+								end if;
+							elsif (MCycle = MCycles) or
+								No_BTR = '1' or
+								(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') or
+								( MCycle = "111" and MCycles= "001" and Pre_XY_F_M = "001" ) then
+								M1_n <= '0';
+								MCycle <= "001";
+								IntCycle <= '0';
+								NMICycle <= '0';
+								if NMI_s = '1' and Prefix = "00" then
+									NMICycle <= '1';
+									IntE_FF1 <= '0';
+								elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
+									IntCycle <= '1';
+									IntE_FF1 <= '0';
+									IntE_FF2 <= '0';
+								end if;
+							elsif (MCycle = "111") or
+								(MCycle = "110" and Mode = 1 and ISet /= "01") then
+								MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+							else
+								MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+							end if;
+						end if;
+					else
+						if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
+							(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
+							TState <= TState + 1;
 						end if;
 					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
 				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
+				if TState = 0 then
+					M1_n <= '0';
+				end if;
 			end if;
 		end if;
 	end process;
diff --git a/cores/Spectrum/T80_ALU.vhd b/cores/Spectrum/T80_ALU.vhd
index 95c98da..86fddce 100644
--- a/cores/Spectrum/T80_ALU.vhd
+++ b/cores/Spectrum/T80_ALU.vhd
@@ -1,13 +1,3 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
 --
 -- Z80 compatible microprocessor core
 --
@@ -48,21 +38,21 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
+--	http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
 -- File history :
 --
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
 --
---      0238 : Fixed zero flag for 16 bit SBC and ADC
+--	0238 : Fixed zero flag for 16 bit SBC and ADC
 --
---      0240 : Added GB operations
+--	0240 : Added GB operations
 --
---      0242 : Cleanup
+--	0242 : Cleanup
 --
---      0247 : Cleanup
+--	0247 : Cleanup
 --
 
 library IEEE;
@@ -82,77 +72,66 @@ entity T80_ALU is
 		Flag_S : integer := 7
 	);
 	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
+		Arith16		: in std_logic;
+		Z16			: in std_logic;
+		ALU_Op		: in std_logic_vector(3 downto 0);
+		IR			: in std_logic_vector(5 downto 0);
+		ISet		: in std_logic_vector(1 downto 0);
+		BusA		: in std_logic_vector(7 downto 0);
+		BusB		: in std_logic_vector(7 downto 0);
+		F_In		: in std_logic_vector(7 downto 0);
+		Q			: out std_logic_vector(7 downto 0);
+		F_Out		: out std_logic_vector(7 downto 0)
 	);
 end T80_ALU;
 
 architecture rtl of T80_ALU is
 
-	procedure AddSub(A        : std_logic_vector;
-					 B        : std_logic_vector;
-					 Sub      : std_logic;
-					 Carry_In : std_logic;
-			  signal Res      : out std_logic_vector;
-			  signal Carry    : out std_logic) is
-
-		variable B_i          : unsigned(A'length - 1 downto 0);
-		variable Res_i        : unsigned(A'length + 1 downto 0);
+	procedure AddSub(A : std_logic_vector;
+					B : std_logic_vector;
+					Sub : std_logic;
+					Carry_In : std_logic;
+					signal Res : out std_logic_vector;
+					signal Carry : out std_logic) is
+		variable B_i		: unsigned(A'length - 1 downto 0);
+		variable Res_i		: unsigned(A'length + 1 downto 0);
 	begin
 		if Sub = '1' then
 			B_i := not unsigned(B);
 		else
-			B_i :=     unsigned(B);
+			B_i := unsigned(B);
 		end if;
-
 		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
 		Carry <= Res_i(A'length + 1);
 		Res <= std_logic_vector(Res_i(A'length downto 1));
 	end;
 
 	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
+	signal	UseCarry		: std_logic;
+	signal	Carry7_v		: std_logic;
+	signal	Overflow_v		: std_logic;
+	signal	HalfCarry_v		: std_logic;
+	signal	Carry_v			: std_logic;
+	signal	Q_v				: std_logic_vector(7 downto 0);
 
-	signal BitMask                 : std_logic_vector(7 downto 0);
+	signal	BitMask			: std_logic_vector(7 downto 0);
 
 begin
 
 	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
+									"00000010" when "001",
+									"00000100" when "010",
+									"00001000" when "011",
+									"00010000" when "100",
+									"00100000" when "101",
+									"01000000" when "110",
+									"10000000" when others;
 
 	UseCarry <= not ALU_Op(2) and ALU_Op(0);
 	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
 	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
 	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
+	OverFlow_v <= Carry_v xor Carry7_v;
 
 	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
 		variable Q_t : std_logic_vector(7 downto 0);
@@ -197,7 +176,7 @@ begin
 			if Q_t(7 downto 0) = "00000000" then
 				F_Out(Flag_Z) <= '1';
 				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
 				end if;
 			else
 				F_Out(Flag_Z) <= '0';
@@ -368,4 +347,5 @@ begin
 		end case;
 		Q <= Q_t;
 	end process;
+
 end;
diff --git a/cores/Spectrum/T80_MCode.vhd b/cores/Spectrum/T80_MCode.vhd
index a8f5fbf..15e2816 100644
--- a/cores/Spectrum/T80_MCode.vhd
+++ b/cores/Spectrum/T80_MCode.vhd
@@ -1,14 +1,3 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
 --
 -- Z80 compatible microprocessor core
 --
@@ -49,35 +38,32 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
+--	http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
 -- File history :
 --
---      0208 : First complete release
+--	0208 : First complete release
 --
---      0211 : Fixed IM 1
+--	0211 : Fixed IM 1
 --
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
 --
---      0235 : Added IM 2 fix by Mike Johnson
+--	0235 : Added IM 2 fix by Mike Johnson
 --
---      0238 : Added NoRead signal
+--	0238 : Added NoRead signal
 --
---      0238b: Fixed instruction timing for POP and DJNZ
+--	0238b: Fixed instruction timing for POP and DJNZ
 --
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
 --
---      0242 : Fixed I/O instruction timing, cleanup
+--	0242 : Fixed I/O instruction timing, cleanup
 --
 
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
-use work.T80_Pack.all;
 
 entity T80_MCode is
 	generic(
@@ -92,66 +78,79 @@ entity T80_MCode is
 		Flag_S : integer := 7
 	);
 	port(
-		IR                              : in std_logic_vector(7 downto 0);
-		ISet                    : in std_logic_vector(1 downto 0);
-		MCycle                  : in std_logic_vector(2 downto 0);
-		F                               : in std_logic_vector(7 downto 0);
-		NMICycle                : in std_logic;
-		IntCycle                : in std_logic;
-		XY_State                : in std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To     : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
+		IR				: in std_logic_vector(7 downto 0);
+		ISet			: in std_logic_vector(1 downto 0);
+		MCycle			: in std_logic_vector(2 downto 0);
+		F				: in std_logic_vector(7 downto 0);
+		NMICycle		: in std_logic;
+		IntCycle		: in std_logic;
+		MCycles			: out std_logic_vector(2 downto 0);
+		TStates			: out std_logic_vector(2 downto 0);
+		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC			: out std_logic;
+		Inc_WZ			: out std_logic;
+		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg		: out std_logic;
+		Read_To_Acc		: out std_logic;
+		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op			: out std_logic_vector(3 downto 0);
 			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
+		Save_ALU		: out std_logic;
+		PreserveC		: out std_logic;
+		Arith16			: out std_logic;
+		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ			: out std_logic;
+		Jump			: out std_logic;
+		JumpE			: out std_logic;
+		JumpXY			: out std_logic;
+		Call			: out std_logic;
+		RstP			: out std_logic;
+		LDZ				: out std_logic;
+		LDW				: out std_logic;
+		LDSPHL			: out std_logic;
+		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH		: out std_logic;
+		ExchangeRp		: out std_logic;
+		ExchangeAF		: out std_logic;
+		ExchangeRS		: out std_logic;
+		I_DJNZ			: out std_logic;
+		I_CPL			: out std_logic;
+		I_CCF			: out std_logic;
+		I_SCF			: out std_logic;
+		I_RETN			: out std_logic;
+		I_BT			: out std_logic;
+		I_BC			: out std_logic;
+		I_BTR			: out std_logic;
+		I_RLD			: out std_logic;
+		I_RRD			: out std_logic;
+		I_INRC			: out std_logic;
+		SetDI			: out std_logic;
+		SetEI			: out std_logic;
+		IMode			: out std_logic_vector(1 downto 0);
+		Halt			: out std_logic;
+		NoRead			: out std_logic;
+		Write			: out std_logic
 	);
 end T80_MCode;
 
 architecture rtl of T80_MCode is
 
+	constant aNone	: std_logic_vector(2 downto 0) := "111";
+	constant aBC	: std_logic_vector(2 downto 0) := "000";
+	constant aDE	: std_logic_vector(2 downto 0) := "001";
+	constant aXY	: std_logic_vector(2 downto 0) := "010";
+	constant aIOA	: std_logic_vector(2 downto 0) := "100";
+	constant aSP	: std_logic_vector(2 downto 0) := "101";
+	constant aZI	: std_logic_vector(2 downto 0) := "110";
+--	constant aNone	: std_logic_vector(2 downto 0) := "000";
+--	constant aXY	: std_logic_vector(2 downto 0) := "001";
+--	constant aIOA	: std_logic_vector(2 downto 0) := "010";
+--	constant aSP	: std_logic_vector(2 downto 0) := "011";
+--	constant aBC	: std_logic_vector(2 downto 0) := "100";
+--	constant aDE	: std_logic_vector(2 downto 0) := "101";
+--	constant aZI	: std_logic_vector(2 downto 0) := "110";
+
 	function is_cc_true(
 		F : std_logic_vector(7 downto 0);
 		cc : bit_vector(2 downto 0)
@@ -245,14 +244,13 @@ begin
 		Halt <= '0';
 		NoRead <= '0';
 		Write <= '0';
-		XYbit_undoc <= '0';
 
 		case ISet is
 		when "00" =>
 
 ------------------------------------------------------------------------------
 --
---      Unprefixed instructions
+--	Unprefixed instructions
 --
 ------------------------------------------------------------------------------
 
@@ -617,7 +615,7 @@ begin
 				when 3 =>
 					Jump <= '1';
 					IncDec_16 <= "0111";
-					--I_RETN <= '1';
+					I_RETN <= '1';
 					SetEI <= '1';
 				when others => null;
 				end case;
@@ -807,11 +805,7 @@ begin
 				end case;
 			elsif IntCycle = '1' then
 				-- INT (IM 2)
-        if mode = 3 then
-          MCycles <= "011";
-        else
-          MCycles <= "101";
-        end if;
+				MCycles <= "101";
 				case to_integer(unsigned(MCycle)) is
 				when 1 =>
 					LDZ <= '1';
@@ -820,13 +814,13 @@ begin
 					Set_Addr_To <= aSP;
 					Set_BusB_To <= "1101";
 				when 2 =>
-					TStates <= "100";
+					--TStates <= "100";
 					Write <= '1';
 					IncDec_16 <= "1111";
 					Set_Addr_To <= aSP;
 					Set_BusB_To <= "1100";
 				when 3 =>
-					TStates <= "100";
+					--TStates <= "100";
 					Write <= '1';
 				when 4 =>
 					Inc_PC <= '1';
@@ -930,7 +924,7 @@ begin
 					case to_integer(unsigned(MCycle)) is
 					when 1 =>
 						Set_Addr_To <= aBC;
-						Set_BusB_To <= "0111";
+						Set_BusB_To	<= "0111";
 					when 2 =>
 						Write <= '1';
 						IORQ <= '1';
@@ -1163,6 +1157,7 @@ begin
 			MCycles <= "011";
 			case to_integer(unsigned(MCycle)) is
 			when 1 =>
+				--TStates <= "101";
 				Set_Addr_TO <= aSP;
 			when 2 =>
 				IncDec_16 <= "0111";
@@ -1183,7 +1178,7 @@ begin
 					when 2 =>
 						Inc_PC <= '1';
 						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
+						Set_BusB_To	<= "0111";
 					when 3 =>
 						Write <= '1';
 					when others => null;
@@ -1205,7 +1200,7 @@ begin
 						Save_ALU <= '1';
 						ALU_Op <= "0001";
 						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
 					when others =>
 					end case;
 				when "10" =>
@@ -1220,7 +1215,7 @@ begin
 					when others => null;
 					end case;
 				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
+					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
 					MCycles <= "101";
 					case to_integer(unsigned(MCycle)) is
 					when 2 =>
@@ -1294,7 +1289,6 @@ begin
 				when 3 =>
 					Read_To_Acc <= '1';
 					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
 				when others => null;
 				end case;
 			end if;
@@ -1306,11 +1300,10 @@ begin
 				when 2 =>
 					Inc_PC <= '1';
 					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
+					Set_BusB_To	<= "0111";
 				when 3 =>
 					Write <= '1';
 					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
 				when others => null;
 				end case;
 			end if;
@@ -1342,7 +1335,7 @@ begin
 
 ------------------------------------------------------------------------------
 --
---      CB prefixed instructions
+--	CB prefixed instructions
 --
 ------------------------------------------------------------------------------
 
@@ -1366,32 +1359,11 @@ begin
 				-- SRA r
 				-- SRL r
 				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
+				if MCycle = "001" or MCycle = "111" then
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
 				end if;
-
-
 			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
 				-- RLC (HL)
 				-- RL (HL)
@@ -1424,34 +1396,20 @@ begin
 				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
 				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
 				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
+				if MCycle = "001" or MCycle = "111" then
+					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+					ALU_Op <= "1001";
 				end if;
 			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
 				-- BIT b,(HL)
 				MCycles <= "010";
 				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
+				when 1 | 7 =>
 					Set_Addr_To <= aXY;
 				when 2 =>
 					ALU_Op <= "1001";
 					TStates <= "100";
-				when others => null;
+				when others =>
 				end case;
 			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
 				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
@@ -1462,35 +1420,34 @@ begin
 				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
 				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
 				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
+				if MCycle = "001" then
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
 				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
+					MCycles <= "100";
 					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
+					when 7 =>
 						Set_Addr_To <= aXY;
 					when 2 =>
+						Set_BusB_To(2 downto 0) <= "110";
 						ALU_Op <= "1010";
 						Read_To_Reg <= '1';
 						Save_ALU <= '1';
 						Set_Addr_To <= aXY;
 						TStates <= "100";
 					when 3 =>
+						Set_Addr_To <= aXY;
+					when 4 =>
 						Write <= '1';
-					when others => null;
+					when others =>
 					end case;
 				end if;
 			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
 				-- SET b,(HL)
 				MCycles <= "011";
 				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
+				when 1 | 7 =>
 					Set_Addr_To <= aXY;
 				when 2 =>
 					ALU_Op <= "1010";
@@ -1500,7 +1457,7 @@ begin
 					TStates <= "100";
 				when 3 =>
 					Write <= '1';
-				when others => null;
+				when others =>
 				end case;
 			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
 				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
@@ -1511,31 +1468,29 @@ begin
 				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
 				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
 				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
+				if MCycle = "001" then
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
 				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
+					MCycles <= "100";
 					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
+					when 7 =>
 						Set_Addr_To <= aXY;
 					when 2 =>
+						Set_BusB_To(2 downto 0) <= "110";
 						ALU_Op <= "1011";
 						Read_To_Reg <= '1';
 						Save_ALU <= '1';
 						Set_Addr_To <= aXY;
 						TStates <= "100";
 					when 3 =>
+						Set_Addr_To <= aXY;
+					when 4 =>
 						Write <= '1';
-					when others => null;
+					when others =>
 					end case;
 				end if;
-				
 			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
 				-- RES b,(HL)
 				MCycles <= "011";
@@ -1550,7 +1505,7 @@ begin
 					TStates <= "100";
 				when 3 =>
 					Write <= '1';
-				when others => null;
+				when others =>
 				end case;
 			end case;
 
@@ -1558,7 +1513,7 @@ begin
 
 ------------------------------------------------------------------------------
 --
---      ED prefixed instructions
+--	ED prefixed instructions
 --
 ------------------------------------------------------------------------------
 
@@ -1877,7 +1832,6 @@ begin
 				when 1 =>
 					Set_Addr_To <= aBC;
 				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
 					IORQ <= '1';
 					if IR(5 downto 3) /= "110" then
 						Read_To_Reg <= '1';
@@ -1893,22 +1847,21 @@ begin
 				case to_integer(unsigned(MCycle)) is
 				when 1 =>
 					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
+					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
 					if IR(5 downto 3) = "110" then
 						Set_BusB_To(3) <= '1';
 					end if;
 				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
 					Write <= '1';
 					IORQ <= '1';
 				when others =>
 				end case;
 			when "10100010" | "10101010" | "10110010" | "10111010" =>
 				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
 				MCycles <= "100";
 				case to_integer(unsigned(MCycle)) is
 				when 1 =>
+                    TStates <= "101";
 					Set_Addr_To <= aBC;
 					Set_BusB_To <= "1010";
 					Set_BusA_To <= "0000";
@@ -1916,19 +1869,16 @@ begin
 					Save_ALU <= '1';
 					ALU_Op <= "0010";
 				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
 					IORQ <= '1';
 					Set_BusB_To <= "0110";
 					Set_Addr_To <= aXY;
 				when 3 =>
 					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
 						IncDec_16 <= "0110";
 					else
-						--IncDec_16 <= "1010";
 						IncDec_16 <= "1110";
 					end if;
-					TStates <= "100";
+					TStates <= "011";  -- "100"
 					Write <= '1';
 					I_BTR <= '1';
 				when 4 =>
@@ -1938,8 +1888,6 @@ begin
 				end case;
 			when "10100011" | "10101011" | "10110011" | "10111011" =>
 				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
 				MCycles <= "100";
 				case to_integer(unsigned(MCycle)) is
 				when 1 =>
@@ -1955,11 +1903,10 @@ begin
 					Set_Addr_To <= aBC;
 				when 3 =>
 					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
+						IncDec_16 <= "0110";
 					else
-						IncDec_16 <= "1110"; -- mikej
+						IncDec_16 <= "1110";
 					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
 					IORQ <= '1';
 					Write <= '1';
 					I_BTR <= '1';
@@ -1974,7 +1921,7 @@ begin
 
 		if Mode = 1 then
 			if MCycle = "001" then
---              TStates <= "100";
+--				TStates <= "100";
 			else
 				TStates <= "011";
 			end if;
@@ -1982,7 +1929,7 @@ begin
 
 		if Mode = 3 then
 			if MCycle = "001" then
---              TStates <= "100";
+--				TStates <= "100";
 			else
 				TStates <= "100";
 			end if;
diff --git a/cores/Spectrum/T80_Pack.vhd b/cores/Spectrum/T80_Pack.vhd
index 907db40..d1b11e1 100644
--- a/cores/Spectrum/T80_Pack.vhd
+++ b/cores/Spectrum/T80_Pack.vhd
@@ -1,13 +1,3 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
 --
 -- Z80 compatible microprocessor core
 --
@@ -48,7 +38,7 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
+--	http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
@@ -60,18 +50,10 @@ use IEEE.std_logic_1164.all;
 
 package T80_Pack is
 
-	constant aNone      : std_logic_vector(2 downto 0) := "111";
-	constant aBC        : std_logic_vector(2 downto 0) := "000";
-	constant aDE        : std_logic_vector(2 downto 0) := "001";
-	constant aXY        : std_logic_vector(2 downto 0) := "010";
-	constant aIOA       : std_logic_vector(2 downto 0) := "100";
-	constant aSP        : std_logic_vector(2 downto 0) := "101";
-	constant aZI        : std_logic_vector(2 downto 0) := "110";
-
 	component T80
 	generic(
-		Mode : integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
 		Flag_C : integer := 0;
 		Flag_N : integer := 1;
 		Flag_P : integer := 2;
@@ -82,55 +64,62 @@ package T80_Pack is
 		Flag_S : integer := 7
 	);
 	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		CEN                     : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		IORQ            : out std_logic;
-		NoRead          : out std_logic;
-		Write           : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		DInst           : in std_logic_vector(7 downto 0);
-		DI                      : in std_logic_vector(7 downto 0);
-		DO                      : out std_logic_vector(7 downto 0);
-		MC                      : out std_logic_vector(2 downto 0);
-		TS                      : out std_logic_vector(2 downto 0);
-		IntCycle_n      : out std_logic;
-		IntE            : out std_logic;
-		Stop            : out std_logic
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		CEN			: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		IORQ		: out std_logic;
+		NoRead		: out std_logic;
+		Write		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		DInst		: in std_logic_vector(7 downto 0);
+		DI			: in std_logic_vector(7 downto 0);
+		DO			: out std_logic_vector(7 downto 0);
+		MC			: out std_logic_vector(2 downto 0);
+		TS			: out std_logic_vector(2 downto 0);
+		IntCycle_n	: out std_logic;
+		IntE		: out std_logic;
+		Stop		: out std_logic;
+
+		SavePC      : out std_logic_vector(15 downto 0);
+		SaveINT     : out std_logic_vector(7 downto 0);
+		RestorePC   : in std_logic_vector(15 downto 0);
+		RestoreINT  : in std_logic_vector(7 downto 0);
+		
+		RestorePC_n : in std_logic
 	);
 	end component;
 
 	component T80_Reg
 	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
 	);
 	end component;
 
 	component T80_MCode
 	generic(
-		Mode   : integer := 0;
+		Mode : integer := 0;
 		Flag_C : integer := 0;
 		Flag_N : integer := 1;
 		Flag_P : integer := 2;
@@ -141,67 +130,65 @@ package T80_Pack is
 		Flag_S : integer := 7
 	);
 	port(
-		IR                      : in  std_logic_vector(7 downto 0);
-		ISet                    : in  std_logic_vector(1 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		F                       : in  std_logic_vector(7 downto 0);
-		NMICycle                : in  std_logic;
-		IntCycle                : in  std_logic;
-		XY_State                : in  std_logic_vector(1 downto 0);
-		MCycles                 : out std_logic_vector(2 downto 0);
-		TStates                 : out std_logic_vector(2 downto 0);
-		Prefix                  : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC                  : out std_logic;
-		Inc_WZ                  : out std_logic;
-		IncDec_16               : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg             : out std_logic;
-		Read_To_Acc             : out std_logic;
-		Set_BusA_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To             : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op                  : out std_logic_vector(3 downto 0);
+		IR				: in std_logic_vector(7 downto 0);
+		ISet			: in std_logic_vector(1 downto 0);
+		MCycle			: in std_logic_vector(2 downto 0);
+		F				: in std_logic_vector(7 downto 0);
+		NMICycle		: in std_logic;
+		IntCycle		: in std_logic;
+		MCycles			: out std_logic_vector(2 downto 0);
+		TStates			: out std_logic_vector(2 downto 0);
+		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC			: out std_logic;
+		Inc_WZ			: out std_logic;
+		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg		: out std_logic;
+		Read_To_Acc		: out std_logic;
+		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op			: out std_logic_vector(3 downto 0);
 			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU                : out std_logic;
-		PreserveC               : out std_logic;
-		Arith16                 : out std_logic;
-		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ                    : out std_logic;
-		Jump                    : out std_logic;
-		JumpE                   : out std_logic;
-		JumpXY                  : out std_logic;
-		Call                    : out std_logic;
-		RstP                    : out std_logic;
-		LDZ                     : out std_logic;
-		LDW                     : out std_logic;
-		LDSPHL                  : out std_logic;
-		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH              : out std_logic;
-		ExchangeRp              : out std_logic;
-		ExchangeAF              : out std_logic;
-		ExchangeRS              : out std_logic;
-		I_DJNZ                  : out std_logic;
-		I_CPL                   : out std_logic;
-		I_CCF                   : out std_logic;
-		I_SCF                   : out std_logic;
-		I_RETN                  : out std_logic;
-		I_BT                    : out std_logic;
-		I_BC                    : out std_logic;
-		I_BTR                   : out std_logic;
-		I_RLD                   : out std_logic;
-		I_RRD                   : out std_logic;
-		I_INRC                  : out std_logic;
-		SetDI                   : out std_logic;
-		SetEI                   : out std_logic;
-		IMode                   : out std_logic_vector(1 downto 0);
-		Halt                    : out std_logic;
-		NoRead                  : out std_logic;
-		Write                   : out std_logic;
-		XYbit_undoc             : out std_logic
+		Save_ALU		: out std_logic;
+		PreserveC		: out std_logic;
+		Arith16			: out std_logic;
+		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ			: out std_logic;
+		Jump			: out std_logic;
+		JumpE			: out std_logic;
+		JumpXY			: out std_logic;
+		Call			: out std_logic;
+		RstP			: out std_logic;
+		LDZ				: out std_logic;
+		LDW				: out std_logic;
+		LDSPHL			: out std_logic;
+		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH		: out std_logic;
+		ExchangeRp		: out std_logic;
+		ExchangeAF		: out std_logic;
+		ExchangeRS		: out std_logic;
+		I_DJNZ			: out std_logic;
+		I_CPL			: out std_logic;
+		I_CCF			: out std_logic;
+		I_SCF			: out std_logic;
+		I_RETN			: out std_logic;
+		I_BT			: out std_logic;
+		I_BC			: out std_logic;
+		I_BTR			: out std_logic;
+		I_RLD			: out std_logic;
+		I_RRD			: out std_logic;
+		I_INRC			: out std_logic;
+		SetDI			: out std_logic;
+		SetEI			: out std_logic;
+		IMode			: out std_logic_vector(1 downto 0);
+		Halt			: out std_logic;
+		NoRead			: out std_logic;
+		Write			: out std_logic
 	);
 	end component;
 
 	component T80_ALU
 	generic(
-		Mode   : integer := 0;
+		Mode : integer := 0;
 		Flag_C : integer := 0;
 		Flag_N : integer := 1;
 		Flag_P : integer := 2;
@@ -212,16 +199,16 @@ package T80_Pack is
 		Flag_S : integer := 7
 	);
 	port(
-		Arith16         : in  std_logic;
-		Z16             : in  std_logic;
-		ALU_Op          : in  std_logic_vector(3 downto 0);
-		IR              : in  std_logic_vector(5 downto 0);
-		ISet            : in  std_logic_vector(1 downto 0);
-		BusA            : in  std_logic_vector(7 downto 0);
-		BusB            : in  std_logic_vector(7 downto 0);
-		F_In            : in  std_logic_vector(7 downto 0);
-		Q               : out std_logic_vector(7 downto 0);
-		F_Out           : out std_logic_vector(7 downto 0)
+		Arith16		: in std_logic;
+		Z16			: in std_logic;
+		ALU_Op		: in std_logic_vector(3 downto 0);
+		IR			: in std_logic_vector(5 downto 0);
+		ISet		: in std_logic_vector(1 downto 0);
+		BusA		: in std_logic_vector(7 downto 0);
+		BusB		: in std_logic_vector(7 downto 0);
+		F_In		: in std_logic_vector(7 downto 0);
+		Q			: out std_logic_vector(7 downto 0);
+		F_Out		: out std_logic_vector(7 downto 0)
 	);
 	end component;
 
diff --git a/cores/Spectrum/T80_Reg.vhd b/cores/Spectrum/T80_Reg.vhd
index 1c0f263..828485f 100644
--- a/cores/Spectrum/T80_Reg.vhd
+++ b/cores/Spectrum/T80_Reg.vhd
@@ -1,12 +1,3 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
 --
 -- T80 Registers, technology independent
 --
@@ -47,15 +38,15 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t51/
+--	http://www.opencores.org/cvsweb.shtml/t51/
 --
 -- Limitations :
 --
 -- File history :
 --
---      0242 : Initial release
+--	0242 : Initial release
 --
---      0244 : Changed to single register file
+--	0244 : Changed to single register file
 --
 
 library IEEE;
@@ -64,29 +55,29 @@ use IEEE.numeric_std.all;
 
 entity T80_Reg is
 	port(
-		Clk                     : in std_logic;
-		CEN                     : in std_logic;
-		WEH                     : in std_logic;
-		WEL                     : in std_logic;
-		AddrA           : in std_logic_vector(2 downto 0);
-		AddrB           : in std_logic_vector(2 downto 0);
-		AddrC           : in std_logic_vector(2 downto 0);
-		DIH                     : in std_logic_vector(7 downto 0);
-		DIL                     : in std_logic_vector(7 downto 0);
-		DOAH            : out std_logic_vector(7 downto 0);
-		DOAL            : out std_logic_vector(7 downto 0);
-		DOBH            : out std_logic_vector(7 downto 0);
-		DOBL            : out std_logic_vector(7 downto 0);
-		DOCH            : out std_logic_vector(7 downto 0);
-		DOCL            : out std_logic_vector(7 downto 0)
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
 	);
 end T80_Reg;
 
 architecture rtl of T80_Reg is
 
 	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal      RegsH   : Register_Image(0 to 7);
-	signal      RegsL   : Register_Image(0 to 7);
+	signal	RegsH	: Register_Image(0 to 7);
+	signal	RegsL	: Register_Image(0 to 7);
 
 begin
 
diff --git a/cores/Spectrum/T80a.vhd b/cores/Spectrum/T80a.vhd
index 75636aa..5e1224e 100644
--- a/cores/Spectrum/T80a.vhd
+++ b/cores/Spectrum/T80a.vhd
@@ -1,12 +1,3 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
 --
 -- Z80 compatible microprocessor core, asynchronous top level
 --
@@ -47,25 +38,25 @@
 -- you have the latest version of this file.
 --
 -- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
+--	http://www.opencores.org/cvsweb.shtml/t80/
 --
 -- Limitations :
 --
 -- File history :
 --
---      0208 : First complete release
+--	0208 : First complete release
 --
---      0211 : Fixed interrupt cycle
+--	0211 : Fixed interrupt cycle
 --
---      0235 : Updated for T80 interface change
+--	0235 : Updated for T80 interface change
 --
---      0238 : Updated for T80 interface change
+--	0238 : Updated for T80 interface change
 --
---      0240 : Updated for T80 interface change
+--	0240 : Updated for T80 interface change
 --
---      0242 : Updated for T80 interface change
+--	0242 : Updated for T80 interface change
 --
---      0247 : Fixed bus req/ack cycle
+--	0247 : Fixed bus req/ack cycle
 --
 
 library IEEE;
@@ -75,52 +66,60 @@ use work.T80_Pack.all;
 
 entity T80a is
 	generic(
-		Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
 	);
 	port(
-		RESET_n         : in std_logic;
-		CLK_n           : in std_logic;
-		WAIT_n          : in std_logic;
-		INT_n           : in std_logic;
-		NMI_n           : in std_logic;
-		BUSRQ_n         : in std_logic;
-		M1_n            : out std_logic;
-		MREQ_n          : out std_logic;
-		IORQ_n          : out std_logic;
-		RD_n            : out std_logic;
-		WR_n            : out std_logic;
-		RFSH_n          : out std_logic;
-		HALT_n          : out std_logic;
-		BUSAK_n         : out std_logic;
-		A                       : out std_logic_vector(15 downto 0);
-		D                       : inout std_logic_vector(7 downto 0)
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		MREQ_n		: out std_logic;
+		IORQ_n		: out std_logic;
+		RD_n		: out std_logic;
+		WR_n		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		D			: inout std_logic_vector(7 downto 0);
+
+		SavePC      : out std_logic_vector(15 downto 0);
+		SaveINT     : out std_logic_vector(7 downto 0);
+		RestorePC   : in std_logic_vector(15 downto 0);
+		RestoreINT  : in std_logic_vector(7 downto 0);
+		
+		RestorePC_n : in std_logic
+		
 	);
 end T80a;
 
 architecture rtl of T80a is
 
-	signal CEN                  : std_logic;
-	signal Reset_s              : std_logic;
-	signal IntCycle_n   : std_logic;
-	signal IORQ                 : std_logic;
-	signal NoRead               : std_logic;
-	signal Write                : std_logic;
-	signal MREQ                 : std_logic;
-	signal MReq_Inhibit : std_logic;
-	signal Req_Inhibit  : std_logic;
-	signal RD                   : std_logic;
-	signal MREQ_n_i             : std_logic;
-	signal IORQ_n_i             : std_logic;
-	signal RD_n_i               : std_logic;
-	signal WR_n_i               : std_logic;
-	signal RFSH_n_i             : std_logic;
-	signal BUSAK_n_i    : std_logic;
-	signal A_i                  : std_logic_vector(15 downto 0);
-	signal DO                   : std_logic_vector(7 downto 0);
-	signal DI_Reg               : std_logic_vector (7 downto 0);        -- Input synchroniser
-	signal Wait_s               : std_logic;
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal TState               : std_logic_vector(2 downto 0);
+	signal CEN			: std_logic;
+	signal Reset_s		: std_logic;
+	signal IntCycle_n	: std_logic;
+	signal IORQ			: std_logic;
+	signal NoRead		: std_logic;
+	signal Write		: std_logic;
+	signal MREQ			: std_logic;
+	signal MReq_Inhibit	: std_logic;
+	signal Req_Inhibit	: std_logic;
+	signal RD			: std_logic;
+	signal MREQ_n_i		: std_logic;
+	signal IORQ_n_i		: std_logic;
+	signal RD_n_i		: std_logic;
+	signal WR_n_i		: std_logic;
+	signal RFSH_n_i		: std_logic;
+	signal BUSAK_n_i	: std_logic;
+	signal A_i			: std_logic_vector(15 downto 0);
+	signal DO			: std_logic_vector(7 downto 0);
+	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
+	signal Wait_s		: std_logic;
+	signal MCycle		: std_logic_vector(2 downto 0);
+	signal TState		: std_logic_vector(2 downto 0);
 
 begin
 
@@ -172,7 +171,14 @@ begin
 			DO => DO,
 			MC => MCycle,
 			TS => TState,
-			IntCycle_n => IntCycle_n);
+			IntCycle_n => IntCycle_n,
+			
+			SavePC => SavePC,
+			SaveINT => SaveINT,
+			RestorePC => RestorePC,
+			RestoreINT => RestoreINT,
+			
+			RestorePC_n => RestorePC_n );
 
 	process (CLK_n)
 	begin
@@ -190,7 +196,7 @@ begin
 			WR_n_i <= '1';
 		elsif CLK_n'event and CLK_n = '1' then
 			WR_n_i <= '1';
-			if TState = "001" then      -- To short for IO writes !!!!!!!!!!!!!!!!!!!
+			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
 				WR_n_i <= not Write;
 			end if;
 		end if;
@@ -226,7 +232,6 @@ begin
 	begin
 		if Reset_s = '0' then
 			RD <= '0';
-			IORQ_n_i <= '1';
 			MREQ <= '0';
 		elsif CLK_n'event and CLK_n = '0' then
 
@@ -234,11 +239,9 @@ begin
 				if TState = "001" then
 					RD <= IntCycle_n;
 					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
 				end if;
 				if TState = "011" then
 					RD <= '0';
-					IORQ_n_i <= '1';
 					MREQ <= '1';
 				end if;
 				if TState = "100" then
@@ -247,16 +250,37 @@ begin
 			else
 				if TState = "001" and NoRead = '0' then
 					RD <= not Write;
-					IORQ_n_i <= not IORQ;
 					MREQ <= not IORQ;
 				end if;
 				if TState = "011" then
 					RD <= '0';
-					IORQ_n_i <= '1';
 					MREQ <= '0';
 				end if;
 			end if;
 		end if;
 	end process;
 
+    -- IORQ_n_i uses a different timming than MREQ.
+	process(Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			IORQ_n_i <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			if MCycle = "001" then
+				if TState = "001" then
+					IORQ_n_i <= IntCycle_n;
+				end if;
+				if TState = "011" then
+					IORQ_n_i <= '1';
+				end if;
+			else
+				if TState = "001" then
+					IORQ_n_i <= not IORQ;
+				end if;
+				if TState = "011" then
+					IORQ_n_i <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
 end;
diff --git a/cores/Spectrum/T80s.vhd b/cores/Spectrum/T80s.vhd
new file mode 100644
index 0000000..df6bd14
--- /dev/null
+++ b/cores/Spectrum/T80s.vhd
@@ -0,0 +1,204 @@
+--
+-- Z80 compatible microprocessor core, synchronous top level
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0208 : First complete release
+--
+--	0210 : Fixed read with wait
+--
+--	0211 : Fixed interrupt cycle
+--
+--	0235 : Updated for T80 interface change
+--
+--	0236 : Added T2Write generic
+--
+--	0237 : Fixed T2Write with wait state
+--
+--	0238 : Updated for T80 interface change
+--
+--	0240 : Updated for T80 interface change
+--
+--	0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80s is
+	generic(
+		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
+		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
+	);
+	port(
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		MREQ_n		: out std_logic;
+		IORQ_n		: out std_logic;
+		RD_n		: out std_logic;
+		WR_n		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		DI			: in std_logic_vector(7 downto 0);
+		DO			: out std_logic_vector(7 downto 0);
+
+		SavePC      : out std_logic_vector(15 downto 0);
+		SaveINT     : out std_logic_vector(7 downto 0);
+		RestorePC   : in std_logic_vector(15 downto 0);
+		RestoreINT  : in std_logic_vector(7 downto 0);
+		
+		RestorePC_n : in std_logic
+	);
+end T80s;
+
+architecture rtl of T80s is
+
+	signal CEN			: std_logic;
+	signal IntCycle_n	: std_logic;
+	signal NoRead		: std_logic;
+	signal Write		: std_logic;
+	signal IORQ			: std_logic;
+	signal DI_Reg		: std_logic_vector(7 downto 0);
+	signal MCycle		: std_logic_vector(2 downto 0);
+	signal TState		: std_logic_vector(2 downto 0);
+
+begin
+
+	CEN <= '1';
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => IOWait)
+		port map(
+			CEN => CEN,
+			M1_n => M1_n,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => RFSH_n,
+			HALT_n => HALT_n,
+			WAIT_n => Wait_n,
+			INT_n => INT_n,
+			NMI_n => NMI_n,
+			RESET_n => RESET_n,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK_n,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+			
+			SavePC => SavePC,
+			SaveINT => SaveINT,
+			RestorePC => RestorePC,
+			RestoreINT => RestoreINT,
+			
+			RestorePC_n => RestorePC_n );
+
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			DI_Reg <= "00000000";
+		elsif CLK_n'event and CLK_n = '1' then
+			RD_n <= '1';
+			WR_n <= '1';
+			IORQ_n <= '1';
+			MREQ_n <= '1';
+			if MCycle = "001" then
+				if TState = "001" or (TState = "010" and Wait_n = '0') then
+					RD_n <= not IntCycle_n;
+					MREQ_n <= not IntCycle_n;
+					IORQ_n <= IntCycle_n;
+				end if;
+				if TState = "011" then
+					MREQ_n <= '0';
+				end if;
+			else
+				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
+					RD_n <= '0';
+					IORQ_n <= not IORQ;
+					MREQ_n <= IORQ;
+				end if;
+				if T2Write = 0 then
+					if TState = "010" and Write = '1' then
+						WR_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+				else
+					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+						WR_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+				end if;
+			end if;
+			if TState = "010" and Wait_n = '1' then
+				DI_Reg <= DI;
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/cores/Spectrum/T80se.vhd b/cores/Spectrum/T80se.vhd
new file mode 100644
index 0000000..c47a56e
--- /dev/null
+++ b/cores/Spectrum/T80se.vhd
@@ -0,0 +1,200 @@
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0235 : First release
+--
+--	0236 : Added T2Write generic
+--
+--	0237 : Fixed T2Write with wait state
+--
+--	0238 : Updated for T80 interface change
+--
+--	0240 : Updated for T80 interface change
+--
+--	0242 : Updated for T80 interface change
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80se is
+	generic(
+		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		T2Write : integer := 1;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
+		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
+	);
+	port(
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		CLKEN		: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		MREQ_n		: out std_logic;
+		IORQ_n		: out std_logic;
+		RD_n		: out std_logic;
+		WR_n		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+		DI			: in std_logic_vector(7 downto 0);
+		DO			: out std_logic_vector(7 downto 0);
+
+		SavePC      : out std_logic_vector(15 downto 0);
+		SaveINT     : out std_logic_vector(7 downto 0);
+		RestorePC   : in std_logic_vector(15 downto 0);
+		RestoreINT  : in std_logic_vector(7 downto 0);
+		
+		RestorePC_n : in std_logic
+	);
+end T80se;
+
+architecture rtl of T80se is
+
+	signal IntCycle_n	: std_logic;
+	signal NoRead		: std_logic;
+	signal Write		: std_logic;
+	signal IORQ			: std_logic;
+	signal DI_Reg		: std_logic_vector(7 downto 0);
+	signal MCycle		: std_logic_vector(2 downto 0);
+	signal TState		: std_logic_vector(2 downto 0);
+
+begin
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => IOWait)
+		port map(
+			CEN => CLKEN,
+			M1_n => M1_n,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => RFSH_n,
+			HALT_n => HALT_n,
+			WAIT_n => Wait_n,
+			INT_n => INT_n,
+			NMI_n => NMI_n,
+			RESET_n => RESET_n,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK_n,
+			CLK_n => CLK_n,
+			A => A,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n,
+
+			SavePC => SavePC,
+			SaveINT => SaveINT,
+			RestorePC => RestorePC,
+			RestoreINT => RestoreINT,
+			
+			RestorePC_n => RestorePC_n );
+
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				DI_Reg <= "00000000";
+			elsif CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or TState = "010" then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				else
+					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					else
+						if (TState = "001" or TState = "010") and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					end if;
+				end if;
+				if TState = "010" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+				
+			end if;
+		end if;
+	end process;
+
+end;
diff --git a/cores/Spectrum/bootloader_hex.txt b/cores/Spectrum/bootloader_hex.txt
index d24c109..2b12c11 100644
--- a/cores/Spectrum/bootloader_hex.txt
+++ b/cores/Spectrum/bootloader_hex.txt
@@ -9,7 +9,7 @@ F7
 EF
 BF
 3E
-02
+0A
 F7
 01
 08
diff --git a/cores/Spectrum/cronograma_ula_reloaded.wcfg b/cores/Spectrum/cronograma_ula_reloaded.wcfg
index 993c650..9b14ce7 100644
--- a/cores/Spectrum/cronograma_ula_reloaded.wcfg
+++ b/cores/Spectrum/cronograma_ula_reloaded.wcfg
@@ -3,15 +3,15 @@
    <wave_state>
    </wave_state>
    <db_ref_list>
-      <db_ref path="C:/Users/rodriguj/Documents/zxspectrum/zxuno/repositorio/cores/ula_reloaded/tb_ula_isim_beh.wdb" id="1" type="auto">
+      <db_ref path=".wdb" id="1" type="auto">
          <top_modules>
             <top_module name="glbl" />
             <top_module name="tb_ula" />
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="25" />
-   <wvobject fp_name="/tb_ula/uut/clk14" type="logic" db_ref_id="1">
+   <WVObjectSize size="34" />
+   <wvobject fp_name="/tb_ula/clk14" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">clk14</obj_property>
       <obj_property name="ObjectShortName">clk14</obj_property>
    </wvobject>
@@ -19,9 +19,13 @@
       <obj_property name="ElementShortName">clk7</obj_property>
       <obj_property name="ObjectShortName">clk7</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/rst_n" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">rst_n</obj_property>
-      <obj_property name="ObjectShortName">rst_n</obj_property>
+   <wvobject fp_name="/tb_ula/uut/hc[0]" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">[0]</obj_property>
+      <obj_property name="ObjectShortName">hc[0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/cpuclk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cpuclk</obj_property>
+      <obj_property name="ObjectShortName">cpuclk</obj_property>
    </wvobject>
    <wvobject fp_name="/tb_ula/uut/hc" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">hc[8:0]</obj_property>
@@ -33,18 +37,37 @@
       <obj_property name="ObjectShortName">vc[8:0]</obj_property>
       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/int_n" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">int_n</obj_property>
-      <obj_property name="ObjectShortName">int_n</obj_property>
+   <wvobject fp_name="/tb_ula/uut/VideoEnable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">VideoEnable</obj_property>
+      <obj_property name="ObjectShortName">VideoEnable</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/cpuclk" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">cpuclk</obj_property>
-      <obj_property name="ObjectShortName">cpuclk</obj_property>
+   <wvobject fp_name="/tb_ula/uut/MayContend_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">MayContend_n</obj_property>
+      <obj_property name="ObjectShortName">MayContend_n</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/uut/tstates" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">tstates[16:0]</obj_property>
-      <obj_property name="ObjectShortName">tstates[16:0]</obj_property>
-      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   <wvobject fp_name="/tb_ula/uut/CauseContention_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">CauseContention_n</obj_property>
+      <obj_property name="ObjectShortName">CauseContention_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/uut/CancelContention" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">CancelContention</obj_property>
+      <obj_property name="ObjectShortName">CancelContention</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/uut/BitmapAddr" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">BitmapAddr</obj_property>
+      <obj_property name="ObjectShortName">BitmapAddr</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/uut/AttrAddr" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">AttrAddr</obj_property>
+      <obj_property name="ObjectShortName">AttrAddr</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/uut/BitmapDataLoad" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">BitmapDataLoad</obj_property>
+      <obj_property name="ObjectShortName">BitmapDataLoad</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/uut/AttrDataLoad" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">AttrDataLoad</obj_property>
+      <obj_property name="ObjectShortName">AttrDataLoad</obj_property>
    </wvobject>
    <wvobject fp_name="/tb_ula/va" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">va[13:0]</obj_property>
@@ -56,31 +79,11 @@
       <obj_property name="ObjectShortName">vramdata[7:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/uut/VideoEnable" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">VideoEnable</obj_property>
-      <obj_property name="ObjectShortName">VideoEnable</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb_ula/uut/BitmapAddr" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">BitmapAddr</obj_property>
-      <obj_property name="ObjectShortName">BitmapAddr</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb_ula/uut/BitmapDataLoad" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">BitmapDataLoad</obj_property>
-      <obj_property name="ObjectShortName">BitmapDataLoad</obj_property>
-   </wvobject>
    <wvobject fp_name="/tb_ula/uut/BitmapData" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">BitmapData[7:0]</obj_property>
       <obj_property name="ObjectShortName">BitmapData[7:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/uut/AttrAddr" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">AttrAddr</obj_property>
-      <obj_property name="ObjectShortName">AttrAddr</obj_property>
-   </wvobject>
-   <wvobject fp_name="/tb_ula/uut/AttrDataLoad" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">AttrDataLoad</obj_property>
-      <obj_property name="ObjectShortName">AttrDataLoad</obj_property>
-   </wvobject>
    <wvobject fp_name="/tb_ula/uut/AttrData" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">AttrData[7:0]</obj_property>
       <obj_property name="ObjectShortName">AttrData[7:0]</obj_property>
@@ -94,14 +97,44 @@
       <obj_property name="ElementShortName">AttrOutputLoad</obj_property>
       <obj_property name="ObjectShortName">AttrOutputLoad</obj_property>
    </wvobject>
+   <wvobject fp_name="/tb_ula/uut/CA" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">CA[4:0]</obj_property>
+      <obj_property name="ObjectShortName">CA[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
    <wvobject fp_name="/tb_ula/uut/CALoad" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">CALoad</obj_property>
       <obj_property name="ObjectShortName">CALoad</obj_property>
    </wvobject>
-   <wvobject fp_name="/tb_ula/uut/CA" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">CA[4:0]</obj_property>
-      <obj_property name="ObjectShortName">CA[4:0]</obj_property>
-      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   <wvobject fp_name="/tb_ula/rst_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_n</obj_property>
+      <obj_property name="ObjectShortName">rst_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/mreq_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mreq_n</obj_property>
+      <obj_property name="ObjectShortName">mreq_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/iorq_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">iorq_n</obj_property>
+      <obj_property name="ObjectShortName">iorq_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/rd_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rd_n</obj_property>
+      <obj_property name="ObjectShortName">rd_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/wr_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">wr_n</obj_property>
+      <obj_property name="ObjectShortName">wr_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">a[15:0]</obj_property>
+      <obj_property name="ObjectShortName">a[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_ula/va" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">va[13:0]</obj_property>
+      <obj_property name="ObjectShortName">va[13:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
    </wvobject>
    <wvobject fp_name="/tb_ula/r" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">r[2:0]</obj_property>
@@ -122,4 +155,8 @@
       <obj_property name="ElementShortName">csync</obj_property>
       <obj_property name="ObjectShortName">csync</obj_property>
    </wvobject>
+   <wvobject fp_name="/tb_ula/int_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">int_n</obj_property>
+      <obj_property name="ObjectShortName">int_n</obj_property>
+   </wvobject>
 </wave_config>
diff --git a/cores/Spectrum/iseconfig/tld_zxuno.xreport b/cores/Spectrum/iseconfig/tld_zxuno.xreport
index b44cb15..6abb66c 100644
--- a/cores/Spectrum/iseconfig/tld_zxuno.xreport
+++ b/cores/Spectrum/iseconfig/tld_zxuno.xreport
@@ -1,12 +1,12 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2014-12-09T12:44:14</DateModified>
+  <DateModified>2015-06-08T00:07:51</DateModified>
   <ModuleName>tld_zxuno</ModuleName>
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
-  <SavedFilePath>A:/zxuno/cores/spectrum_v2_spartan6/test14/iseconfig/tld_zxuno.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>A:/zxuno/cores/spectrum_v2_spartan6/test14\</ImplementationReportsDirectory>
-  <DateInitialized>2014-12-03T23:37:26</DateInitialized>
+  <SavedFilePath>A:/zxuno/cores/spectrum_v2_spartan6/test15/iseconfig/tld_zxuno.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>A:/zxuno/cores/spectrum_v2_spartan6/test15\</ImplementationReportsDirectory>
+  <DateInitialized>2014-12-12T22:53:38</DateInitialized>
   <EnableMessageFiltering>true</EnableMessageFiltering>
  </header>
  <body>
diff --git a/cores/Spectrum/iseconfig/zxuno.projectmgr b/cores/Spectrum/iseconfig/zxuno.projectmgr
index c377bf7..782fcd5 100644
--- a/cores/Spectrum/iseconfig/zxuno.projectmgr
+++ b/cores/Spectrum/iseconfig/zxuno.projectmgr
@@ -7,16 +7,15 @@
    <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
       <ClosedNodes>
          <ClosedNode>/tld_zxuno/la_maquina - zxuno</ClosedNode>
-         <ClosedNode>/ula</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem>tld_zxuno (A:/zxuno/cores/spectrum_v2_spartan6/test14/tld_zxuno.v)</SelectedItem>
+         <SelectedItem>tld_zxuno (A:/zxuno/cores/spectrum_v2_spartan6/test15/tld_zxuno.v)</SelectedItem>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000029d000000020000000000000000000000000000000064ffffffff0000008100000000000000020000029d0000000100000000000000000000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000025b000000020000000000000000000000000000000064ffffffff0000008100000000000000020000025b0000000100000000000000000000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>tld_zxuno (A:/zxuno/cores/spectrum_v2_spartan6/test14/tld_zxuno.v)</CurrentItem>
+      <CurrentItem>tld_zxuno (A:/zxuno/cores/spectrum_v2_spartan6/test15/tld_zxuno.v)</CurrentItem>
    </ItemView>
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
       <ClosedNodes>
@@ -40,9 +39,9 @@
       <SelectedItems/>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000382000000040101000100000000000000000000000064ffffffff000000810000000000000004000001ea0000000100000000000000bb0000000100000000000000760000000100000000000000670000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000366000000040101000100000000000000000000000064ffffffff000000810000000000000004000001ce0000000100000000000000bb0000000100000000000000760000000100000000000000670000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>A:\zxuno\cores\spectrum_v2_spartan6\test14\T80.vhd</CurrentItem>
+      <CurrentItem>A:\zxuno\cores\spectrum_v2_spartan6\test15\T80.vhd</CurrentItem>
    </ItemView>
    <ItemView guiview="Library" >
       <ClosedNodes>
@@ -57,7 +56,7 @@
    </ItemView>
    <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
       <ClosedNodes>
-         <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
+         <ClosedNode>Design Utilities</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
          <SelectedItem>Add Existing Source</SelectedItem>
@@ -70,17 +69,4 @@
    </ItemView>
    <SourceProcessView>000000ff0000000000000002000001390000011b01000000050100000002</SourceProcessView>
    <CurrentView>Implementation</CurrentView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNode>User Constraints</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem/>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000016e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000016e0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem/>
-   </ItemView>
 </Project>
diff --git a/cores/Spectrum/mapa_teclado_uk.vhd b/cores/Spectrum/mapa_teclado_uk.vhd
new file mode 100644
index 0000000..c3e098a
--- /dev/null
+++ b/cores/Spectrum/mapa_teclado_uk.vhd
@@ -0,0 +1,129 @@
+--	Package File Template
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package mapa_uk is
+  constant KEY_RELEASED : std_logic_vector(7 downto 0) := X"f0";
+  constant KEY_EXTENDED : std_logic_vector(7 downto 0) := X"e0";
+  constant KEY_ESC 		: std_logic_vector(7 downto 0) := X"76";
+  constant KEY_F1 		: std_logic_vector(7 downto 0) := X"05";
+  constant KEY_F2 		: std_logic_vector(7 downto 0) := X"06";
+  constant KEY_F3 		: std_logic_vector(7 downto 0) := X"04";
+  constant KEY_F4 		: std_logic_vector(7 downto 0) := X"0C";
+  constant KEY_F5 		: std_logic_vector(7 downto 0) := X"03";
+  constant KEY_F6 		: std_logic_vector(7 downto 0) := X"0B";
+  constant KEY_F7 		: std_logic_vector(7 downto 0) := X"83";
+  constant KEY_F8 		: std_logic_vector(7 downto 0) := X"0A";
+  constant KEY_F9 		: std_logic_vector(7 downto 0) := X"01";
+  constant KEY_F10 		: std_logic_vector(7 downto 0) := X"09";
+  constant KEY_F11 		: std_logic_vector(7 downto 0) := X"78";
+  constant KEY_F12 		: std_logic_vector(7 downto 0) := X"07";
+
+  constant KEY_GRAVEAC	: std_logic_vector(7 downto 0) := X"0E";
+  constant KEY_1 		: std_logic_vector(7 downto 0) := X"16";
+  constant KEY_2 		: std_logic_vector(7 downto 0) := X"1E";
+  constant KEY_3 		: std_logic_vector(7 downto 0) := X"26";
+  constant KEY_4 		: std_logic_vector(7 downto 0) := X"25";
+  constant KEY_5 		: std_logic_vector(7 downto 0) := X"2E";
+  constant KEY_6 		: std_logic_vector(7 downto 0) := X"36";
+  constant KEY_7 		: std_logic_vector(7 downto 0) := X"3D";
+  constant KEY_8 		: std_logic_vector(7 downto 0) := X"3E";
+  constant KEY_9 		: std_logic_vector(7 downto 0) := X"46";
+  constant KEY_0 		: std_logic_vector(7 downto 0) := X"45";
+  constant KEY_MINUS 	: std_logic_vector(7 downto 0) := X"4E";
+  constant KEY_EQUAL 	: std_logic_vector(7 downto 0) := X"55";
+  constant KEY_BKSP 	: std_logic_vector(7 downto 0) := X"66";
+
+  constant KEY_TAB 		: std_logic_vector(7 downto 0) := X"0D";
+  constant KEY_Q 		: std_logic_vector(7 downto 0) := X"15";
+  constant KEY_W 		: std_logic_vector(7 downto 0) := X"1D";
+  constant KEY_E 		: std_logic_vector(7 downto 0) := X"24";
+  constant KEY_R 		: std_logic_vector(7 downto 0) := X"2D";
+  constant KEY_T 		: std_logic_vector(7 downto 0) := X"2C";
+  constant KEY_Y 		: std_logic_vector(7 downto 0) := X"35";
+  constant KEY_U 		: std_logic_vector(7 downto 0) := X"3C";
+  constant KEY_I 		: std_logic_vector(7 downto 0) := X"43";
+  constant KEY_O 		: std_logic_vector(7 downto 0) := X"44";
+  constant KEY_P 		: std_logic_vector(7 downto 0) := X"4D";
+  constant KEY_CORCHA 	: std_logic_vector(7 downto 0) := X"54";
+  constant KEY_CORCHC 	: std_logic_vector(7 downto 0) := X"5B";
+  constant KEY_BL 	    : std_logic_vector(7 downto 0) := X"5D";
+  constant KEY_ENTER 	: std_logic_vector(7 downto 0) := X"5A";
+
+  constant KEY_CPSLK 	: std_logic_vector(7 downto 0) := X"58";
+  constant KEY_A 		: std_logic_vector(7 downto 0) := X"1C";
+  constant KEY_S 		: std_logic_vector(7 downto 0) := X"1B";
+  constant KEY_D 		: std_logic_vector(7 downto 0) := X"23";
+  constant KEY_F 		: std_logic_vector(7 downto 0) := X"2B";
+  constant KEY_G 		: std_logic_vector(7 downto 0) := X"34";
+  constant KEY_H 		: std_logic_vector(7 downto 0) := X"33";
+  constant KEY_J 		: std_logic_vector(7 downto 0) := X"3B";
+  constant KEY_K 		: std_logic_vector(7 downto 0) := X"42";
+  constant KEY_L 		: std_logic_vector(7 downto 0) := X"4B";
+  constant KEY_SEMICOL	: std_logic_vector(7 downto 0) := X"4C";
+  constant KEY_ACUTEAC 	: std_logic_vector(7 downto 0) := X"52";
+
+  constant KEY_LSHIFT	: std_logic_vector(7 downto 0) := X"12";
+  constant KEY_Z 		: std_logic_vector(7 downto 0) := X"1A";
+  constant KEY_X 		: std_logic_vector(7 downto 0) := X"22";
+  constant KEY_C 		: std_logic_vector(7 downto 0) := X"21";
+  constant KEY_V 		: std_logic_vector(7 downto 0) := X"2A";
+  constant KEY_B 		: std_logic_vector(7 downto 0) := X"32";
+  constant KEY_N 		: std_logic_vector(7 downto 0) := X"31";
+  constant KEY_M 		: std_logic_vector(7 downto 0) := X"3A";
+  constant KEY_COMMA 	: std_logic_vector(7 downto 0) := X"41";
+  constant KEY_DOT 	    : std_logic_vector(7 downto 0) := X"49";
+  constant KEY_SLASH 	: std_logic_vector(7 downto 0) := X"4A";
+  constant KEY_RSHIFT	: std_logic_vector(7 downto 0) := X"59";
+
+  constant KEY_CTRLI 	: std_logic_vector(7 downto 0) := X"14";
+  constant KEY_ALTI 	: std_logic_vector(7 downto 0) := X"11";
+  constant KEY_SPACE 	: std_logic_vector(7 downto 0) := X"29";
+
+  constant KEY_KP0 		: std_logic_vector(7 downto 0) := X"70";
+  constant KEY_KP1 		: std_logic_vector(7 downto 0) := X"69";
+  constant KEY_KP2 		: std_logic_vector(7 downto 0) := X"72";
+  constant KEY_KP3 		: std_logic_vector(7 downto 0) := X"7A";
+  constant KEY_KP4 		: std_logic_vector(7 downto 0) := X"6B";
+  constant KEY_KP5 		: std_logic_vector(7 downto 0) := X"73";
+  constant KEY_KP6 		: std_logic_vector(7 downto 0) := X"74";
+  constant KEY_KP7 		: std_logic_vector(7 downto 0) := X"6C";
+  constant KEY_KP8 		: std_logic_vector(7 downto 0) := X"75";
+  constant KEY_KP9 		: std_logic_vector(7 downto 0) := X"7D";
+  constant KEY_KPDOT 	: std_logic_vector(7 downto 0) := X"71";
+  constant KEY_KPPLUS 	: std_logic_vector(7 downto 0) := X"79";
+  constant KEY_KPMINUS 	: std_logic_vector(7 downto 0) := X"7B";
+  constant KEY_KPSTAR 	: std_logic_vector(7 downto 0) := X"7C";
+
+  constant KEY_NUMLOCK	: std_logic_vector(7 downto 0) := X"77";
+  constant KEY_SCRLOCK 	: std_logic_vector(7 downto 0) := X"7E";
+
+-- Teclas con E0 + scancode
+  constant KEY_WAKEUP 	: std_logic_vector(7 downto 0) := X"5E";
+  constant KEY_SLEEP 	: std_logic_vector(7 downto 0) := X"3F";
+  constant KEY_POWER 	: std_logic_vector(7 downto 0) := X"37";
+  constant KEY_INS 		: std_logic_vector(7 downto 0) := X"70";
+  constant KEY_DEL 		: std_logic_vector(7 downto 0) := X"71";
+  constant KEY_HOME 	: std_logic_vector(7 downto 0) := X"6C";
+  constant KEY_END 		: std_logic_vector(7 downto 0) := X"69";
+  constant KEY_PGU 		: std_logic_vector(7 downto 0) := X"7D";
+  constant KEY_PGD 		: std_logic_vector(7 downto 0) := X"7A";
+  constant KEY_UP 		: std_logic_vector(7 downto 0) := X"75";
+  constant KEY_DOWN 	: std_logic_vector(7 downto 0) := X"72";
+  constant KEY_LEFT 	: std_logic_vector(7 downto 0) := X"6B";
+  constant KEY_RIGHT 	: std_logic_vector(7 downto 0) := X"74";
+  constant KEY_CTRLD 	: std_logic_vector(7 downto 0) := X"14";
+  constant KEY_ALTD 	: std_logic_vector(7 downto 0) := X"11";
+  constant KEY_KPENTER 	: std_logic_vector(7 downto 0) := X"5A";
+  constant KEY_KPSLASH 	: std_logic_vector(7 downto 0) := X"4A";
+  constant KEY_PRTSCR 	: std_logic_vector(7 downto 0) := X"7C";
+
+end package mapa_uk;
+
+package body mapa_uk is
+end package body mapa_uk;
\ No newline at end of file
diff --git a/cores/Spectrum/memory.v b/cores/Spectrum/memory.v
index 975a383..684b71a 100644
--- a/cores/Spectrum/memory.v
+++ b/cores/Spectrum/memory.v
@@ -30,7 +30,7 @@ module memory (
    input wire [15:0] a,
    input wire [7:0] din,  // proveniente del bus de datos de salida de la CPU
    output reg [7:0] dout, // hacia el bus de datos de entrada de la CPU
-   output reg oe_n,       // el dato es valido   
+   output reg oe_n,       // el dato es valido
    input wire mreq_n,
    input wire iorq_n,
    input wire rd_n,
@@ -38,24 +38,27 @@ module memory (
    input wire m1_n,
    input wire rfsh_n,
    output wire enable_nmi_n,
-   
+
    // Interface con la ULA
    input wire [13:0] vramaddr,
    output wire [7:0] vramdout,
    output wire issue2_keyboard_enabled,
-   
+   output wire timming_ula,
+   output wire disable_contention,
+   output reg access_to_screen,
+
    // Interface para registros ZXUNO
    input wire [7:0] addr,
    input wire ior,
    input wire iow,
    output wire in_boot_mode,
-   
+
    // Interface con la SRAM
    output wire [18:0] sram_addr,
    inout wire [7:0] sram_data,
    output wire sram_we_n
    );
-   
+
    parameter
       MASTERCONF = 8'h00,
       MASTERMAPPER = 8'h01;
@@ -64,22 +67,29 @@ module memory (
    reg divmmc_is_enabled = 1'b0;
    reg divmmc_nmi_is_disabled = 1'b0;
    reg issue2_keyboard = 1'b0;
+   reg timming = 1'b0;
+   reg disable_cont = 1'b0;
    reg masterconf_frozen = 1'b0;
-   
+
    assign issue2_keyboard_enabled = issue2_keyboard;
    assign in_boot_mode = ~masterconf_frozen;
+   assign timming_ula = timming;
+   assign disable_contention = disable_cont;
 
    always @(posedge clk) begin
       if (!mrst_n) begin
-         {issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= 4'b0001;
+         {disable_cont,timming,issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= 6'b000001;
          masterconf_frozen <= 1'b0;
       end
-      else if (addr==MASTERCONF && iow && !masterconf_frozen) begin
-         {issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= din[3:0];
-         masterconf_frozen <= din[7];
+      else if (addr==MASTERCONF && iow) begin
+         {disable_cont,timming,issue2_keyboard} <= din[5:3];
+         if (!masterconf_frozen) begin
+            masterconf_frozen <= din[7];
+            {divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode} <= din[2:0];
+         end
       end
    end
-   
+
    reg [4:0] mastermapper = 5'h00;
    always @(posedge clk) begin
       if (!mrst_n)
@@ -126,7 +136,7 @@ module memory (
             divmmc_status_after_m1 <= 1'b0;
          end
       end
-      if (m1_n==1'b1 /*!rfsh_n && !mreq_n*/) begin  // tras el ciclo M1, aquí es cuando realmente se hace el mapping
+      if (m1_n==1'b1) begin  // tras el ciclo M1, aquí es cuando realmente se hace el mapping
          divmmc_is_paged <= divmmc_status_after_m1;
       end
    end
@@ -184,7 +194,6 @@ module memory (
          end
          else begin  // estamos en modo normal de ejecución
 
-            // TODO: añadir aquí el codigo para comprobar si ha de paginarse la ROM del DIVMMC!!!!!!!!!!
             if (divmmc_is_enabled && (divmmc_is_paged || conmem)) begin  // DivMMC ha entrado en modo automapper o está mapeado a la fuerza
                if (a[13]==1'b0) begin // Si estamos en los primeros 8K
                   if (conmem || !mapram_mode) begin
@@ -276,6 +285,18 @@ module memory (
       end
    end
 
+   // Hay contienda en las páginas 5 y 7 de memoria, que son las dos páginas de pantalla
+   always @* begin
+     access_to_screen = 1'b0;
+     if (!initial_boot_mode) begin
+        if (!amstrad_allram_page_mode) begin
+           if (a[15:14]==2'b01 || (a[15:14]==2'b11 && (banco_ram==3'd5 || banco_ram==3'd7))) begin
+               access_to_screen = 1'b1;
+           end
+        end
+     end
+   end
+
    // Conexiones internas
    wire [7:0] bootrom_dout;
    wire [7:0] ram_dout;
@@ -303,8 +324,6 @@ module memory (
    rom boot_rom (
       .clk(mclk),
       .a(a[13:0]),
-      .we(1'b0), // !mreq_n && !wr_n && a[15:14]==2'b00),
-      .din(),  // (din),
       .dout(bootrom_dout)
     );    
 
@@ -319,7 +338,7 @@ module memory (
          oe_n = 1'b0;
       end
       else if (addr==MASTERCONF && ior) begin
-         dout = {6'h00,divmmc_is_enabled,initial_boot_mode};
+         dout = {masterconf_frozen,1'b0,disable_cont,timming,issue2_keyboard,divmmc_nmi_is_disabled,divmmc_is_enabled,initial_boot_mode};
          oe_n = 1'b0;
       end
       else if (addr==MASTERMAPPER && ior) begin
diff --git a/cores/Spectrum/pal_sync_generator_sinclair.v b/cores/Spectrum/pal_sync_generator_sinclair.v
new file mode 100644
index 0000000..128d9b1
--- /dev/null
+++ b/cores/Spectrum/pal_sync_generator_sinclair.v
@@ -0,0 +1,85 @@
+`timescale 1ns / 1ps
+`default_nettype none
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    00:11:22 10/17/2012 
+// Design Name: 
+// Module Name:    pal_generator 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module pal_sync_generator_sinclair (
+    input wire clk,
+    input wire timming,
+    input wire [2:0] ri,
+    input wire [2:0] gi,
+    input wire [2:0] bi,
+    output wire [8:0] hcnt,
+    output wire [8:0] vcnt,
+    output reg [2:0] ro,
+    output reg [2:0] go,
+    output reg [2:0] bo,
+    output reg csync
+    );
+
+    parameter
+      END_COUNT_H_48K  = 447,
+      END_COUNT_V_48K  = 311,
+      END_COUNT_H_128K = 455,
+      END_COUNT_V_128K = 310,
+      BHBLANK          = 320,
+      EHBLANK          = 415,
+      BHSYNC           = 344,
+      EHSYNC           = 375,
+      BVPERIOD         = 248,
+      EVPERIOD         = 255,
+      BVSYNC           = 248,
+      EVSYNC           = 251;
+
+	reg [8:0] hc = 9'h000;
+	reg [8:0] vc = 9'h137;  // linea 311
+
+	assign hcnt = hc;
+	assign vcnt = vc;
+	
+	always @(posedge clk) begin
+		if ( (hc == END_COUNT_H_48K && !timming) || (hc == END_COUNT_H_128K && timming) ) begin
+			hc <= 0;
+			if ( (vc == END_COUNT_V_48K && !timming) || (vc == END_COUNT_V_128K && timming) )
+				vc <= 0;
+			else
+				vc <= vc + 1;
+		end
+		else
+			hc <= hc + 1;
+	end
+
+    always @* begin
+        ro = ri;
+        go = gi;
+        bo = bi;
+        csync = 1'b1;
+        if ( (hc>=BHBLANK && hc<=EHBLANK) || (vc>=BVPERIOD && vc<=EVPERIOD) ) begin
+            ro = 3'b000;
+            go = 3'b000;
+            bo = 3'b000;
+            if ( (hc>=BHSYNC && hc<=EHSYNC) || (vc>=BVSYNC && vc<=EVSYNC) ) begin
+                csync = 1'b0;
+            end
+        end
+     end
+        
+endmodule
diff --git a/cores/Spectrum/pantalla_ulatest3.hex b/cores/Spectrum/pantalla_ulatest3.hex
new file mode 100644
index 0000000..5c16417
--- /dev/null
+++ b/cores/Spectrum/pantalla_ulatest3.hex
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diff --git a/cores/Spectrum/par_usage_statistics.html b/cores/Spectrum/par_usage_statistics.html
index d7889d4..35d8594 100644
--- a/cores/Spectrum/par_usage_statistics.html
+++ b/cores/Spectrum/par_usage_statistics.html
@@ -1,31 +1,31 @@
 <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
 <xtag-section name="ParStatistics">
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>3291</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>13317</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>13317</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>12231</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>8.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>18.2 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>20.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>34.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>34.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>34.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>34.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>35.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>36.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>3241</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>13509</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>13509</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>12464</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.9 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>17.3 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>19.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>49.3 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>64.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>64.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>64.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>65.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>67.0 sec</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>5.7</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.3</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.4</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>6.8</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.6</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>11.4962</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>10.5109</xtag-par-property-value></TD></TR>
 </xtag-section>
 </TABLE>
diff --git a/cores/Spectrum/pines_zxuno.ucf b/cores/Spectrum/pines_zxuno.ucf
index 2afa78a..f652ef6 100644
--- a/cores/Spectrum/pines_zxuno.ucf
+++ b/cores/Spectrum/pines_zxuno.ucf
@@ -1,6 +1,8 @@
 # Clocks & debug
 NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
 NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
+NET "clk50mhz" PERIOD=20 ns;
+NET "sysclk" PERIOD=35 ns;
 
 # Video output
 NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
@@ -14,6 +16,8 @@ NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
 NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
 NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
 #NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
+NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
+NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
 
 # Sound input/output
 NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
@@ -21,10 +25,10 @@ NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
 NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
 
 # Keyboard
-NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33;
-NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33;
-#NET "clkmouse" LOC="P94" | IOSTANDARD = LVCMOS33;  # comprobar estos pines
-#NET "datamouse" LOC="P95" | IOSTANDARD = LVCMOS33; # los he asignado a voleo
+NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
+#NET "clkmouse" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;  # comprobar estos pines
+#NET "datamouse" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # los he asignado a voleo
 
 # SRAM
 NET "sram_addr<0>"  LOC="P115" | IOSTANDARD = LVCMOS33;
@@ -70,4 +74,11 @@ NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
 NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
 NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
 NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
-NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
\ No newline at end of file
+NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
+
+# JOYSTICK
+NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;    #JOY6
+NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY4
+NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY3
+NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
+NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;  #JOY7
diff --git a/cores/Spectrum/ps2k_av.vhd b/cores/Spectrum/ps2k_av.vhd
new file mode 100644
index 0000000..407882d
--- /dev/null
+++ b/cores/Spectrum/ps2k_av.vhd
@@ -0,0 +1,180 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.mapa_es.all;
+
+entity ps2k is port (
+    clk     : in  std_logic;
+    ps2clk  : in  std_logic;
+    ps2data : in  std_logic;
+    rows    : in  std_logic_vector(7 downto 0);
+    cols    : out std_logic_vector(4 downto 0);
+    joy     : out std_logic_vector(4 downto 0);
+    scancode: out std_logic_vector(7 downto 0);
+    rst     : out std_logic;
+    nmi     : out std_logic;
+    mrst    : out std_logic);
+end ps2k;
+
+architecture behavioral of ps2k is
+
+  type    key_matrix  is array (7 downto 0) of std_logic_vector(4 downto 0);
+  signal  keys      : key_matrix;
+  signal  pressed   : std_logic;
+  signal  isalt     : std_logic;
+  signal  lastclk   : std_logic_vector(4 downto 0);
+  signal  bit_count : unsigned (3 downto 0);
+  signal  shiftreg  : std_logic_vector(8 downto 0);
+  signal  parity    : std_logic;
+
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      rst <= '1';
+      nmi <= '1';
+      mrst <= '1';
+      lastclk <= lastclk(3 downto 0) & ps2clk;
+      if lastclk="11100" and ps2clk='0' then  -- detector de flanco de bajada de PS2CLK
+        if bit_count=0 then
+          parity <= '0';
+          if ps2data='0' then
+            bit_count <= bit_count + 1;
+          end if;
+        else
+          if bit_count<10 then
+            bit_count <= bit_count + 1;
+            shiftreg  <= ps2data & shiftreg(8 downto 1);
+            parity    <= parity xor ps2data;
+          elsif ps2data='1' then
+            bit_count <= (others => '0');
+            if parity = '1' then -- nueva pulsacion completa en shiftreg.
+              pressed  <= '1';
+              scancode <= shiftreg(7 downto 0);
+              case shiftreg(7 downto 0) is
+                when X"f0" => pressed    <= '0';
+                when X"12" |
+                     X"59" => keys(0)(0) <= pressed; -- Left or Right shift (CAPS SHIFT)
+                when X"1a" => keys(0)(1) <= pressed; -- Z
+                when X"22" => keys(0)(2) <= pressed; -- X
+                when X"21" => keys(0)(3) <= pressed; -- C
+                when X"2a" => keys(0)(4) <= pressed; -- V
+                when X"1c" => keys(1)(0) <= pressed; -- A
+                when X"1b" => keys(1)(1) <= pressed; -- S
+                when X"23" => keys(1)(2) <= pressed; -- D
+                when X"2b" => keys(1)(3) <= pressed; -- F
+                when X"34" => keys(1)(4) <= pressed; -- G
+                when X"15" => keys(2)(0) <= pressed; -- Q
+                when X"1d" => keys(2)(1) <= pressed; -- W
+                when X"24" => keys(2)(2) <= pressed; -- E
+                when X"2d" => keys(2)(3) <= pressed; -- R
+                when X"2c" => keys(2)(4) <= pressed; -- T
+                when X"16" => keys(3)(0) <= pressed; -- 1
+                when X"1e" => keys(3)(1) <= pressed; -- 2
+                when X"26" => keys(3)(2) <= pressed; -- 3
+                when X"25" => keys(3)(3) <= pressed; -- 4
+                when X"2e" => keys(3)(4) <= pressed; -- 5
+                when X"45" => keys(4)(0) <= pressed; -- 0
+                when X"46" => keys(4)(1) <= pressed; -- 9
+                when X"3e" => keys(4)(2) <= pressed; -- 8
+                when X"3d" => keys(4)(3) <= pressed; -- 7
+                when X"36" => keys(4)(4) <= pressed; -- 6
+                when X"4d" => keys(5)(0) <= pressed; -- P
+                when X"44" => keys(5)(1) <= pressed; -- O
+                when X"43" => keys(5)(2) <= pressed; -- I
+                when X"3c" => keys(5)(3) <= pressed; -- U
+                when X"35" => keys(5)(4) <= pressed; -- Y
+                when X"5a" => keys(6)(0) <= pressed; -- ENTER
+                when X"4b" => keys(6)(1) <= pressed; -- L
+                when X"42" => keys(6)(2) <= pressed; -- K
+                when X"3b" => keys(6)(3) <= pressed; -- J
+                when X"33" => keys(6)(4) <= pressed; -- H
+                when X"29" => keys(7)(0) <= pressed; -- SPACE
+                when X"14" => keys(7)(1) <= pressed; -- CTRL (Symbol Shift)
+                when X"3a" => keys(7)(2) <= pressed; -- M
+                when X"31" => keys(7)(3) <= pressed; -- N
+                when X"32" => keys(7)(4) <= pressed; -- B
+                when X"76" => keys(0)(0) <= pressed; -- Break (Caps Space)
+                              keys(7)(0) <= pressed;
+                when X"0e" |
+                     X"06" => keys(0)(0) <= pressed; -- Edit (Caps 1)
+                              keys(3)(0) <= pressed;
+                when X"4e" |
+                     X"09" => keys(0)(0) <= pressed; -- Graph (Caps 9)
+                              keys(4)(1) <= pressed;
+                when X"66" => keys(0)(0) <= pressed; -- Backspace (Caps 0)
+                              keys(4)(0) <= pressed;
+                              if keys(7)(1)='1' and isalt='1' then
+                                mrst <= '0';         -- Master Reset
+                              end if;
+                when X"0d" => keys(0)(0) <= pressed; -- Extend
+                              keys(7)(1) <= pressed;
+                when X"54" => keys(0)(0) <= pressed; -- True Video (Caps 3)
+                              keys(3)(2) <= pressed;
+                when X"5b" => keys(0)(0) <= pressed; -- Inv. Video (Caps 4)
+                              keys(3)(3) <= pressed;
+                when X"58" => keys(0)(0) <= pressed; -- Caps lock (Caps 2)
+                              keys(3)(1) <= pressed;
+                when X"6b" => keys(0)(0) <= pressed; -- Left (Caps 5)
+                              keys(3)(4) <= pressed;
+                when X"72" => keys(0)(0) <= pressed; -- Down (Caps 6)
+                              keys(4)(4) <= pressed;
+                when X"75" => keys(0)(0) <= pressed; -- Up (Caps 7)
+                              keys(4)(3) <= pressed;
+                when X"74" => keys(0)(0) <= pressed; -- Right (Caps 8)
+                              keys(4)(2) <= pressed;
+                when X"55" => keys(7)(1) <= pressed; -- = (Symb L)
+                              keys(6)(1) <= pressed;
+                when X"4a" => keys(7)(1) <= pressed; -- / (Symb V)
+                              keys(0)(4) <= pressed;
+                when X"7c" => keys(7)(1) <= pressed; -- * (Symb B)
+                              keys(7)(4) <= pressed;
+                when X"7b" => keys(7)(1) <= pressed; -- - (Symb J)
+                              keys(6)(3) <= pressed;
+                when X"79" => keys(7)(1) <= pressed; -- + (Symb K)
+                              keys(6)(2) <= pressed;
+                when X"4c" => keys(7)(1) <= pressed; -- ; (Symb O)
+                              keys(5)(1) <= pressed;
+                when X"52" => keys(7)(1) <= pressed; -- " (Symb P)
+                              keys(5)(0) <= pressed;
+                when X"41" => keys(7)(1) <= pressed; -- , (Symb N)
+                              keys(7)(3) <= pressed;
+                when X"49" => keys(7)(1) <= pressed; -- , (Symb M)
+                              keys(7)(2) <= pressed;
+                when X"71" => joy(1)     <= pressed; -- Joy Left
+                              if keys(7)(1)='1' and isalt='1' then
+                                rst <= '0';          -- Reset
+                              end if;
+                when X"69" => joy(2)     <= pressed; -- Joy Down
+                when X"6c" => joy(3)     <= pressed; -- Joy Up
+                when X"7a" => joy(0)     <= pressed; -- Joy Right
+                when X"11" => joy(4)     <= pressed; -- Joy Fire
+                              isalt      <= pressed;
+                when X"03" => if keys(7)(1)='1' and isalt='1' then
+                                nmi <= '0';          -- NMI
+                              end if;
+                when others=> null;
+              end case;
+            end if;
+          else
+            bit_count <= (others => '0');
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (keys, rows)
+  variable tmp: std_logic;
+  begin
+    for i in 0 to 4 loop
+      tmp:= '0';
+      for j in 0 to 7 loop
+        tmp:= tmp or (keys(j)(i) and not rows(j));
+      end loop;
+      cols(i) <=  not tmp;
+    end loop;
+  end process;
+
+end architecture;
diff --git a/cores/Spectrum/ps2k_es.vhd b/cores/Spectrum/ps2k_es.vhd
index 3ca7ac9..368765a 100644
--- a/cores/Spectrum/ps2k_es.vhd
+++ b/cores/Spectrum/ps2k_es.vhd
@@ -300,6 +300,8 @@ begin
                   when KEY_F5       => if isctrl='1' and isalt='1' then
                                          nmi <= '0';  -- NMI
                                        end if;
+                  when KEY_F10      => keys(0)(0) <= pressed;
+                                       keys(4)(1) <= pressed; -- Modo gráfico, para pulsar F10 en la BIOS
                   when KEY_KPPUNTO  => if isctrl='1' and isalt='1' then
                                          rst <= '0'; -- reset al hacer ctrl-alt-supr
                                        end if;
diff --git a/cores/Spectrum/ps2k_mcleod.vhd b/cores/Spectrum/ps2k_mcleod.vhd
new file mode 100644
index 0000000..368765a
--- /dev/null
+++ b/cores/Spectrum/ps2k_mcleod.vhd
@@ -0,0 +1,358 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.mapa_es.all;
+
+entity ps2k is port (
+    clk     : in  std_logic;
+    ps2clk  : in  std_logic;
+    ps2data : in  std_logic;
+    rows    : in  std_logic_vector(7 downto 0);
+    cols    : out std_logic_vector(4 downto 0);
+    joy     : out std_logic_vector(4 downto 0);
+    scancode: out std_logic_vector(7 downto 0);
+    rst     : out std_logic;
+    nmi     : out std_logic;
+    mrst    : out std_logic);
+end ps2k;
+
+architecture behavioral of ps2k is
+
+  type    key_matrix  is array (7 downto 0) of std_logic_vector(4 downto 0);
+  signal  keys      : key_matrix;
+  signal  pressed   : std_logic;
+  signal  isctrl    : std_logic;
+  signal  isshift   : std_logic;
+  signal  isalt     : std_logic;
+  signal  isextend  : std_logic;
+  signal  lastclk   : std_logic_vector(4 downto 0);
+  signal  bit_count : unsigned (3 downto 0);
+  signal  shiftreg  : std_logic_vector(8 downto 0);
+  signal  parity    : std_logic;
+
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      rst <= '1';
+      nmi <= '1';
+      mrst <= '1';
+      lastclk <= lastclk(3 downto 0) & ps2clk;
+      if lastclk="11100" and ps2clk='0' then  -- detector de flanco de bajada de PS2CLK
+        if bit_count=0 then
+          parity <= '0';
+          if ps2data='0' then
+            bit_count <= bit_count + 1;
+          end if;
+        else
+          if bit_count<10 then
+            bit_count <= bit_count + 1;
+            shiftreg  <= ps2data & shiftreg(8 downto 1);
+            parity    <= parity xor ps2data;
+          elsif ps2data='1' then
+            bit_count <= (others => '0');
+            if parity = '1' then -- nueva pulsacion completa en shiftreg.
+              pressed <= '1';
+              scancode <= shiftreg(7 downto 0);
+              if isextend='1' and shiftreg(7 downto 0)=KEY_RELEASED then  -- procesar la secuencia E0 F0 key
+                isextend <= '1';
+              else
+                isextend <= '0';
+              end if;
+              case shiftreg(7 downto 0) is  -- detectar secuencias especiales: tecla soltada y tecla extendida
+                when KEY_RELEASED => pressed    <= '0';
+                when KEY_EXTENDED => isextend   <= '1';
+                when others => null;
+              end case;
+              if isextend='0' then  -- teclas no extendidas
+                case shiftreg(7 downto 0) is
+                  when KEY_LSHIFT | 
+                       KEY_RSHIFT   => isshift <= pressed;
+                  when KEY_ALTI     => isalt <= pressed;
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_CTRLI    => keys(0)(0) <= pressed; -- Ctrl izquierdo: (CAPS SHIFT)
+                                       isctrl <= pressed;
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_Z        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(1) <= pressed; -- Z
+                  when KEY_X        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(2) <= pressed; -- X
+                  when KEY_C        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(3) <= pressed; -- C
+                  when KEY_V        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(4) <= pressed; -- V
+                  when KEY_A        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(0) <= pressed; -- A
+                  when KEY_S        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(1) <= pressed; -- S
+                  when KEY_D        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(2) <= pressed; -- D
+                  when KEY_F        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(3) <= pressed; -- F
+                  when KEY_G        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(4) <= pressed; -- G
+                  when KEY_Q        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(0) <= pressed; -- Q
+                  when KEY_W        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(1) <= pressed; -- W
+                  when KEY_E        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(2) <= pressed; -- E
+                  when KEY_R        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(3) <= pressed; -- R
+                  when KEY_T        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(4) <= pressed; -- T
+                  when KEY_1        => if isshift='0' then
+                                         keys(3)(0) <= pressed; -- 1
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(0) <= pressed; -- !
+                                       end if;
+                  when KEY_2        => if isshift='0' then
+                                         keys(3)(1) <= pressed; -- 2
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(5)(0) <= pressed; -- "
+                                       end if;  
+                  when KEY_3        => if isshift='0' then
+                                         keys(3)(2) <= pressed; -- 3
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(2) <= pressed; -- #
+                                       end if;  
+                  when KEY_4        => if isshift='0' then
+                                         keys(3)(3) <= pressed; -- 4
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(3) <= pressed; -- $
+                                       end if;
+                  when KEY_5        => if isshift='0' then
+                                         keys(3)(4) <= pressed; -- 5
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(4) <= pressed; -- $
+                                       end if;
+                  when KEY_0        => if isshift='0' then
+                                         keys(4)(0) <= pressed; -- 0
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(6)(1) <= pressed; -- =
+                                       end if;
+                  when KEY_9        => if isshift='0' then
+                                         keys(4)(1) <= pressed; -- 9
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(4)(1) <= pressed; -- )
+                                       end if;
+                  when KEY_8        => if isshift='0' then
+                                         keys(4)(2) <= pressed; -- 8
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(4)(2) <= pressed; -- (
+                                       end if;
+                  when KEY_7        => if isshift='0' then
+                                         keys(4)(3) <= pressed; -- 7
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(0)(4) <= pressed; -- /
+                                       end if;
+                  when KEY_6        => if isshift='0' then
+                                         keys(4)(4) <= pressed; -- 6
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(4)(4) <= pressed; -- &
+                                       end if;
+                  when KEY_P        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(0) <= pressed; -- P
+                  when KEY_O        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(1) <= pressed; -- O
+                  when KEY_I        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(2) <= pressed; -- I
+                  when KEY_U        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(3) <= pressed; -- U
+                  when KEY_Y        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(4) <= pressed; -- Y
+                  when KEY_ENTER    => keys(6)(0) <= pressed; -- ENTER
+                  when KEY_L        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(1) <= pressed; -- L
+                  when KEY_K        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(2) <= pressed; -- K
+                  when KEY_J        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(3) <= pressed; -- J
+                  when KEY_H        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(4) <= pressed; -- H
+                  when KEY_SPACE    => keys(7)(0) <= pressed; -- SPACE
+                  when KEY_M        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(7)(2) <= pressed; -- M
+                  when KEY_N        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(7)(3) <= pressed; -- N
+                  when KEY_B        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(7)(4) <= pressed; -- B
+                  when KEY_BKSP     => keys(0)(0) <= pressed; -- Backspace (Caps 0)
+                                       keys(4)(0) <= pressed;
+                                       if isctrl='1' and isalt='1' then
+                                         mrst <= '0';
+                                       end if;
+                  when KEY_CPSLK    => keys(0)(0) <= pressed; -- Caps lock (Caps 2)
+                                       keys(3)(1) <= pressed;
+                  when KEY_ESC      => keys(0)(0) <= pressed; -- Break (Caps Space)
+                                       keys(7)(0) <= pressed;
+                  when KEY_F2       => keys(0)(0) <= pressed;
+                                       keys(3)(0) <= pressed; -- EDIT
+                  when KEY_BL       => keys(7)(1) <= pressed;
+                                       keys(1)(2) <= pressed; -- usado con EXT, da \
+                  when KEY_APOS     => keys(7)(1) <= pressed;
+                                       if isshift='0' then 
+                                         keys(4)(3) <= pressed; -- apostrofe '
+                                       else
+                                         keys(0)(3) <= pressed; -- tecla ?
+                                       end if;
+                  when KEY_TAB      => keys(0)(0) <= pressed;
+                                       keys(7)(1) <= pressed; -- modo extendido
+                  when KEY_CORCHA   => keys(7)(1) <= pressed;
+                                       keys(6)(4) <= pressed; -- simbolo ^
+                  when KEY_CORCHC   => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(6)(2) <= pressed; -- simbolo +
+                                       else
+                                         keys(7)(4) <= pressed; -- simbolo *
+                                       end if;
+                  when KEY_LLAVA    => keys(7)(1) <= pressed;
+                                       keys(1)(3) <= pressed; -- llave abierta, con EXT
+                  when KEY_LLAVC    => keys(7)(1) <= pressed;
+                                       keys(5)(0) <= pressed; -- copyright
+                  when KEY_LT       => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(2)(3) <= pressed; -- símbolo <
+                                       else
+                                         keys(2)(4) <= pressed; -- símbolo >
+                                       end if;
+                  when KEY_COMA     => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(7)(3) <= pressed; -- símbolo ,
+                                       else
+                                         keys(5)(1) <= pressed; -- símbolo ;
+                                       end if;
+                  when KEY_PUNTO    => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(7)(2) <= pressed; -- símbolo .
+                                       else
+                                         keys(0)(1) <= pressed; -- símbolo :
+                                       end if;
+                  when KEY_MENOS    => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(6)(3) <= pressed; -- símbolo -                
+                                       else
+                                         keys(4)(0) <= pressed; -- tecla _ (guion bajo)
+                                       end if;
+                  when KEY_F5       => if isctrl='1' and isalt='1' then
+                                         nmi <= '0';  -- NMI
+                                       end if;
+                  when KEY_F10      => keys(0)(0) <= pressed;
+                                       keys(4)(1) <= pressed; -- Modo gráfico, para pulsar F10 en la BIOS
+                  when KEY_KPPUNTO  => if isctrl='1' and isalt='1' then
+                                         rst <= '0'; -- reset al hacer ctrl-alt-supr
+                                       end if;
+                  when KEY_KP4      => joy(1) <= pressed; -- dato entregado por el joystick: izquierda
+                  when KEY_KP6      => joy(0) <= pressed; -- dato entregado por el joystick: derecha
+                  when KEY_KP8      => joy(3) <= pressed; -- dato entregado por el joystick: arriba
+                  when KEY_KP5      => joy(2) <= pressed; -- dato entregado por el joystick: abajo
+                  when others=> null;
+                end case;
+              else -- process extended keys
+                case shiftreg(7 downto 0) is
+                  when KEY_CTRLD    => keys(7)(1) <= pressed; -- Ctrl derecho -> symbol shift
+                                       isctrl <= pressed;
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_ALTGR    => keys(0)(0) <= pressed;
+                                       keys(4)(1) <= pressed; -- Modo gráfico
+                                       isalt <= '1';
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_LEFT     => keys(0)(0) <= pressed; -- Left (Caps 5)
+                                       keys(3)(4) <= pressed;
+                  when KEY_DOWN     => keys(0)(0) <= pressed; -- Down (Caps 6)
+                                       keys(4)(4) <= pressed;
+                  when KEY_UP       => keys(0)(0) <= pressed; -- Up (Caps 7)
+                                       keys(4)(3) <= pressed;
+                  when KEY_RIGHT    => keys(0)(0) <= pressed; -- Right (Caps 8)
+                                       keys(4)(2) <= pressed;
+                  when KEY_SUP      => if isctrl='1' and isalt='1' then
+                                         rst <= '0'; -- reset al hacer ctrl-alt-supr
+                                       end if;
+                  when others => null;
+                end case;
+              end if;  
+            end if;
+          else
+            bit_count <= (others => '0');
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (keys, rows)
+  variable tmp: std_logic;
+  begin
+    for i in 0 to 4 loop
+      tmp:= '0';
+      for j in 0 to 7 loop
+        tmp:= tmp or (keys(j)(i) and not rows(j));
+      end loop;
+      cols(i) <=  not tmp;
+    end loop;
+  end process;
+
+end architecture;
diff --git a/cores/Spectrum/ps2k_uk.vhd b/cores/Spectrum/ps2k_uk.vhd
new file mode 100644
index 0000000..a66d295
--- /dev/null
+++ b/cores/Spectrum/ps2k_uk.vhd
@@ -0,0 +1,397 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.mapa_uk.all;
+
+entity ps2k is port (
+    clk     : in  std_logic;
+    ps2clk  : in  std_logic;
+    ps2data : in  std_logic;
+    rows    : in  std_logic_vector(7 downto 0);
+    cols    : out std_logic_vector(4 downto 0);
+    joy     : out std_logic_vector(4 downto 0);
+    scancode: out std_logic_vector(7 downto 0);
+    rst     : out std_logic;
+    nmi     : out std_logic;
+    mrst    : out std_logic);
+end ps2k;
+
+architecture behavioral of ps2k is
+
+  type    key_matrix  is array (7 downto 0) of std_logic_vector(4 downto 0);
+  signal  keys      : key_matrix;
+  signal  pressed   : std_logic;
+  signal  isctrl    : std_logic;
+  signal  isshift   : std_logic;
+  signal  isalt     : std_logic;
+  signal  isextend  : std_logic;
+  signal  lastclk   : std_logic_vector(4 downto 0);
+  signal  bit_count : unsigned (3 downto 0);
+  signal  shiftreg  : std_logic_vector(8 downto 0);
+  signal  parity    : std_logic;
+
+begin
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      rst <= '1';
+      nmi <= '1';
+      mrst <= '1';
+      lastclk <= lastclk(3 downto 0) & ps2clk;
+      if lastclk="11100" and ps2clk='0' then  -- detector de flanco de bajada de PS2CLK
+        if bit_count=0 then
+          parity <= '0';
+          if ps2data='0' then
+            bit_count <= bit_count + 1;
+          end if;
+        else
+          if bit_count<10 then
+            bit_count <= bit_count + 1;
+            shiftreg  <= ps2data & shiftreg(8 downto 1);
+            parity    <= parity xor ps2data;
+          elsif ps2data='1' then
+            bit_count <= (others => '0');
+            if parity = '1' then -- nueva pulsacion completa en shiftreg.
+              pressed <= '1';
+              scancode <= shiftreg(7 downto 0);
+              if isextend='1' and shiftreg(7 downto 0)=KEY_RELEASED then  -- procesar la secuencia E0 F0 key
+                isextend <= '1';
+              else
+                isextend <= '0';
+              end if;
+              case shiftreg(7 downto 0) is  -- detectar secuencias especiales: tecla soltada y tecla extendida
+                when KEY_RELEASED => pressed    <= '0';
+                when KEY_EXTENDED => isextend   <= '1';
+                when others => null;
+              end case;
+              if isextend='0' then  -- teclas no extendidas
+                case shiftreg(7 downto 0) is
+                  when KEY_LSHIFT | 
+                       KEY_RSHIFT   => isshift <= pressed;
+                  when KEY_ALTI     => isalt <= pressed;
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_CTRLI    => keys(0)(0) <= pressed; -- Ctrl izquierdo: (CAPS SHIFT)
+                                       isctrl <= pressed;
+                  when KEY_Z        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(1) <= pressed; -- Z
+                  when KEY_X        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(2) <= pressed; -- X
+                  when KEY_C        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(3) <= pressed; -- C
+                  when KEY_V        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(0)(4) <= pressed; -- V
+                  when KEY_A        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(0) <= pressed; -- A
+                  when KEY_S        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(1) <= pressed; -- S
+                  when KEY_D        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(2) <= pressed; -- D
+                  when KEY_F        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(3) <= pressed; -- F
+                  when KEY_G        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(1)(4) <= pressed; -- G
+                  when KEY_Q        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(0) <= pressed; -- Q
+                  when KEY_W        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(1) <= pressed; -- W
+                  when KEY_E        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(2) <= pressed; -- E
+                  when KEY_R        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(3) <= pressed; -- R
+                  when KEY_T        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(2)(4) <= pressed; -- T
+                  when KEY_1        => if isshift='0' then
+                                         keys(3)(0) <= pressed; -- 1
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(0) <= pressed; -- !
+                                       end if;
+                  when KEY_2        => if isshift='0' then
+                                         keys(3)(1) <= pressed; -- 2
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(1) <= pressed; -- @
+                                       end if;  
+                  when KEY_3        => if isshift='0' then
+                                         keys(3)(2) <= pressed; -- 3
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(2) <= pressed; -- #
+                                       end if;  
+                  when KEY_4        => if isshift='0' then
+                                         keys(3)(3) <= pressed; -- 4
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(3) <= pressed; -- $
+                                       end if;
+                  when KEY_5        => if isshift='0' then
+                                         keys(3)(4) <= pressed; -- 5
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(3)(4) <= pressed; -- %
+                                       end if;
+                  when KEY_0        => if isshift='0' then
+                                         keys(4)(0) <= pressed; -- 0
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(4)(1) <= pressed; -- )
+                                       end if;
+                  when KEY_9        => if isshift='0' then
+                                         keys(4)(1) <= pressed; -- 9
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(4)(2) <= pressed; -- (
+                                       end if;
+                  when KEY_8        => if isshift='0' then
+                                         keys(4)(2) <= pressed; -- 8
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(7)(4) <= pressed; -- *
+                                       end if;
+                  when KEY_7        => if isshift='0' then
+                                         keys(4)(3) <= pressed; -- 7
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(4)(4) <= pressed; -- &
+                                       end if;
+                  when KEY_6        => if isshift='0' then
+                                         keys(4)(4) <= pressed; -- 6
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(6)(4) <= pressed; -- ^
+                                       end if;
+                  when KEY_P        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(0) <= pressed; -- P
+                  when KEY_O        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(1) <= pressed; -- O
+                  when KEY_I        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(2) <= pressed; -- I
+                  when KEY_U        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(3) <= pressed; -- U
+                  when KEY_Y        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(5)(4) <= pressed; -- Y
+                  when KEY_ENTER    => keys(6)(0) <= pressed; -- ENTER
+                  when KEY_L        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(1) <= pressed; -- L
+                  when KEY_K        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(2) <= pressed; -- K
+                  when KEY_J        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(3) <= pressed; -- J
+                  when KEY_H        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(6)(4) <= pressed; -- H
+                  when KEY_SPACE    => keys(7)(0) <= pressed; -- SPACE
+                  when KEY_M        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(7)(2) <= pressed; -- M
+                  when KEY_N        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(7)(3) <= pressed; -- N
+                  when KEY_B        => if isshift='1' then
+                                         keys(0)(0) <= pressed;
+                                       end if;
+                                       keys(7)(4) <= pressed; -- B
+                  when KEY_BKSP     => keys(0)(0) <= pressed; -- Backspace (Caps 0)
+                                       keys(4)(0) <= pressed;
+                                       if isctrl='1' and isalt='1' then
+                                         mrst <= '0';
+                                       end if;
+                  when KEY_CPSLK    => keys(0)(0) <= pressed; -- Caps lock (Caps 2)
+                                       keys(3)(1) <= pressed;
+                  when KEY_ESC      => keys(0)(0) <= pressed; -- Break (Caps Space)
+                                       keys(7)(0) <= pressed;
+                  when KEY_F2       => keys(0)(0) <= pressed;
+                                       keys(3)(0) <= pressed; -- EDIT
+                  when KEY_BL       => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(1)(2) <= pressed; -- usado con EXT, da \
+                                       else
+                                         keys(1)(1) <= pressed; -- usado con EXT, da |
+                                       end if;
+                  when KEY_GRAVEAC  => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(0)(2) <= pressed; -- tecla POUND
+                                       else
+                                         keys(1)(0) <= pressed; -- usado con EXT, da ~
+                                       end if;
+                  when KEY_TAB      => keys(0)(0) <= pressed;
+                                       keys(7)(1) <= pressed; -- modo extendido
+                  when KEY_CORCHA   => keys(7)(1) <= pressed;
+                                       if isshift='1' then
+                                         keys(1)(3) <= pressed;
+                                       else
+                                         keys(5)(4) <= pressed; -- simbolo [ con EXT
+                                       end if;
+                  when KEY_CORCHC   => keys(7)(1) <= pressed;
+                                       if isshift='1' then
+                                         keys(1)(4) <= pressed;
+                                       else
+                                         keys(5)(3) <= pressed; -- simbolo ] con EXT
+                                       end if;
+                  when KEY_EQUAL    => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(6)(1) <= pressed; -- símbolo =
+                                       else
+                                         keys(6)(2) <= pressed; -- símbolo +
+                                       end if;
+                  when KEY_COMMA    => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(7)(3) <= pressed; -- símbolo ,
+                                       else
+                                         keys(2)(3) <= pressed; -- símbolo <
+                                       end if;
+                  when KEY_DOT      => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(7)(2) <= pressed; -- símbolo .
+                                       else
+                                         keys(2)(4) <= pressed; -- símbolo >
+                                       end if;
+                  when KEY_MINUS    => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(6)(3) <= pressed; -- símbolo -                
+                                       else
+                                         keys(4)(0) <= pressed; -- tecla _ (guion bajo)
+                                       end if;
+                  when KEY_SEMICOL  => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(5)(1) <= pressed; -- tecla ;
+                                       else
+                                         keys(0)(1) <= pressed; -- tecla :
+                                       end if;
+                  when KEY_ACUTEAC  => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(4)(3) <= pressed; -- tecla '
+                                       else
+                                         keys(5)(0) <= pressed; -- tecla "
+                                       end if;
+                  when KEY_SLASH    => keys(7)(1) <= pressed;
+                                       if isshift='0' then
+                                         keys(0)(4) <= pressed;
+                                       else
+                                         keys(0)(3) <= pressed;
+                                       end if;                                       
+                  when KEY_F5       => if isctrl='1' and isalt='1' then
+                                         nmi <= '0';  -- NMI
+                                       end if;
+                  when KEY_F10      => keys(0)(0) <= pressed;
+                                       keys(4)(1) <= pressed; -- Modo gráfico, para pulsar F10 en la BIOS
+                  when KEY_KPDOT    => if isctrl='1' and isalt='1' then
+                                         rst <= '0'; -- reset al hacer ctrl-alt-supr
+                                       else
+                                         keys(7)(1) <= pressed;
+                                         keys(7)(2) <= pressed; -- tecla .                                       
+                                       end if;
+                  when KEY_KP4      => joy(1) <= pressed; -- dato entregado por el joystick: izquierda
+                  when KEY_KP6      => joy(0) <= pressed; -- dato entregado por el joystick: derecha
+                  when KEY_KP8      => joy(3) <= pressed; -- dato entregado por el joystick: arriba
+                  when KEY_KP5      => joy(2) <= pressed; -- dato entregado por el joystick: abajo
+                  when KEY_KP7      => joy(3) <= pressed;
+                                       joy(1) <= pressed; -- dato entregado por el joystick: arriba-izquierda
+                  when KEY_KP9      => joy(3) <= pressed;
+                                       joy(0) <= pressed; -- dato entregado por el joystick: arriba-derecha
+                  when KEY_KP1      => joy(2) <= pressed;
+                                       joy(1) <= pressed; -- dato entregado por el joystick: abajo-izquierda
+                  when KEY_KP3      => joy(2) <= pressed;
+                                       joy(0) <= pressed; -- dato entregado por el joystick: abajo-derecha
+                  when KEY_KPSTAR   => keys(7)(1) <= pressed;
+                                       keys(7)(2) <= pressed; -- tecla *                                       
+                  when KEY_KPMINUS  => keys(7)(1) <= pressed;
+                                       keys(6)(3) <= pressed; -- tecla -
+                  when KEY_KPPLUS   => keys(7)(1) <= pressed;
+                                       keys(6)(2) <= pressed; -- tecla +                                       
+                  when others=> null;
+                end case;
+              else -- process extended keys
+                case shiftreg(7 downto 0) is
+                  when KEY_CTRLD    => keys(7)(1) <= pressed; -- Ctrl derecho -> symbol shift
+                                       isctrl <= pressed;
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_ALTD     => isalt <= '1';
+                                       joy(4) <= pressed; -- dato entregado por el joystick
+                  when KEY_LEFT     => keys(0)(0) <= pressed; -- Left (Caps 5)
+                                       keys(3)(4) <= pressed;
+                  when KEY_DOWN     => keys(0)(0) <= pressed; -- Down (Caps 6)
+                                       keys(4)(4) <= pressed;
+                  when KEY_UP       => keys(0)(0) <= pressed; -- Up (Caps 7)
+                                       keys(4)(3) <= pressed;
+                  when KEY_RIGHT    => keys(0)(0) <= pressed; -- Right (Caps 8)
+                                       keys(4)(2) <= pressed;
+                  when KEY_KPSLASH  => keys(7)(1) <= pressed;
+                                       keys(0)(4) <= pressed; -- tecla /
+                  when KEY_KPENTER  => keys(6)(0) <= pressed; -- tecla ENTER
+                  when KEY_DEL      => if isctrl='1' and isalt='1' then
+                                         rst <= '0'; -- reset al hacer ctrl-alt-supr
+                                       end if;
+                  when others => null;
+                end case;
+              end if;  
+            end if;
+          else
+            bit_count <= (others => '0');
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process (keys, rows)
+  variable tmp: std_logic;
+  begin
+    for i in 0 to 4 loop
+      tmp:= '0';
+      for j in 0 to 7 loop
+        tmp:= tmp or (keys(j)(i) and not rows(j));
+      end loop;
+      cols(i) <=  not tmp;
+    end loop;
+  end process;
+
+end architecture;
diff --git a/cores/Spectrum/relojes.v b/cores/Spectrum/relojes.v
index d21bd03..28a88d9 100644
--- a/cores/Spectrum/relojes.v
+++ b/cores/Spectrum/relojes.v
@@ -54,8 +54,8 @@ module relojes(CLKIN_IN,
                            .O(CLKIN_IBUFG));
    BUFG  CLK0_BUFG_INST (.I(CLK0_BUF), 
                         .O(CLKFB_IN));
-   DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(10.0), .CLKFX_DIVIDE(25), 
-         .CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"), 
+   DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(10.0), .CLKFX_DIVIDE(23), 
+         .CLKFX_MULTIPLY(13), .CLKIN_DIVIDE_BY_2("FALSE"), 
          .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"), 
          .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), 
          .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), 
diff --git a/cores/Spectrum/relojes_pll.v b/cores/Spectrum/relojes_pll.v
new file mode 100644
index 0000000..f85f176
--- /dev/null
+++ b/cores/Spectrum/relojes_pll.v
@@ -0,0 +1,137 @@
+// file: pll.v
+// 
+// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+// Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// CLK_OUT1    28.218      0.000       N/A      341.754        N/A
+//
+//----------------------------------------------------------------------------
+// Input Clock   Input Freq (MHz)   Input Jitter (UI)
+//----------------------------------------------------------------------------
+// primary              50            0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "pll,clk_wiz_v1_8,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=true,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=true}" *)
+module pll
+ (// Clock in ports
+  input wire        CLK_IN1,
+  // Clock out ports
+  output wire       CLK_OUT1,
+  // Dynamic reconfiguration ports
+  input wire        PROGCLK,
+  input wire        PROGDATA,
+  input wire        PROGEN,
+  output wire       PROGDONE
+ );
+
+  // Input buffering
+  //------------------------------------
+  wire clkin1;
+  IBUFG clkin1_buf
+   (.O (clkin1),
+    .I (CLK_IN1));
+
+
+  // Clocking primitive
+  //------------------------------------
+  // Instantiation of the DCM primitive
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+  wire        locked_int;
+  wire [2:1]  status_int;
+  wire        clkfx;
+  wire        clkfx180_unused;
+  wire        clkfxdv_unused;
+
+  DCM_CLKGEN
+  #(.CLKFXDV_DIVIDE        (2),
+    .CLKFX_DIVIDE          (102),
+    .CLKFX_MULTIPLY        (57),
+    .SPREAD_SPECTRUM       ("NONE"),
+    .STARTUP_WAIT          ("FALSE"),
+    .CLKIN_PERIOD          (20.000),
+    .CLKFX_MD_MAX          (0.000))
+   dcm_clkgen_inst
+    // Input clock
+   (.CLKIN                 (clkin1),
+    // Output clocks
+    .CLKFX                 (clkfx),
+    .CLKFX180              (clkfx180_unused),
+    .CLKFXDV               (clkfxdv_unused),
+    // Ports for dynamic reconfiguration
+    .PROGCLK               (PROGCLK),
+    .PROGDATA              (PROGDATA),
+    .PROGEN                (PROGEN),
+    .PROGDONE              (PROGDONE),
+    // Other control and status signals
+    .FREEZEDCM             (1'b0),
+    .LOCKED                (locked_int),
+    .STATUS                (status_int),
+    .RST                   (1'b0));
+
+
+  // Output buffering
+  //-----------------------------------
+
+
+  BUFG clkout1_buf
+   (.O   (CLK_OUT1),
+    .I   (clkfx));
+
+
+
+
+endmodule
diff --git a/cores/Spectrum/rom.v b/cores/Spectrum/rom.v
index 061e7ed..38d4599 100644
--- a/cores/Spectrum/rom.v
+++ b/cores/Spectrum/rom.v
@@ -21,8 +21,6 @@
 module rom (
     input wire clk,
     input wire [13:0] a,
-    input wire we,
-    input wire [7:0] din,
     output reg [7:0] dout
     );
 
@@ -38,8 +36,6 @@ module rom (
    end
    
    always @(posedge clk) begin
-     if (we)
-        mem[a[5:0]] <= din;
      dout <= mem[a[5:0]];
    end
 endmodule
diff --git a/cores/Spectrum/tb_ula.v b/cores/Spectrum/tb_ula.v
index c6edf48..d93a11a 100644
--- a/cores/Spectrum/tb_ula.v
+++ b/cores/Spectrum/tb_ula.v
@@ -55,7 +55,7 @@ module tb_ula;
 	wire y_n;
 
 	// Instantiate the Unit Under Test (UUT)
-	ula uut (
+	ula_radas uut (
 		.clk14(clk14), 
 		.wssclk(wssclk), 
 		.rst_n(rst_n), 
@@ -74,6 +74,9 @@ module tb_ula;
 		.kbd(kbd), 
 		.mic(mic), 
 		.spk(spk), 
+        .issue2_keyboard(1'b0),
+        .timming(1'b0),
+        .disable_contention(1'b0),
 		.clkay(clkay), 
 		.clkdac(clkdac), 
 		.clkkbd(clkkbd), 
@@ -94,7 +97,7 @@ module tb_ula;
 		clk14 = 0;
 		wssclk = 0;
 		rst_n = 0;
-		a = 0;
+		a = 16'h4000;
 		mreq_n = 1;
 		iorq_n = 1;
 		rd_n = 1;
diff --git a/cores/Spectrum/tld_zxuno.v b/cores/Spectrum/tld_zxuno.v
index 3361827..008226f 100644
--- a/cores/Spectrum/tld_zxuno.v
+++ b/cores/Spectrum/tld_zxuno.v
@@ -33,6 +33,8 @@ module tld_zxuno (
    input wire dataps2,
    output wire audio_out_left,
    output wire audio_out_right,
+   output wire stdn,
+   output wire stdnb,
    
    output wire [18:0] sram_addr,
    inout wire [7:0] sram_data,
@@ -47,24 +49,38 @@ module tld_zxuno (
    output wire sd_clk,     
    output wire sd_mosi,    
    input wire sd_miso,
+   output wire testled,   // nos servirá como testigo de uso de la SPI
    
-//   output wire ss,
-//   output wire sclk,
-//   output wire mosi,
-//   output wire miso,
-   
-   output wire testled   // nos servirá como testigo de uso de la SPI
+   input wire joyup,
+   input wire joydown,
+   input wire joyleft,
+   input wire joyright,
+   input wire joyfire
    );
 
    wire wssclk,sysclk;
-   relojes los_relojes_del_sistema (
-    .CLKIN_IN(clk50mhz), 
-    .CLKDV_OUT(wssclk), //  5MHz
-    .CLKFX_OUT(sysclk), // 28MHz 
-    .CLKIN_IBUFG_OUT(), 
-    .CLK0_OUT(), 
-    .LOCKED_OUT()
-    );
+//   relojes los_relojes_del_sistema (
+//    .CLKIN_IN(clk50mhz), 
+//    .CLKDV_OUT(wssclk), //  5MHz
+//    .CLKFX_OUT(sysclk), // 28MHz 
+//    .CLKIN_IBUFG_OUT(), 
+//    .CLK0_OUT(), 
+//    .LOCKED_OUT()
+//    );
+
+	assign wssclk = 1'b0;  // de momento, sin WSS
+	assign stdn = 1'b0;  // fijar norma PAL
+	assign stdnb = 1'b1; // y conectamos reloj PAL
+   pll reloj_maestro
+   (// Clock in ports
+    .CLK_IN1            (clk50mhz),      // IN
+    // Clock out ports
+    .CLK_OUT1           (sysclk),     // OUT
+    // Dynamic reconfiguration ports
+    .PROGCLK            (1'b0),      // IN
+    .PROGDATA           (1'b0),     // IN
+    .PROGEN             (1'b0),       // IN
+    .PROGDONE           ());    // OUT
 
    wire audio_out;
    assign audio_out_left = audio_out;
@@ -95,14 +111,23 @@ module tld_zxuno (
     .sd_cs_n(sd_cs_n),
     .sd_clk(sd_clk),
     .sd_mosi(sd_mosi),
-    .sd_miso(sd_miso)
+    .sd_miso(sd_miso),
+    
+    .joyup(joyup),
+    .joydown(joydown),
+    .joyleft(joyleft),
+    .joyright(joyright),
+    .joyfire(joyfire)
     );
-    
-//    assign ss = sd_cs_n;
-//    assign sclk = sd_clk;
-//    assign mosi = sd_mosi;
-//    assign miso = sd_miso;
-    
+       
     assign testled = (!flash_cs_n || !sd_cs_n);
+//    reg [21:0] monoestable = 22'hFFFFFF;
+//    always @(posedge sysclk) begin
+//        if (!flash_cs_n || !sd_cs_n)
+//            monoestable <= 0;
+//        else if (monoestable[21] == 1'b0)
+//            monoestable <= monoestable + 1;
+//    end
+//    assign testled = ~monoestable[21];
 
 endmodule
diff --git a/cores/Spectrum/tv80_to_t80_wrapper.v b/cores/Spectrum/tv80_to_t80_wrapper.v
index a65cadf..3a6a8f2 100644
--- a/cores/Spectrum/tv80_to_t80_wrapper.v
+++ b/cores/Spectrum/tv80_to_t80_wrapper.v
@@ -62,7 +62,13 @@ module tv80n_wrapper (
 		.HALT_n(halt_n),
 		.BUSAK_n(busak_n),
 		.A(A),
-		.D(d)
+		.D(d),
+		
+		.SavePC(),
+		.SaveINT(),
+		.RestorePC(16'h0000),
+		.RestoreINT(8'h00),
+		.RestorePC_n(1'b1)
 	);
 	
 	assign dout = d; 
diff --git a/cores/Spectrum/ula_radas.v b/cores/Spectrum/ula_radas.v
index 3f9b1ab..e109ec7 100644
--- a/cores/Spectrum/ula_radas.v
+++ b/cores/Spectrum/ula_radas.v
@@ -51,6 +51,9 @@ module ula_radas (
     output wire clkdac,
     output wire clkkbd,
     input wire issue2_keyboard,
+    input wire timming,
+    input wire disable_contention,
+    input wire access_to_contmem,
 
     // Video
 	 output wire [2:0] r,
@@ -60,6 +63,13 @@ module ula_radas (
     output wire y_n
     );
 
+    parameter
+      BHPIXEL =  0,
+      EHPIXEL =  255,
+      BVPIXEL =  0,
+      EVPIXEL =  191,
+      BVSYNC  =  248;    
+
 	 // RGB inputs to sync module
 	 reg [2:0] ri;
 	 reg [2:0] gi;
@@ -77,41 +87,34 @@ module ula_radas (
     assign clkay = hc[0];
     assign clkkbd = hc[4];
 
-	 pal_sync_generator_progressive syncs (
+	 pal_sync_generator_sinclair syncs (
     .clk(clk7),
-	 .wssclk(wssclk),
-	 .ri(ri),
-	 .gi(gi),
-	 .bi(bi),
-	 .hcnt(hc),
-	 .vcnt(vc),
+    .timming(timming),
+    .ri(ri),
+    .gi(gi),
+    .bi(bi),
+    .hcnt(hc),
+    .vcnt(vc),
     .ro(r),
     .go(g),
     .bo(b),
     .csync(csync)
     );
 
-    parameter
-      BHPIXEL =  0,
-      EHPIXEL =  255,
-      BBORDER =  256,
-      EBORDER =  320,
-      BHBLANK =  320,
-      EHBLANK =  416,
-      BHSYNC  =  344,
-      EHSYNC  =  376,
-      BBORDEL =  416,
-      EBORDEL =  447,
-      BVPIXEL =  0,
-      EVPIXEL =  191,
-      BBORDED =  192,
-      EBORDED =  247,
-      BVPERIOD = 248,
-      EVPERIOD = 255,
-      BVSYNC  =  248,
-      EVSYNC  =  251,
-      BBORDEU =  256,
-      EBORDEU =  311;    
+//	 pal_sync_generator_progressive syncs (
+//    .clk(clk7),
+//    .wssclk(wssclk),
+//    .ri(ri),
+//    .gi(gi),
+//    .bi(bi),
+//    .hcnt(hc),
+//    .vcnt(vc),
+//    .ro(r),
+//    .go(g),
+//    .bo(b),
+//    .csync(csync)
+//    );
+
 
 ///////////////////////////////////////////////
 // ULA datapath
@@ -351,8 +354,7 @@ module ula_radas (
          CA <= hc[7:3];
    end
 
-   // VRAM Address generation
-   
+   // VRAM Address generation   
    wire [8:0] hcd = hc + 9'hFF8;  // hc delayed 8 ticks
    always @* begin
      if (!RadasEnabled) begin
@@ -399,8 +401,10 @@ module ula_radas (
          if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin  // VidEN_n is low here: paper area
             VideoEnable = 1'b1;
             if (hc[2:0]==3'd4) begin
-               SerializerLoad = 1'b1;  // updated every 8 pixel clocks, if we are in paper area
+                SerializerLoad = 1'b1;  // updated every 8 pixel clocks, if we are in paper area
             end
+         end
+         if (hc>=BHPIXEL && hc<=EHPIXEL && vc>=BVPIXEL && vc<=EVPIXEL) begin
             if (hc[3:0]==4'd8 || hc[3:0]==4'd12) begin
                BitmapAddr = 1'b1;
             end
@@ -474,12 +478,20 @@ module ula_radas (
       end
    end
 
+	reg post_processed_ear;  // EAR signal after being altered by the keyboard current issue
+	always @* begin
+		if (issue2_keyboard)
+			post_processed_ear = ear ^ (spk | mic);
+		else
+			post_processed_ear = ear ^ spk;
+    end
+
    // Z80 gets values from registers (or floating bus)
    always @* begin
       dout = 8'hFF;
       if (iorq_n==1'b0 && rd_n==1'b0) begin
          if (a[0]==1'b0)
-            dout = {1'b1,issue2_keyboard^ear,1'b1,kbd};
+            dout = {1'b1,post_processed_ear,1'b1,kbd};
          else if (a==ULAPLUSADDR)
             dout = {1'b0,PaletteReg};
          else if (a==ULAPLUSDATA && PaletteReg[6]==1'b0)
@@ -487,10 +499,8 @@ module ula_radas (
          else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1)
             dout = {7'b0000000,ConfigReg};
          else if (a[7:0]==TIMEXPORT) begin
-            if (BitmapAddr)
-               dout = BitmapData;
-            else if (AttrAddr)  
-               dout = AttrData;   // floating bus
+            if (BitmapAddr || AttrAddr)
+               dout = vramdata;
             else
                dout = 8'hFF;
          end
@@ -499,58 +509,101 @@ module ula_radas (
          
    // INT generation
    always @* begin
-      if (vc==BVSYNC && hc>=0 && hc<=63) // 32 T-states INT pulse width
+      if (vc==BVSYNC && hc>=2 && hc<=65) // 32 T-states INT pulse width
          int_n = 1'b0;
       else
          int_n = 1'b1;
    end
    
+
+///////////////////////////////////
+// AUXILIARY SIGNALS FOR CONTENTION CONTROL
+///////////////////////////////////
+   wire iorequla = !iorq_n && (a[0]==0);
+   wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA);
+   wire ioreqall_n = !(iorequlaplus || iorequla);
+
+   reg Border_n;
+   always @* begin
+     if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
+        Border_n = 1;
+    else
+        Border_n = 0;
+	end
+
 ///////////////////////////////////
 // CPU CLOCK GENERATION (Altwasser method)
 ///////////////////////////////////
 
-`define MASTERCPUCLK clk7
+//`define MASTERCPUCLK clk7
+//   reg ioreqtw3 = 0;
+//   reg mreqt23 = 0;
+//    wire N1y2 = ~access_to_contmem | ioreqall_n;
+//    wire N3 = hc[3:0]>=4'd4;
+//    wire N4 = ~Border_n | ~ioreqtw3 | ~mreqt23 | ~cpuclk;
+//    wire N5 = ~(N1y2 | N3 | N4);
+//    wire N6 = ~(hc[3:0]>=4'd4 | ~Border_n | ~cpuclk | ioreqall_n | ~ioreqtw3);
+//    assign cpuclk = (hc[0] | N5 | N6);
+//    
+//	always @(posedge cpuclk) begin
+//       ioreqtw3 <= ioreqall_n;
+//       mreqt23 <= mreq_n;
+//	end
 
-   reg CPUInternalClock = 0;
-	reg ioreqtw3 = 0;
-	reg mreqt23 = 0;
+//	wire Nor1 = (~access_to_contmem & ioreqall_n) | (hc[3:0]<4'd12) | 
+//                (~Border_n | ~ioreqtw3 | ~cpuclk | ~mreqt23);
+//	wire Nor2 = (hc[3:0]<4'd4) | ~Border_n | ~cpuclk | ioreqall_n | ~ioreqtw3;
+//	wire CLKContention = ~Nor1 | ~Nor2;
+//
+//	always @(posedge cpuclk) begin
+//      if (!CLKContention) begin
+//         ioreqtw3 <= ioreqall_n;
+//         mreqt23 <= mreq_n;
+//      end
+//	end
+//
+//   assign cpuclk = (!CLKContention || RadasEnabled || disable_contention)? hc[0] : 1'b1;
+//
+//  reg CPUInternalClock = 0;
+//	always @(posedge `MASTERCPUCLK) begin
+//		if (!CLKContention || RadasEnabled || disable_contention)
+//			CPUInternalClock <= ~CPUInternalClock;
+//	   else
+//		   CPUInternalClock <= 1'b1;
+//   end
+//
+//   assign cpuclk = CPUInternalClock;
 
-   wire iorequla = !iorq_n && (a[0]==0);
-	wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA);
-	wire ioreqall_n = !(iorequlaplus || iorequla);
 
-	reg Border_n;
-	always @(*) begin
-		if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
-			Border_n = 1;
-		else
-			Border_n = 0;
-	end
-	wire Nor1 = (~(a[14] | ~ioreqall_n)) | 
-	            (~(~a[15] | ~ioreqall_n)) | 
-					( hc[3:0]<4'd4 ) | 
-					(~Border_n | ~ioreqtw3 | ~cpuclk | ~mreqt23);
-	wire Nor2 = ( hc[3:0]<4'd4 ) | 
-	            ~Border_n |
-					~cpuclk |
-					ioreqall_n |
-					~ioreqtw3;
-	wire CLKContention = ~Nor1 | ~Nor2;
 
-	always @(posedge cpuclk) begin
-      if (!CLKContention) begin
-         ioreqtw3 <= ioreqall_n;
-         mreqt23 <= mreq_n;
-      end
-	end
+///////////////////////////////////
+// CPU CLOCK GENERATION (CSmith method)
+///////////////////////////////////
 
-	always @(posedge `MASTERCPUCLK) begin
-		if (!CLKContention || RadasEnabled)
-			CPUInternalClock = ~CPUInternalClock;
-	   else
-		   CPUInternalClock = 1'b1;
-   end
-
-   assign cpuclk = CPUInternalClock;
+    reg MayContend_n;
+    always @* begin  // esto era negedge clk7 en el esquemático
+       if (hc[3:0]>4'd3 && Border_n==1'b1)
+         MayContend_n <= 1'b0;
+       else
+         MayContend_n <= 1'b1;
+    end
+    
+    reg CauseContention_n;
+    always @* begin
+        if ((access_to_contmem || !ioreqall_n) && !RadasEnabled && !disable_contention)
+            CauseContention_n = 1'b0;
+        else
+            CauseContention_n = 1'b1;
+    end
+    
+    reg CancelContention = 1'b1;
+    always @(posedge cpuclk) begin
+        if (!mreq_n || !ioreqall_n)
+            CancelContention <= 1'b1;
+        else
+            CancelContention <= 1'b0;
+    end
+    
+    assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0];
 
 endmodule
diff --git a/cores/Spectrum/zxuno.gise b/cores/Spectrum/zxuno.gise
index aeb1b10..c781d58 100644
--- a/cores/Spectrum/zxuno.gise
+++ b/cores/Spectrum/zxuno.gise
@@ -22,178 +22,9 @@
   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="zxuno.xise"/>
 
   <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
-    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_zxuno.bgn" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="tld_zxuno.bit" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="tld_zxuno.bld"/>
-    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="tld_zxuno.cmd_log"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="tld_zxuno.drc" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="tld_zxuno.lso"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_zxuno.ncd" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="tld_zxuno.ngc"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="tld_zxuno.ngd"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="tld_zxuno.ngr"/>
-    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="tld_zxuno.pad"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="tld_zxuno.par" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="tld_zxuno.pcf" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tld_zxuno.prj"/>
-    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="tld_zxuno.ptwx"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="tld_zxuno.stx"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="tld_zxuno.syr"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="tld_zxuno.twr" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="tld_zxuno.twx" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="tld_zxuno.unroutes" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_zxuno.ut" xil_pn:subbranch="FPGAConfiguration"/>
-    <file xil_pn:fileType="FILE_XPI" xil_pn:name="tld_zxuno.xpi"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="tld_zxuno.xst"/>
-    <file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_zxuno_envsettings.html"/>
     <file xil_pn:fileType="FILE_NCD" xil_pn:name="tld_zxuno_guide.ncd" xil_pn:origination="imported"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_zxuno_map.map" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_zxuno_map.mrp" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_zxuno_map.ncd" xil_pn:subbranch="Map"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="tld_zxuno_map.ngm" xil_pn:subbranch="Map"/>
-    <file xil_pn:fileType="FILE_PSR" xil_pn:name="tld_zxuno_map.psr"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_map.xrpt"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_ngdbuild.xrpt"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="tld_zxuno_pad.csv" xil_pn:subbranch="Par"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="tld_zxuno_pad.txt" xil_pn:subbranch="Par"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_par.xrpt"/>
-    <file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_zxuno_summary.html"/>
-    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="tld_zxuno_summary.xml"/>
-    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="tld_zxuno_usage.xml"/>
-    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_zxuno_xst.xrpt"/>
-    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
-    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
-    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
-    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
-    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
   </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3524997284752945764" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7188828471653365900" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9129001642772221986" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1417646268" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="9132046586730190230" xil_pn:start_ts="1417646268">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418128311" xil_pn:in_ck="8495362880660263435" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8572459946363546403" xil_pn:start_ts="1418128204">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
-      <outfile xil_pn:name="tld_zxuno.cmd_log"/>
-      <outfile xil_pn:name="tld_zxuno.lso"/>
-      <outfile xil_pn:name="tld_zxuno.ngc"/>
-      <outfile xil_pn:name="tld_zxuno.ngr"/>
-      <outfile xil_pn:name="tld_zxuno.prj"/>
-      <outfile xil_pn:name="tld_zxuno.stx"/>
-      <outfile xil_pn:name="tld_zxuno.syr"/>
-      <outfile xil_pn:name="tld_zxuno.xst"/>
-      <outfile xil_pn:name="tld_zxuno_envsettings.html"/>
-      <outfile xil_pn:name="tld_zxuno_summary.html"/>
-      <outfile xil_pn:name="tld_zxuno_xst.xrpt"/>
-      <outfile xil_pn:name="webtalk_pn.xml"/>
-      <outfile xil_pn:name="xst"/>
-    </transform>
-    <transform xil_pn:end_ts="1417648484" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8119187138760779895" xil_pn:start_ts="1417648484">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418128318" xil_pn:in_ck="6001021794932523067" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5213230963878834957" xil_pn:start_ts="1418128311">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="_ngo"/>
-      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
-      <outfile xil_pn:name="tld_zxuno.bld"/>
-      <outfile xil_pn:name="tld_zxuno.cmd_log"/>
-      <outfile xil_pn:name="tld_zxuno.ngd"/>
-      <outfile xil_pn:name="tld_zxuno_ngdbuild.xrpt"/>
-      <outfile xil_pn:name="xlnx_auto_0_xdb"/>
-    </transform>
-    <transform xil_pn:end_ts="1418128564" xil_pn:in_ck="6001021794932523068" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1827537523135263760" xil_pn:start_ts="1418128318">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
-      <outfile xil_pn:name="tld_zxuno.pcf"/>
-      <outfile xil_pn:name="tld_zxuno_map.map"/>
-      <outfile xil_pn:name="tld_zxuno_map.mrp"/>
-      <outfile xil_pn:name="tld_zxuno_map.ncd"/>
-      <outfile xil_pn:name="tld_zxuno_map.ngm"/>
-      <outfile xil_pn:name="tld_zxuno_map.psr"/>
-      <outfile xil_pn:name="tld_zxuno_map.xrpt"/>
-      <outfile xil_pn:name="tld_zxuno_summary.xml"/>
-      <outfile xil_pn:name="tld_zxuno_usage.xml"/>
-    </transform>
-    <transform xil_pn:end_ts="1418128614" xil_pn:in_ck="2351177188178857301" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="9217742489531529416" xil_pn:start_ts="1418128564">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
-      <outfile xil_pn:name="tld_zxuno.ncd"/>
-      <outfile xil_pn:name="tld_zxuno.pad"/>
-      <outfile xil_pn:name="tld_zxuno.par"/>
-      <outfile xil_pn:name="tld_zxuno.ptwx"/>
-      <outfile xil_pn:name="tld_zxuno.unroutes"/>
-      <outfile xil_pn:name="tld_zxuno.xpi"/>
-      <outfile xil_pn:name="tld_zxuno_pad.csv"/>
-      <outfile xil_pn:name="tld_zxuno_pad.txt"/>
-      <outfile xil_pn:name="tld_zxuno_par.xrpt"/>
-    </transform>
-    <transform xil_pn:end_ts="1418128641" xil_pn:in_ck="-3822709731627043894" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="335873702051717080" xil_pn:start_ts="1418128614">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
-      <outfile xil_pn:name="tld_zxuno.bgn"/>
-      <outfile xil_pn:name="tld_zxuno.bit"/>
-      <outfile xil_pn:name="tld_zxuno.drc"/>
-      <outfile xil_pn:name="tld_zxuno.ut"/>
-      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
-      <outfile xil_pn:name="webtalk.log"/>
-      <outfile xil_pn:name="webtalk_pn.xml"/>
-    </transform>
-    <transform xil_pn:end_ts="1418128614" xil_pn:in_ck="6001021794932522936" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1418128603">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
-      <outfile xil_pn:name="tld_zxuno.twr"/>
-      <outfile xil_pn:name="tld_zxuno.twx"/>
-    </transform>
-  </transforms>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
 
 </generated_project>
diff --git a/cores/Spectrum/zxuno.v b/cores/Spectrum/zxuno.v
index c0fae5b..a57e471 100644
--- a/cores/Spectrum/zxuno.v
+++ b/cores/Spectrum/zxuno.v
@@ -51,7 +51,14 @@ module zxuno (
     output wire sd_cs_n,    
     output wire sd_clk,     
     output wire sd_mosi,    
-    input wire sd_miso      
+    input wire sd_miso,
+    
+    // DB9 JOYSTICK
+   input wire joyup,
+   input wire joydown,
+   input wire joyleft,
+   input wire joyright,
+   input wire joyfire
     );
 
    // Señales de la CPU
@@ -101,21 +108,27 @@ module zxuno (
    wire [4:0] kbdcol;
    wire [7:0] kbdrow;
    wire mrst_n,rst_n;  // los dos resets suministrados por el teclado
-   wire issue2_keyboard;
    wire [7:0] scancode;  // scancode original desde el teclado PC
    wire read_scancode = (zxuno_addr==8'h04 && zxuno_regrd);
    
    // Interfaz kempston
    wire [4:0] kbd_joy;
+   wire [4:0] db9_joy = {~joyfire, ~joyup, ~joydown, ~joyleft, ~joyright};
    wire oe_n_kempston = !(!iorq_n && !rd_n && cpuaddr[7:0]==8'd31);
    
+   // Configuración ULA
+   wire timming_ula;
+   wire issue2_keyboard;
+   wire disable_contention;
+   wire access_to_screen;
+   
    assign kbdrow = cpuaddr[15:8];  // las filas del teclado son A8-A15 de la CPU
 
    // Asignación de dato para la CPU segun la decodificación de todos los dispositivos
    // conectados a ella.
    assign cpudin = (oe_n_romyram==1'b0)?        memory_dout :
                    (oe_n_ay==1'b0)?             ay_dout :
-                   (oe_n_kempston==1'b0)?       {3'b000,kbd_joy} :
+                   (oe_n_kempston==1'b0)?       {3'b000,(kbd_joy/* | db9_joy*/)} :
                    (oe_n_zxunoaddr==1'b0)?      zxuno_addr_to_cpu :
                    (oe_n_spi==1'b0)?            spi_dout :
                    (read_scancode==1'b1)?       scancode :
@@ -156,6 +169,7 @@ module zxuno (
 
 	 // CPU interface
 	 .a(cpuaddr),
+     .access_to_contmem(access_to_screen),
 	 .mreq_n(mreq_n),
 	 .iorq_n(iorq_n),
 	 .rd_n(rd_n),
@@ -163,7 +177,7 @@ module zxuno (
 	 .cpuclk(cpuclk),
 	 .int_n(int_n),
 	 .din(cpudout),
-    .dout(ula_dout),
+     .dout(ula_dout),
 
     // VRAM interface
 	 .va(vram_addr),  // 16KB videoram
@@ -178,13 +192,14 @@ module zxuno (
     .clkdac(clkdac),
     .clkkbd(clkkbd),
     .issue2_keyboard(issue2_keyboard),
+    .timming(timming_ula),
+    .disable_contention(disable_contention),
 
     // Video
 	 .r(r),
 	 .g(g),
 	 .b(b),
-	 .csync(csync),
-    .y_n()
+	 .csync(csync)
     );
 
    zxunoregs addr_reg_zxuno (
@@ -252,6 +267,9 @@ module zxuno (
       .vramaddr(vram_addr),
       .vramdout(vram_dout),
       .issue2_keyboard_enabled(issue2_keyboard),
+      .timming_ula(timming_ula),
+      .disable_contention(disable_contention),
+      .access_to_screen(access_to_screen),
    
    // Interface para registros ZXUNO
       .addr(zxuno_addr),
diff --git a/cores/Spectrum/zxuno.xise b/cores/Spectrum/zxuno.xise
index 8a45f7c..2c017ad 100644
--- a/cores/Spectrum/zxuno.xise
+++ b/cores/Spectrum/zxuno.xise
@@ -15,14 +15,6 @@
   <version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="pal_sync_generator_progressive.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="ula.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
     <file xil_pn:name="tb_ula.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="PostMapSimulation"/>
@@ -37,17 +29,7 @@
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
     </file>
-    <file xil_pn:name="mapa_teclado_es.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="ps2k.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation"/>
-      <association xil_pn:name="Implementation"/>
-    </file>
-    <file xil_pn:name="relojes.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="Implementation"/>
-    </file>
+    <file xil_pn:name="mapa_teclado_es.vhd" xil_pn:type="FILE_VHDL"/>
     <file xil_pn:name="T80.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
@@ -134,6 +116,24 @@
       <association xil_pn:name="BehavioralSimulation"/>
       <association xil_pn:name="Implementation"/>
     </file>
+    <file xil_pn:name="pal_sync_generator_sinclair.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="relojes_pll.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
+    <file xil_pn:name="ps2k_av.vhd" xil_pn:type="FILE_VHDL"/>
+    <file xil_pn:name="ps2k_mcleod.vhd" xil_pn:type="FILE_VHDL"/>
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    <file xil_pn:name="ps2k_uk.vhd" xil_pn:type="FILE_VHDL">
+    </file>
+    <file xil_pn:name="mapa_teclado_uk.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation"/>
+      <association xil_pn:name="Implementation"/>
+    </file>
   </files>
 
   <properties>
@@ -145,7 +145,7 @@
     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -169,7 +169,7 @@
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="10" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -381,13 +381,13 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_ula" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_ula" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_zxuno" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_zxuno" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
@@ -401,7 +401,7 @@
     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_ula" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_zxuno" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
diff --git a/cores/Spectrum/zxunoregs.v b/cores/Spectrum/zxunoregs.v
index 4d4db42..86e2694 100644
--- a/cores/Spectrum/zxunoregs.v
+++ b/cores/Spectrum/zxunoregs.v
@@ -69,7 +69,7 @@ module zxunoregs (
 
 Addr  |   Dir  |  Description
 ------+--------+----------------------------------------------
-$00   |   R/W  | Master configuration: LOCK 0 0 ISSUE2 DISNMI ENDIV ENBOOT  . ENDIV=1 enables DIVMMC . ENBOOT=1 boot ROM in use
+$00   |   R/W  | Master configuration: LOCK 0 0 TIMMING ISSUE2 DISNMI ENDIV ENBOOT  . ENDIV=1 enables DIVMMC . ENBOOT=1 boot ROM in use
 $01   |   R/W  | Master memory mapper: 0 0 0 B4 B2 B2 B1 B0    . B4-B0: 16K bank to map onto $C000-$FFFF. 
       |        |                                                        System RAM (128K) uses banks 0-7
       |        |                                                        System ROM (64K) is located from bank 8 to bank 11.
@@ -77,7 +77,7 @@ $01   |   R/W  | Master memory mapper: 0 0 0 B4 B2 B2 B1 B0    . B4-B0: 16K bank
       |        |                                                        DIVMMC RAM is located at banks 13-14 (32KB)
 $02   |   R/W  | Flash SPI port
 $03   |   R/W  | Flash SPI CS pin
-$04   |   R/W  | R: returbns the last scancode issued by the keyboard. W: sends command to the keyboard (not yet impl.)
+$04   |   R/W  | R: returns the last scancode issued by the keyboard. W: sends command to the keyboard (not yet impl.)
 
 */
 endmodule