mirror of https://github.com/zxdos/zxuno.git
semiworking dos
This commit is contained in:
byrtolet
parent
5fa24a6531
commit
e575738919
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@ -9,7 +9,8 @@ vhdl work "../source/YM2149_linmix.vhd"
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vhdl work "../source/ula.vhd"
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vhdl work "../source/T65/T65.vhd"
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vhdl work "../source/scan_converter.vhd"
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vhdl work "../source/rom_oa.vhd"
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vhdl work "../source/pravetz.vhd"
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#vhdl work "../source/rom_oa.vhd"
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vhdl work "../source/ram48k.vhd"
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vhdl work "../source/m6522.vhd"
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vhdl work "../source/keyboard/keyboard.vhd"
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@ -21,5 +22,6 @@ vhdl work "../source/onebitadc.vhd"
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vhdl work "../source/clkdiv.vhd"
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vhdl work "../source/controller_8dos.vhd"
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vhdl work "../source/dos8rom.vhd"
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#vhdl work "../source/spi_controller.vhd"
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#vhdl work "../source/disk_ii.vhd"
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vhdl work "../source/spi_controller.vhd"
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vhdl work "../source/disk_ii.vhd"
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vhdl work "../source/debounce.vhd"
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@ -15,7 +15,24 @@ entity controller_8dos is
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O_MAPn : out std_logic;
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A : in std_logic_vector(15 downto 0);
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D_IN : in std_logic_vector(7 downto 0); -- From 6502
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D_OUT : out std_logic_vector(7 downto 0) -- To 6502
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D_OUT : out std_logic_vector(7 downto 0); -- To 6502
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-- indication
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disk_a_on : out std_logic;
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disk_cur_TRACK: out std_logic_vector(5 downto 0); -- Current track (0-34)
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disk_track_addr: out std_logic_vector(13 downto 0);
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IMAGE_NUMBER_out : out std_logic_vector(9 downto 0);
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track_ok : out std_logic; -- 0 when disk is active else 1
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IMAGE_UP :in std_logic;
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IMAGE_DOWN :in std_logic;
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-- sd card
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SD_DAT : in std_logic;
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SD_DAT3 : out std_logic;
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SD_CMD : out std_logic;
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SD_CLK : out std_logic
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);
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end controller_8dos;
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@ -25,12 +42,55 @@ architecture imp of controller_8dos is
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signal s_extension: std_logic;
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signal rom_out: std_logic_vector(7 downto 0);
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signal IO_CONTROLn_int : std_logic;
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signal disk_select : std_logic;
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signal CUR_PHI_2:std_logic;
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signal OLD_PHI_2:std_logic;
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signal rising_PHI_2:std_logic;
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signal falling_PHI_2:std_logic;
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begin
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signal disk_D_OUT : std_logic_vector(7 downto 0);
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-- connection between spi_controller & disk_ii
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signal IMAGE_NUMBER : unsigned(9 downto 0);
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signal TRACK : unsigned(5 downto 0);
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signal TRACK_ADDR : unsigned(13 downto 0);
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signal TRACK_RAM_ADDR : unsigned(13 downto 0);
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signal TRACK_RAM_DI : unsigned(7 downto 0);
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signal TRACK_RAM_WE : std_logic;
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signal TRACK_GOOD: std_logic;
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--
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signal D1_ACTIVE, D2_ACTIVE : std_logic;
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signal IMAGE_UP_old : std_logic;
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signal IMAGE_DOWN_old : std_logic;
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signal IMAGE_UP_cur : std_logic;
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signal IMAGE_DOWN_cur : std_logic;
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begin
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IMAGE_NUMBER_OUT <= std_logic_vector(IMAGE_NUMBER);
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imgnum:process (CLK_24)
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constant maxcount:integer := 1000000000;
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begin
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if (rising_edge(CLK_24)) then
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if (RESETn = '0') then
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IMAGE_NUMBER <= "0000000000";
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else
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IMAGE_UP_old <= IMAGE_UP_cur;
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IMAGE_UP_cur <= IMAGE_UP;
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IMAGE_DOWN_old <= IMAGE_DOWN_cur;
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IMAGE_DOWN_cur <= IMAGE_DOWN;
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if (IMAGE_UP_cur = '0' and IMAGE_UP_old = '1') then
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IMAGE_NUMBER <= IMAGE_NUMBER + 1;
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end if;
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if (IMAGE_DOWN_cur = '0' and IMAGE_DOWN_old = '1') and IMAGE_NUMBER >0 then
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IMAGE_NUMBER <= IMAGE_NUMBER - 1;
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end if;
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end if;
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end if;
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end process;
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-- PHI_2 edges
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phi_2_edges: process(CLK_24)
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begin
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@ -44,11 +104,16 @@ begin
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--IO_CONTROL_SIGNAL
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IO_CONTROLn_int <= '0'
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when (A(15 downto 8) = x"03")
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IO_CONTROLn_int <= '0' when (A(15 downto 8) = x"03")
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and (A(7 downto 4) /= x"0")
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and (IO_SELECTn = '0')
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else '1';
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--disk_select signal
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disk_select <= '1' when (A(15 downto 8) = x"03")
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and (A(7 downto 4) = x"1")
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and (IO_SELECTn = '0')
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else '0';
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IO_CONTROLn <= IO_CONTROLn_int;
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s_romdis <= '1';
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O_ROMDISn <= s_romdis;
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@ -96,47 +161,55 @@ begin
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dout => rom_out
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);
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D_OUT <= rom_out;
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-- multiplex output
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D_OUT <= rom_out when disk_select = '0' else disk_D_OUT;
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-- disk : entity work.disk_ii port map (
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-- CLK_14M => CLK_14M,
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-- CLK_2M => CLK_2M,
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-- PRE_PHASE_ZERO => PRE_PHASE_ZERO,
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-- IO_SELECT => IO_SELECT(6),
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-- DEVICE_SELECT => DEVICE_SELECT(6),
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-- RESET => reset,
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-- A => ADDR,
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-- D_IN => D,
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-- D_OUT => PD,
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-- TRACK => TRACK,
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-- TRACK_ADDR => TRACK_ADDR,
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-- D1_ACTIVE => D1_ACTIVE,
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-- D2_ACTIVE => D2_ACTIVE,
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-- ram_write_addr => TRACK_RAM_ADDR,
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-- ram_di => TRACK_RAM_DI,
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-- ram_we => TRACK_RAM_WE
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-- );
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-- sdcard_interface : entity work.spi_controller port map (
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-- CLK_14M => CLK_14M,
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-- RESET => RESET,
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-- indication
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disk_a_on <= not D1_ACTIVE;
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-- CS_N => CS_N,
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-- MOSI => MOSI,
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-- MISO => MISO,
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-- SCLK => SCLK,
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track_ok <= not TRACK_GOOD;
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disk : entity work.disk_ii port map (
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CLK => CLK_24,
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PHI_2 => PHI_2,
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DEVICE_SELECT => disk_select,
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RESETn => RESETn,
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A => A(3 downto 0),
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D_IN => D_IN,
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D_OUT => disk_D_OUT,
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-- sd card
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D1_ACTIVE => D1_ACTIVE, -- drive 1 on
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D2_ACTIVE => D2_ACTIVE, -- drive 2 on
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-- to spi_controler
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TRACK => TRACK, -- current track to read
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TRACK_ADDR => TRACK_ADDR, -- current track_address
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ram_write_addr => TRACK_RAM_ADDR,
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ram_di => TRACK_RAM_DI,
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ram_we => TRACK_RAM_WE,
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TRACK_GOOD => TRACK_GOOD
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);
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disk_cur_TRACK <= std_logic_vector(TRACK);
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disk_track_addr <= std_logic_vector(TRACK_ADDR);
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sdcard_interface : entity work.spi_controller port map (
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CLK_14M => CLK_24,
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RESETn => RESETn,
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CS_N => SD_DAT3,
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MOSI => SD_CMD,
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MISO => SD_DAT,
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SCLK => SD_CLK,
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-- track => TRACK,
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-- image => image,
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-- ram_write_addr => TRACK_RAM_ADDR,
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-- ram_di => TRACK_RAM_DI,
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-- ram_we => TRACK_RAM_WE
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-- );
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track => TRACK,
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image => IMAGE_NUMBER,
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TRACK_GOOD => TRACK_GOOD,
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-- SD_DAT3 <= CS_N;
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-- SD_CMD <= MOSI;
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-- MISO <= SD_DAT;
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-- SD_CLK <= SCLK;
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-- from diskii
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ram_write_addr => TRACK_RAM_ADDR,
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ram_di => TRACK_RAM_DI,
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ram_we => TRACK_RAM_WE
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);
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end imp;
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@ -68,22 +68,22 @@ use ieee.numeric_std.all;
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entity disk_ii is
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port (
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CLK_14M : in std_logic;
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CLK_2M : in std_logic;
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PRE_PHASE_ZERO : in std_logic;
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IO_SELECT : in std_logic; -- e.g., C600 - C6FF ROM
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CLK : in std_logic;
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PHI_2 : in std_logic;
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DEVICE_SELECT : in std_logic; -- e.g., C0E0 - C0EF I/O locations
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RESET : in std_logic;
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A : in unsigned(15 downto 0);
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D_IN : in unsigned(7 downto 0); -- From 6502
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D_OUT : out unsigned(7 downto 0); -- To 6502
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RESETn : in std_logic;
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A : in std_logic_vector(3 downto 0);
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D_IN : in std_logic_vector(7 downto 0); -- From 6502
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D_OUT : out std_logic_vector(7 downto 0); -- To 6502
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TRACK : out unsigned(5 downto 0); -- Current track (0-34)
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track_addr : out unsigned(13 downto 0);
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D1_ACTIVE : out std_logic; -- Disk 1 motor on
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D2_ACTIVE : out std_logic; -- Disk 2 motor on
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ram_write_addr : in unsigned(13 downto 0); -- Address for track RAM
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ram_di : in unsigned(7 downto 0); -- Data to track RAM
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ram_we : in std_logic -- RAM write enable
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ram_we : in std_logic; -- RAM write enable
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TRACK_GOOD : in std_logic -- True when the track is read
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-- by spi
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);
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end disk_ii;
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@ -103,9 +103,14 @@ architecture rtl of disk_ii is
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-- Storage for one track worth of data in "nibblized" form
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type track_ram is array(0 to 6655) of unsigned(7 downto 0);
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-- type track_ram is array(0 to 2655) of unsigned(7 downto 0);
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-- Double-ported RAM for holding a track
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signal track_memory : track_ram;
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signal ram_do : unsigned(7 downto 0);
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attribute ram_style: string;
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attribute ram_style of track_memory : signal is "block"; --"distributed";
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signal ram_do : std_logic_vector(7 downto 0);
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-- Lower bit indicates whether disk data is "valid" or not
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-- RAM address is track_byte_addr(14 downto 1)
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@ -114,22 +119,35 @@ architecture rtl of disk_ii is
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-- not yet ready.
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signal track_byte_addr : unsigned(14 downto 0);
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signal read_disk : std_logic; -- When C08C accessed
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signal CUR_PHI_2:std_logic;
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signal OLD_PHI_2:std_logic;
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signal rising_PHI_2:std_logic;
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signal falling_PHI_2:std_logic;
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begin
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interpret_io : process (CLK_2M)
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-- PHI_2 edges
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phi_2_edges: process(CLK)
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begin
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if rising_edge(CLK_2M) then
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if reset = '1' then
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motor_phase <= (others => '0');
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drive_on <= '0';
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drive2_select <= '0';
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q6 <= '0';
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q7 <= '0';
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else
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if PRE_PHASE_ZERO = '1' and DEVICE_SELECT = '1' then
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if (rising_edge(CLK))then
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OLD_PHI_2 <= CUR_PHI_2;
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CUR_PHI_2 <= PHI_2;
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end if;
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end process;
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rising_PHI_2 <= CUR_PHI_2 and not OLD_PHI_2;
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falling_PHI_2<= not CUR_PHI_2 and CUR_PHI_2;
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interpret_io : process (CLK,RESETn)
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begin
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if RESETn = '0' then
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motor_phase <= (others => '0');
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drive_on <= '0';
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drive2_select <= '0';
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q6 <= '0';
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q7 <= '0';
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else
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if rising_edge(CLK) then
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if DEVICE_SELECT = '1' and rising_PHI_2 = '1' then
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if A(3) = '0' then -- C080 - C087
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motor_phase(TO_INTEGER(A(2 downto 1))) <= A(0);
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motor_phase(TO_INTEGER(unsigned(A(2 downto 1)))) <= A(0);
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else
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case A(2 downto 1) is
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when "00" => drive_on <= A(0); -- C088 - C089
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@ -165,15 +183,15 @@ begin
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-- 0 1 2 3 0
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--
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update_phase : process (CLK_14M)
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update_phase : process (CLK, RESETn)
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variable phase_change : integer;
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variable new_phase : integer;
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variable rel_phase : std_logic_vector(3 downto 0);
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begin
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if rising_edge(CLK_14M) then
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if reset = '1' then
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phase <= TO_UNSIGNED(70, 8); -- Deliberately odd to test reset
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else
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if RESETn = '0' then
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phase <= TO_UNSIGNED(138, 8); -- Deliberately odd to test reset
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else
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if rising_edge(CLK) then
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phase_change := 0;
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new_phase := TO_INTEGER(phase);
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rel_phase := motor_phase;
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@ -223,7 +241,7 @@ begin
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when others => null;
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end case;
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end if;
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if new_phase + phase_change <= 0 then
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new_phase := 0;
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elsif new_phase + phase_change > 139 then
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@ -239,28 +257,28 @@ begin
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TRACK <= phase(7 downto 2);
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-- Dual-ported RAM holding the contents of the track
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track_storage : process (CLK_14M)
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track_storage : process (CLK)
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begin
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if rising_edge(CLK_14M) then
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if rising_edge(CLK) then
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if ram_we = '1' then
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track_memory(to_integer(ram_write_addr)) <= ram_di;
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end if;
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ram_do <= track_memory(to_integer(track_byte_addr(14 downto 1)));
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ram_do <= std_logic_vector(track_memory(to_integer(track_byte_addr(14 downto 1))));
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end if;
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end process;
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-- Go to the next byte when the disk is accessed or if the counter times out
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read_head : process (CLK_2M)
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variable byte_delay : unsigned(5 downto 0); -- Accounts for disk spin rate
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read_head : process (CLK)
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variable byte_delay : unsigned(8 downto 0); -- Accounts for disk spin rate
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begin
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if rising_edge(CLK_2M) then
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if reset = '1' then
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if rising_edge(CLK) then
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if RESETn = '0' then
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track_byte_addr <= (others => '0');
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byte_delay := (others => '0');
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else
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byte_delay := byte_delay - 1;
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if (read_disk = '1' and PRE_PHASE_ZERO = '1') or byte_delay = 0 then
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byte_delay := (others => '0');
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if (read_disk = '1' and rising_PHI_2 = '1') then --or byte_delay = 0 then
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byte_delay := "000000100";
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if track_byte_addr = X"33FE" then
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track_byte_addr <= (others => '0');
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else
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@ -271,17 +289,26 @@ begin
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end if;
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end process;
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rom : entity work.disk_ii_rom port map (
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addr => A(7 downto 0),
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clk => CLK_14M,
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dout => rom_dout);
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read_disk <= '1' when DEVICE_SELECT = '1' and A(3 downto 0) = x"C" else
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read_disk <= '1' when DEVICE_SELECT = '1' and q7 = '0' and q6 = '0' and A(0) = '0' else
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'0'; -- C08C
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D_OUT <= rom_dout when IO_SELECT = '1' else
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ram_do when read_disk = '1' and track_byte_addr(0) = '0' else
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(others => '0');
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write_d_out:process(CLK)
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begin
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D_OUT <= (others => '0');
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if rising_edge(CLK) then
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if read_disk = '1' and track_byte_addr(0) = '0' and TRACK_GOOD = '1' and DRIVE_ON ='1' then
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D_OUT <= ram_do;
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else if (q6 = '1') then
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if (DRIVE_ON = '1')then
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D_OUT <= x"20";
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else
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D_OUT <= x"00";
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end if;
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end if;
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end if;
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end if;
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end process;
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track_addr <= track_byte_addr(14 downto 1);
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@ -131,3 +131,10 @@ NET "SD_DAT" LOC="P117" | IOSTANDARD = LVCMOS33;
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NET "SD_DAT3" LOC="P121" | IOSTANDARD = LVCMOS33;
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NET "SD_CMD" LOC="P119" | IOSTANDARD = LVCMOS33;
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NET "SD_CLK" LOC="P115" | IOSTANDARD = LVCMOS33;
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NET "disk_a_on" LOC="P35" | IOSTANDARD = LVCMOS25;
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NET "track_ok" LOC="P34" | IOSTANDARD = LVCMOS25;
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NET "image_buton_up" LOC="P112" | IOSTANDARD = LVCMOS25;
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NET "image_buton_down" LOC="P114" | IOSTANDARD = LVCMOS25;
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#PIN "controller8dos/sdcard_interface/Mmux_spi_clk11.A4" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "inst_buf3.O" CLOCK_DEDICATED_ROUTE = FALSE;
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@ -38,11 +38,11 @@ begin
|
|||
cs0 <= '1' when cs='1' and addr(15 downto 14)="00" else '0';
|
||||
cs1 <= '1' when cs='1' and addr(15 downto 14)="01" else '0';
|
||||
cs2 <= '1' when cs='1' and addr(15 downto 14)="10" else '0';
|
||||
cs3 <= '1' when cs='1' and addr(15 downto 14)="11" else '0';
|
||||
cs3 <= '1' when cs='1' and addr(14 downto 14)="1" else '0';
|
||||
|
||||
do <=
|
||||
ro0 when oe='1' and cs0='1' else
|
||||
ro1 when oe='1' and cs1='1' else
|
||||
ro3 when oe='1' and cs3='1' else
|
||||
ro2 when oe='1' and cs2='1' else
|
||||
ro3 when oe='1' and cs3='1' else
|
||||
(others=>'0');
|
||||
|
|
@ -57,15 +57,16 @@ begin
|
|||
do => ro0
|
||||
);
|
||||
|
||||
RAM_4000_7FFF : entity work.ram16k
|
||||
port map (
|
||||
clk => clk,
|
||||
cs => cs1,
|
||||
we => we,
|
||||
addr => addr(13 downto 0),
|
||||
di => di,
|
||||
do => ro1
|
||||
);
|
||||
ro1 <= (others => '0');
|
||||
-- RAM_4000_7FFF : entity work.ram16k
|
||||
-- port map (
|
||||
-- clk => clk,
|
||||
-- cs => cs1,
|
||||
-- we => we,
|
||||
-- addr => addr(13 downto 0),
|
||||
-- di => di,
|
||||
-- do => ro1
|
||||
-- );
|
||||
|
||||
RAM_8000_BFFF : entity work.ram16k
|
||||
port map (
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ begin
|
|||
end process;
|
||||
ram_read :process(CLK_x2)
|
||||
begin
|
||||
if rising_edge(CLK_x2) then
|
||||
if falling_edge(CLK_x2) then
|
||||
O_VIDEO <= ram(to_integer(unsigned(hpos_o)));
|
||||
end if;
|
||||
end process;
|
||||
|
|
|
|||
|
|
@ -33,9 +33,10 @@ entity spi_controller is
|
|||
ram_we : out std_logic;
|
||||
track : in unsigned(5 downto 0); -- Track number (0-34)
|
||||
image : in unsigned(9 downto 0); -- Which disk image to read
|
||||
TRACK_GOOD : out std_logic; --
|
||||
-- System Interface -------------------------------------------------------
|
||||
CLK_14M : in std_logic; -- System clock
|
||||
reset : in std_logic
|
||||
RESETn : in std_logic
|
||||
);
|
||||
|
||||
end spi_controller;
|
||||
|
|
@ -127,6 +128,7 @@ begin
|
|||
-- Purpose:
|
||||
-- Implements the combined "SD Card init", "track read" and "command" FSMs.
|
||||
--
|
||||
TRACK_GOOD <= '1' when current_track = track and current_image = image and write_addr = TRACK_SIZE else '0';
|
||||
sd_fsm : process(spi_clk)
|
||||
subtype cmd_t is std_logic_vector(5 downto 0);
|
||||
constant CMD0 : cmd_t := std_logic_vector(to_unsigned(0, 6));
|
||||
|
|
@ -144,7 +146,7 @@ begin
|
|||
begin
|
||||
if rising_edge(spi_clk) then
|
||||
ram_we <= '0';
|
||||
if reset = '1' then
|
||||
if RESETn = '0' then
|
||||
state <= POWER_UP;
|
||||
-- Deliberately out of range
|
||||
current_track <= (others => '1');
|
||||
|
|
@ -169,6 +171,21 @@ begin
|
|||
-- SD Card init FSM
|
||||
---------------------------------------------------------------------
|
||||
when POWER_UP =>
|
||||
current_track <= (others => '1');
|
||||
current_image <= (others => '1');
|
||||
sclk_sig <= '0';
|
||||
slow_clk <= true;
|
||||
CS_N <= '1';
|
||||
command <= (others => '0');
|
||||
argument <= (others => '0');
|
||||
crc7 <= (others => '0');
|
||||
command_out <= (others => '1');
|
||||
counter := TO_UNSIGNED(0, 8);
|
||||
byte_counter := TO_UNSIGNED(0, BLOCK_BITS);
|
||||
write_addr <= (others => '0');
|
||||
high_capacity <= false;
|
||||
version <= MMC;
|
||||
lba := (others => '0');
|
||||
counter := TO_UNSIGNED(224, 8);
|
||||
state <= RAMP_UP;
|
||||
|
||||
|
|
@ -317,6 +334,8 @@ begin
|
|||
sclk_sig <= '0';
|
||||
slow_clk <= true;
|
||||
CS_N <= '1';
|
||||
state <= POWER_UP;
|
||||
write_addr <= (others => '0');
|
||||
|
||||
---------------------------------------------------------------------
|
||||
-- Embedded "read track" FSM
|
||||
|
|
|
|||
Loading…
Reference in New Issue