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myboard initial commit

This commit is contained in:
byrtolet 2018-08-02 08:25:43 +03:00
parent 33bc057a81
commit e74716b534
4 changed files with 127 additions and 13 deletions
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106
cores/Oric/source/oric_zxuno_my.ucf Normal file
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@ -0,0 +1,106 @@
#UCF for ZX-UNO
NET "CLK_50" LOC="P126" | IOSTANDARD = LVCMOS25 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS25;
# Video output
NET O_VIDEO_R(2) LOC="P100" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_G(2) LOC="P99" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
NET O_VIDEO_B(2) LOC="P98" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
NET O_HSYNC LOC="P95" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
NET O_VSYNC LOC="P97" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
#NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS25;
#NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS25;
# Audio
NET "AUDIO_OUT" LOC="P94" | IOSTANDARD = LVCMOS33;
NET "K7_TAPEOUT" LOC="P115" | IOSTANDARD = LVCMOS25;
NET "K7_TAPEIN" LOC="P116" | IOSTANDARD = LVCMOS25;
# Keyboard and mouse
NET "PS2CLK1" LOC="P105" | IOSTANDARD = LVCMOS25 | PULLUP;
NET "PS2DAT1" LOC="P104" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS25 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS25;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS25;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS25;
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS25;
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS25;
#NET "sram_data<3>" LOC="P123 | IOSTANDARD = LVCMOS25;
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS25;
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS25;
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS25;
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS25;
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS25;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS25;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS25;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS25;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS25;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS25;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS25;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS25;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS25;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS25;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS25;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS25 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS25 | PULLUP;
# Switch
NET "I_RESET" LOC="P15" | IOSTANDARD = LVCMOS25 | PULLUP;
NET "I_NMI" LOC="P111" | IOSTANDARD = LVCMOS25 | PULLUP;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;
# NET D_VIDEO_R(2) LOC="P51" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_R(1) LOC="P50" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_R(0) LOC="P47" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(2) LOC="P40" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(1) LOC="P35" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_G(0) LOC="P33" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(2) LOC="P23" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(1) LOC="P17" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VIDEO_B(0) LOC="P24" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_HSYNC LOC="P57" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
# NET D_VSYNC LOC="P58" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;

10
cores/Oric/source/oricatmos.vhd
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@ -54,6 +54,7 @@ port (
-- K7_REMOTE : out std_logic; -- K7_REMOTE : out std_logic;
-- K7_AUDIOOUT : out std_logic; -- K7_AUDIOOUT : out std_logic;
I_NMI : in std_logic;
-- PRINTER -- PRINTER
-- PRT_DATA : inout std_logic_vector(7 downto 0); -- PRT_DATA : inout std_logic_vector(7 downto 0);
-- PRT_STR : out std_logic; -- strobe -- PRT_STR : out std_logic; -- strobe
@ -102,6 +103,8 @@ architecture RTL of ORIC is
signal cpu_rw : std_logic; signal cpu_rw : std_logic;
signal cpu_irq : std_logic; signal cpu_irq : std_logic;
signal ad : std_logic_vector(15 downto 0); signal ad : std_logic_vector(15 downto 0);
signal NMI_INT :std_logic;
signal RESET_INT:std_logic;
-- VIA -- VIA
signal via_pa_out_oe : std_logic_vector( 7 downto 0); signal via_pa_out_oe : std_logic_vector( 7 downto 0);
@ -177,6 +180,9 @@ begin
D_HSYNC <= O_HSYNC; D_HSYNC <= O_HSYNC;
D_VSYNC <= O_VSYNC; D_VSYNC <= O_VSYNC;
NMI_INT <= not I_NMI;
RESET_INT <= not I_RESET;
inst_pll_base : PLL_BASE inst_pll_base : PLL_BASE
generic map ( generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED" BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
@ -223,7 +229,7 @@ begin
LOCKED => pll_locked, -- Active high PLL lock signal LOCKED => pll_locked, -- Active high PLL lock signal
CLKFBIN => CLKFB, -- Clock feedback input CLKFBIN => CLKFB, -- Clock feedback input
CLKIN => CLK_50, -- Clock input CLKIN => CLK_50, -- Clock input
RST => I_RESET -- Asynchronous PLL reset RST => RESET_INT -- Asynchronous PLL reset
); );
@ -250,7 +256,7 @@ begin
Rdy => '1', Rdy => '1',
Abort_n => '1', Abort_n => '1',
IRQ_n => cpu_irq, IRQ_n => cpu_irq,
NMI_n => '1', NMI_n => NMI_INT,
SO_n => '1', SO_n => '1',
R_W_n => cpu_rw, R_W_n => cpu_rw,
Sync => open, Sync => open,

6
cores/Oric/source/ula.vhd
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@ -419,15 +419,17 @@ begin
u_ld_reg: process(CLK_24, lRELOAD_SEL, RESET_INT) u_ld_reg: process(CLK_24, lRELOAD_SEL, RESET_INT)
begin begin
if (falling_edge(CLK_24)) then
if (RESET_INT = '1') then if (RESET_INT = '1') then
lREG_INK <= (others=>'1'); lREG_INK <= (others=>'1');
lREG_STYLE <= (others=>'0'); lREG_STYLE <= (others=>'0');
lREG_PAPER <= (others=>'0'); lREG_PAPER <= (others=>'0');
lREG_MODE <= (others=>'0'); lREG_MODE <= (others=>'0');
elsif (lRELOAD_SEL = '1') then elsif (lRELOAD_SEL = '1') then
lREG_INK <= (others=>'1'); lREG_INK <= (others=>'0');
lREG_STYLE <= (others=>'0'); lREG_STYLE <= (others=>'0');
lREG_PAPER <= (others=>'0'); lREG_PAPER <= (others=>'1');
end if;
elsif rising_edge(CLK_24) then elsif rising_edge(CLK_24) then
if (RELD_REG = '1' and isAttrib = '1') then if (RELD_REG = '1' and isAttrib = '1') then
case lREGHOLD(6 downto 3) is case lREGHOLD(6 downto 3) is

2
cores/generar.sh
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@ -4,6 +4,6 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc "$ruta_ucf"_zxu
map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf
trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf
bitgen -intstyle ise -f "$machine".ut "$machine".ncd bitgen -intstyle ise -g UnusedPin:Pullup -f "$machine".ut "$machine".ncd
bit2bin "$machine".bit COREn."$2" bit2bin "$machine".bit COREn."$2"
cp "$machine".bit "$machine"."$1".bit cp "$machine".bit "$machine"."$1".bit