mirror of https://github.com/zxdos/zxuno.git
myboard initial commit
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byrtolet
parent
33bc057a81
commit
e74716b534
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@ -0,0 +1,106 @@
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#UCF for ZX-UNO
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NET "CLK_50" LOC="P126" | IOSTANDARD = LVCMOS25 | PERIOD=20.0ns;
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#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS25;
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# Video output
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NET O_VIDEO_R(2) LOC="P100" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_VIDEO_R(1) LOC="P80" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_VIDEO_R(0) LOC="P79" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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NET O_VIDEO_G(2) LOC="P99" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_VIDEO_G(1) LOC="P83" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_VIDEO_G(0) LOC="P82" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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NET O_VIDEO_B(2) LOC="P98" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_VIDEO_B(1) LOC="P92" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_VIDEO_B(0) LOC="P88" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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NET O_HSYNC LOC="P95" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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NET O_VSYNC LOC="P97" | IOSTANDARD = LVCMOS25 | DRIVE = 8 | SLEW = FAST;
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#NET O_NTSC LOC="P66" | IOSTANDARD = LVCMOS25;
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#NET O_PAL LOC="P67" | IOSTANDARD = LVCMOS25;
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# Audio
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NET "AUDIO_OUT" LOC="P94" | IOSTANDARD = LVCMOS33;
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NET "K7_TAPEOUT" LOC="P115" | IOSTANDARD = LVCMOS25;
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NET "K7_TAPEIN" LOC="P116" | IOSTANDARD = LVCMOS25;
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# Keyboard and mouse
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NET "PS2CLK1" LOC="P105" | IOSTANDARD = LVCMOS25 | PULLUP;
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NET "PS2DAT1" LOC="P104" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS25 | PULLUP;
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# SRAM
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#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS25;
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#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<3>" LOC="P123 | IOSTANDARD = LVCMOS25;
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#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS25;
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#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS25;
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#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS25;
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# SPI Flash
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#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS25;
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#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS25;
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#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS25;
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#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS25;
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#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS25;
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#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS25;
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# SD/MMC
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#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS25;
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#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS25;
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#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS25;
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#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS25;
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# JOYSTICK
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#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS25 | PULLUP;
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#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS25 | PULLUP;
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# Switch
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NET "I_RESET" LOC="P15" | IOSTANDARD = LVCMOS25 | PULLUP;
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NET "I_NMI" LOC="P111" | IOSTANDARD = LVCMOS25 | PULLUP;
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NET "CLK_50" TNM_NET = "CLK_50";
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TIMESPEC "TS_CLK_50" = PERIOD "CLK_50" 20 ns HIGH 50 %;
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# NET D_VIDEO_R(2) LOC="P51" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_R(1) LOC="P50" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_R(0) LOC="P47" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_G(2) LOC="P40" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_G(1) LOC="P35" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_G(0) LOC="P33" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_B(2) LOC="P23" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_B(1) LOC="P17" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VIDEO_B(0) LOC="P24" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_HSYNC LOC="P57" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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# NET D_VSYNC LOC="P58" | IOSTANDARD = LVCMOS25 | DRIVE=2 | SLEW=SLOW;
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@ -54,6 +54,7 @@ port (
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-- K7_REMOTE : out std_logic;
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-- K7_AUDIOOUT : out std_logic;
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I_NMI : in std_logic;
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-- PRINTER
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-- PRT_DATA : inout std_logic_vector(7 downto 0);
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-- PRT_STR : out std_logic; -- strobe
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@ -102,6 +103,8 @@ architecture RTL of ORIC is
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signal cpu_rw : std_logic;
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signal cpu_irq : std_logic;
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signal ad : std_logic_vector(15 downto 0);
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signal NMI_INT :std_logic;
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signal RESET_INT:std_logic;
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-- VIA
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signal via_pa_out_oe : std_logic_vector( 7 downto 0);
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@ -177,6 +180,9 @@ begin
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D_HSYNC <= O_HSYNC;
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D_VSYNC <= O_VSYNC;
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NMI_INT <= not I_NMI;
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RESET_INT <= not I_RESET;
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inst_pll_base : PLL_BASE
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generic map (
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BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
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@ -223,7 +229,7 @@ begin
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LOCKED => pll_locked, -- Active high PLL lock signal
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CLKFBIN => CLKFB, -- Clock feedback input
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CLKIN => CLK_50, -- Clock input
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RST => I_RESET -- Asynchronous PLL reset
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RST => RESET_INT -- Asynchronous PLL reset
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);
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@ -250,7 +256,7 @@ begin
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Rdy => '1',
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Abort_n => '1',
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IRQ_n => cpu_irq,
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NMI_n => '1',
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NMI_n => NMI_INT,
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SO_n => '1',
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R_W_n => cpu_rw,
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Sync => open,
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@ -419,15 +419,17 @@ begin
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u_ld_reg: process(CLK_24, lRELOAD_SEL, RESET_INT)
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begin
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if (falling_edge(CLK_24)) then
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if (RESET_INT = '1') then
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lREG_INK <= (others=>'1');
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lREG_STYLE <= (others=>'0');
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lREG_PAPER <= (others=>'0');
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lREG_MODE <= (others=>'0');
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elsif (lRELOAD_SEL = '1') then
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lREG_INK <= (others=>'1');
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lREG_INK <= (others=>'0');
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lREG_STYLE <= (others=>'0');
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lREG_PAPER <= (others=>'0');
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lREG_PAPER <= (others=>'1');
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end if;
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elsif rising_edge(CLK_24) then
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if (RELD_REG = '1' and isAttrib = '1') then
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case lREGHOLD(6 downto 3) is
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@ -4,6 +4,6 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc "$ruta_ucf"_zxu
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map -intstyle ise -w -ol high -mt 2 -p xc6slx9-tqg144-"$speed" -logic_opt off -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -ir off -pr off -lc off -power off -o "$machine"_map.ncd "$machine".ngd "$machine".pcf
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par -intstyle ise -w -ol high -mt 4 "$machine"_map.ncd "$machine".ncd "$machine".pcf
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trce -intstyle ise -v 3 -s "$speed" -n 3 -fastpaths -xml "$machine".twx "$machine".ncd -o "$machine".twr "$machine".pcf
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bitgen -intstyle ise -f "$machine".ut "$machine".ncd
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bitgen -intstyle ise -g UnusedPin:Pullup -f "$machine".ut "$machine".ncd
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bit2bin "$machine".bit COREn."$2"
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cp "$machine".bit "$machine"."$1".bit
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