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JupiterAce a última versión

This commit is contained in:
antoniovillena 2016-04-28 14:14:15 +02:00
parent bba00ea2ba
commit e8154a7dcb
23 changed files with 13205 additions and 272 deletions
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1129
cores/JupiterAce/T80.vhd Normal file
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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
SavePC : out std_logic_vector(15 downto 0);
SaveINT : out std_logic_vector(7 downto 0);
RestorePC : in std_logic_vector(15 downto 0);
RestoreINT : in std_logic_vector(7 downto 0);
RestorePC_n : in std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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@ -0,0 +1,286 @@
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0);
SavePC : out std_logic_vector(15 downto 0);
SaveINT : out std_logic_vector(7 downto 0);
RestorePC : in std_logic_vector(15 downto 0);
RestoreINT : in std_logic_vector(7 downto 0);
RestorePC_n : in std_logic
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
SavePC => SavePC,
SaveINT => SaveINT,
RestorePC => RestorePC,
RestoreINT => RestoreINT,
RestorePC_n => RestorePC_n );
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
MREQ <= '0';
end if;
end if;
end if;
end process;
-- IORQ_n_i uses a different timming than MREQ.
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
IORQ_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" then
if TState = "001" then
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
IORQ_n_i <= '1';
end if;
else
if TState = "001" then
IORQ_n_i <= not IORQ;
end if;
if TState = "011" then
IORQ_n_i <= '1';
end if;
end if;
end if;
end process;
end;

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#include <stdio.h>
#include <string.h>
int main (int argc, char *argv[])
{
FILE *f;
unsigned char *scr;
char nombre[256];
int i,leido;
if (argc<2)
return 1;
scr = malloc(65536);
f = fopen (argv[1],"rb");
if (!f)
return 1;
leido = fread (scr, 1, 65536, f);
fclose (f);
strcpy (nombre, argv[1]);
nombre[strlen(nombre)-3]=0;
strcat (nombre, "hex");
f = fopen (nombre, "wt");
for (i=0;i<leido;i++)
fprintf (f, "%.2X\n", scr[i]);
fclose(f);
return 0;
}

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@ -1,5 +1,6 @@
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
@ -23,6 +24,7 @@
module jupiter_ace (
input wire clkram,
input wire clk65,
input wire clkcpu,
input wire reset,
input wire ear,
output wire [7:0] filas,
@ -33,148 +35,127 @@ module jupiter_ace (
output wire spk
);
wire sramce;
wire cramce;
wire scramwr, scramoe;
wire ramce, xramce, romce, vramdec;
wire en254r, en254w;
/* Los buses de memoria */
wire [7:0] DoutROM;
wire [7:0] DoutRAM;
wire [7:0] DoutXRAM;
wire [7:0] DoutSRAM;
wire [7:0] DoutCRAM;
wire [7:0] DoutIO;
// Los buses del Z80
wire [7:0] DinZ80;
wire [7:0] DoutZ80;
wire [15:0] AZ80;
wire [9:0] ASRAM;
wire [9:0] ACRAM;
wire [9:0] ASRAMVideo;
wire [2:0] ACRAMVideo;
wire iorq, mreq, intr, cpuclk, rd, wr, cpuwait;
wire iorq_n, mreq_n, int_n, rd_n, wr_n, wait_n;
wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
wire [7:0] sram_data, cram_data;
wire [9:0] sram_addr, cram_addr;
/* Copia del bus de direcciones para las filas del teclado */
// Copia del bus de direcciones para las filas del teclado
assign filas = AZ80[15:8];
tri [7:0] Din; // bus de datos triestado. Todo lo que esta conectado a el...
assign Din = (!romce)? DoutROM : 8'bzzzzzzzz;
assign Din = DoutRAM;
assign Din = DoutXRAM;
assign Din[5:0] = DoutIO;
assign Din = (!sramce && cpuwait && !vramdec)? DoutSRAM : 8'bzzzzzzzz;
assign Din = (!cramce && cpuwait && !vramdec)? DoutCRAM : 8'bzzzzzzzz;
assign DinZ80 = Din;
/* Arbitrador del bus de direcciones de entrada a la SRAM */
assign ASRAM = (!vramdec && cpuwait)? AZ80[9:0] : ASRAMVideo;
/* Arbitrador del bus de direccioens de entrada a la CRAM */
assign ACRAM = (!vramdec && cpuwait)? AZ80[9:0] : {DoutSRAM[6:0],ACRAMVideo};
// Multiplexor para asignar un valor al bus de datos de entrada del Z80
assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
(sram_enable == 1'b1)? dout_sram :
(cram_enable == 1'b1)? dout_cram :
(uram_enable == 1'b1)? dout_uram :
(xram_enable == 1'b1)? dout_xram :
(eram_enable == 1'b1)? dout_eram :
(data_from_jace_oe == 1'b1)? data_from_jace :
sram_data | cram_data; // By default, this is what the data bus sees
/* La memoria RAM del equipo */
ram1k sram (
// Memoria del equipo
ram1k_dualport sram (
.clk(clkram),
.a(ASRAM),
.ce(sram_enable),
.a1(AZ80[9:0]),
.a2(sram_addr),
.din(DoutZ80),
.dout(DoutSRAM),
.ce_n(sramce),
.oe_n(scramoe),
.we_n(scramwr)
.dout1(dout_sram),
.dout2(sram_data),
.we(~wr_n)
);
ram1k cram(
.clk(clkram),
.a(ACRAM),
ram1k_dualport cram (
.clk(clkram),
.ce(cram_enable),
.a1(AZ80[9:0]),
.a2(cram_addr),
.din(DoutZ80),
.dout(DoutCRAM),
.ce_n(cramce),
.oe_n(scramoe),
.we_n(scramwr)
.dout1(dout_cram),
.dout2(cram_data),
.we(~wr_n)
);
ram1k uram(
.clk(clkram),
.a(AZ80[9:0]),
.din(DoutZ80),
.dout(DoutRAM),
.ce_n(ramce),
.oe_n(rd),
.we_n(wr)
.ce(uram_enable),
.a(AZ80[9:0]),
.din(DoutZ80),
.dout(dout_uram),
.we(~wr_n)
);
ram16k xram(
.clk(clkram),
.a(AZ80[13:0]),
.din(DoutZ80),
.dout(DoutXRAM),
.ce_n(xramce),
.oe_n(rd),
.we_n(wr)
.ce(xram_enable),
.a(AZ80[13:0]),
.din(DoutZ80),
.dout(dout_xram),
.we(~wr_n)
);
ram32k eram(
.clk(clkram),
.ce(eram_enable),
.a(AZ80[14:0]),
.din(DoutZ80),
.dout(dout_eram),
.we(~wr_n)
);
/* La ROM */
rom8k rom(
.clka(clkram),
.addra(AZ80[12:0]),
.douta(DoutROM),
.ena(~romce)
rom the_rom(
.clk(clkram),
.a(AZ80[12:0]),
.dout(dout_rom)
);
/* Decodificador de acceso a memoria y E/S */
decodificador deco(
.a(AZ80),
.mreq(mreq),
.iorq(iorq),
.rd(rd),
.wr(wr),
.romce(romce),
.ramce(ramce),
.xramce(xramce),
.vramdec(vramdec),
.en254r(en254r),
.en254w(en254w)
);
/* Logica de arbitración de memoria y periféricos */
jace glue_logic (
.clkm(clkram),
.clk(clk65),
.cpuclk(cpuclk),
.a(AZ80), /* bus de direcciones CPU */
.d3(DoutZ80[3]),
.dout(DoutIO[5:0]), /* bus de datos de la CPU */
.wr(wr),
.vramdec(vramdec),
.intr(intr),
.cpuwait(cpuwait), /* Salida WAIT al procesador */
.en254r(en254r),
.en254w(en254w),
.sramce(sramce), /* Habilitación de la RAM de pantalla */
.cramce(cramce), /* Habilitación de la RAM de caracteres */
.scramoe(scramoe), /* OE de ambas RAM's: de pantalla y de caracteres */
.scramwr(scramwr), /* WE de ambas RAM's: de pantalla y de caracteres */
.DinShiftR(DoutCRAM), /* Entrada paralelo al registro de desplazamiento. Viene del bus de datos de la RAM de caracteres */
.videoinverso(DoutSRAM[7]), /* Bit 7 leído de la RAM de pantalla. Indica si el caracter debe invertirse o no */
.ASRAMVideo(ASRAMVideo), /* Al bus de direcciones de la RAM de pantalla */
.ACRAMVideo(ACRAMVideo), /* Al bus de direcciones de la RAM de caracteres */
.kbd(columnas),
.ear(ear),
.mic(mic),
.spk(spk),
.sync(sync),
.video(video) /* Señal de video, sin sincronismos */
);
/* La CPU */
tv80n cpu(
// Outputs
.m1_n(), .mreq_n(mreq), .iorq_n(iorq), .rd_n(rd), .wr_n(wr), .rfsh_n(), .halt_n(), .busak_n(), .A(AZ80), .do(DoutZ80),
.m1_n(), .mreq_n(mreq_n), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n), .rfsh_n(), .halt_n(), .busak_n(), .A(AZ80), .do(DoutZ80),
// Inputs
.di(DinZ80), .reset_n(reset), .clk(cpuclk), .wait_n(cpuwait), .int_n(intr), .nmi_n(1'b1), .busrq_n(1'b1)
);
.di(DinZ80), .reset_n(reset), .clk(clkcpu), .wait_n(wait_n), .int_n(int_n), .nmi_n(1'b1), .busrq_n(1'b1)
);
jace_logic todo_lo_demas (
.clk(clk65),
// CPU interface
.cpu_addr(AZ80),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.data_from_cpu(DoutZ80),
.data_to_cpu(data_from_jace),
.data_to_cpu_oe(data_from_jace_oe),
.wait_n(wait_n),
.int_n(int_n),
// CPU-RAM interface
.rom_enable(rom_enable),
.sram_enable(sram_enable),
.cram_enable(cram_enable),
.uram_enable(uram_enable),
.xram_enable(xram_enable),
.eram_enable(eram_enable),
// Screen RAM and Char RAM interface
.screen_addr(sram_addr),
.screen_data(sram_data),
.char_addr(cram_addr),
.char_data(cram_data),
// Devices
.kbdcols(columnas),
.ear(ear),
.spk(spk),
.mic(mic),
.video(video),
.csync(sync)
);
endmodule

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@ -0,0 +1,193 @@
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:32:05 11/08/2015
// Design Name:
// Module Name: jace_logic
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module jace_logic (
input wire clk,
// CPU interface
input wire [15:0] cpu_addr,
input wire mreq_n,
input wire iorq_n,
input wire rd_n,
input wire wr_n,
input wire [7:0] data_from_cpu,
output reg [7:0] data_to_cpu,
output reg data_to_cpu_oe,
output reg wait_n,
output wire int_n,
// CPU-RAM interface
output reg rom_enable,
output reg sram_enable,
output reg cram_enable,
output reg uram_enable,
output reg xram_enable,
output reg eram_enable,
// Screen RAM and Char RAM interface
output wire [9:0] screen_addr,
input wire [7:0] screen_data,
output wire [9:0] char_addr,
input wire [7:0] char_data,
// Devices
input wire [4:0] kbdcols,
input wire ear,
output reg spk,
output reg mic,
output wire video,
output wire csync
);
initial begin
wait_n = 1'b1;
spk = 1'b0;
mic = 1'b0;
end
reg [8:0] cntpix = 9'd0;
reg [8:0] cntscn = 9'd0;
wire [17:0] cnt = {cntscn, cntpix};
always @(posedge clk) begin
if (cntpix != 9'd415)
cntpix <= cntpix + 9'd1;
else begin
cntpix <= 9'd0;
if (cntscn != 9'd311)
cntscn <= cntscn + 9'd1;
else
cntscn <= 9'd0;
end
end
reg vsync; // FIELD signal in schematic
always @* begin
if (cntscn >= 9'd248 && cntscn <= 9'd255)
vsync = 1'b0;
else
vsync = 1'b1;
end
assign int_n = vsync;
reg hsync; // LINE signal in schematic
always @* begin
if (cntpix >= 9'd320 && cntpix <= 9'd351)
hsync = 1'b0;
else
hsync = 1'b1;
end
assign csync = hsync & vsync;
reg viden; // VIDEN signal in schematic
always @* begin
if (cntpix >= 9'd0 && cntpix <= 9'd255 &&
cntscn >= 9'd0 && cntscn <= 9'd191)
viden = 1'b1;
else
viden = 1'b0;
end
// SHIFT/LOAD signal to 74LS166
reg shiftload;
always @* begin
if (cnt[2:0] == 3'b000 && viden == 1'b1)
shiftload = 1'b1;
else
shiftload = 1'b0;
end
assign screen_addr = {cnt[16:12], cnt[7:3]};
assign char_addr = {screen_data[6:0], cnt[11:9]};
// 74LS166
reg [7:0] shiftreg = 8'h00;
always @(posedge clk) begin
if (shiftload == 1'b1)
shiftreg <= char_data;
else
shiftreg <= {shiftreg[6:0], 1'b0};
end
// Pixel inverter reg and video output stage
reg pixinverter = 1'b0;
always @(posedge clk) begin
if (cnt[2:0] == 3'b000)
pixinverter <= viden & screen_data[7];
end
assign video = shiftreg[7] ^ pixinverter;
// Address decoder
reg fast_access;
always @* begin
rom_enable = 1'b0;
sram_enable = 1'b0;
cram_enable = 1'b0;
uram_enable = 1'b0;
xram_enable = 1'b0;
eram_enable = 1'b0;
fast_access = 1'b1;
if (mreq_n == 1'b0) begin
if (cpu_addr >= 16'h0000 && cpu_addr <= 16'h1FFF)
rom_enable = 1'b1;
else if (cpu_addr >= 16'h2000 && cpu_addr <= 16'h27FF) begin
sram_enable = 1'b1;
if (cpu_addr >= 16'h2400 && cpu_addr <= 16'h27FF)
fast_access = 1'b0;
end
else if (cpu_addr >= 16'h2800 && cpu_addr <= 16'h2FFF) begin
cram_enable = 1'b1;
if (cpu_addr >= 16'h2C00 && cpu_addr <= 16'h2FFF)
fast_access = 1'b0;
end
else if (cpu_addr >= 16'h3000 && cpu_addr <= 16'h3FFF)
uram_enable = 1'b1;
else if (cpu_addr >= 16'h4000 && cpu_addr <= 16'h7FFF)
xram_enable = 1'b1;
else
eram_enable = 1'b1;
end
end
// CPU arbitration to share memory with video generator
always @(posedge clk) begin
if ((sram_enable == 1'b1 || cram_enable == 1'b1) && viden == 1'b1 && fast_access == 1'b0)
wait_n <= 1'b0;
else if (viden == 1'b0)
wait_n <= 1'b1;
end
// IO devices
always @* begin
data_to_cpu_oe = 1'b0;
data_to_cpu = {2'b11, ear, kbdcols};
if (iorq_n == 1'b0 && cpu_addr[0] == 1'b0 && rd_n == 1'b0) begin
data_to_cpu_oe = 1'b1;
end
end
always @(posedge clk) begin
if (iorq_n == 1'b0 && cpu_addr[0] == 1'b0) begin
if (rd_n == 1'b0 && wr_n == 1'b1)
spk <= 1'b0;
else if (rd_n == 1'b1 && wr_n == 1'b0)
spk <= 1'b1;
if (wr_n == 1'b0)
mic <= data_from_cpu[3];
end
end
endmodule

188
cores/JupiterAce/jupiter_ace.gise Normal file
View File

@ -0,0 +1,188 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="jupiter_ace.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_jace_spartan6.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="tld_jace_spartan6.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="tld_jace_spartan6.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="tld_jace_spartan6.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="tld_jace_spartan6.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="tld_jace_spartan6.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="tld_jace_spartan6.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="tld_jace_spartan6.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="tld_jace_spartan6.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="tld_jace_spartan6.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="tld_jace_spartan6.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="tld_jace_spartan6.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tld_jace_spartan6.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="tld_jace_spartan6.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="tld_jace_spartan6.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="tld_jace_spartan6.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="tld_jace_spartan6.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="tld_jace_spartan6.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="tld_jace_spartan6.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="tld_jace_spartan6.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="tld_jace_spartan6.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="tld_jace_spartan6.xst"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_jace_spartan6_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="tld_jace_spartan6_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="tld_jace_spartan6_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="tld_jace_spartan6_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="tld_jace_spartan6_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="tld_jace_spartan6_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="tld_jace_spartan6_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="tld_jace_spartan6_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="tld_jace_spartan6_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="tld_jace_spartan6_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4731562624927410055" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6263557264038183016" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1951148348739412805" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482304" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2932384963007625358" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482377" xil_pn:in_ck="-1011495219309582457" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5110793382240503873" xil_pn:start_ts="1460482304">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="tld_jace_spartan6.lso"/>
<outfile xil_pn:name="tld_jace_spartan6.ngc"/>
<outfile xil_pn:name="tld_jace_spartan6.ngr"/>
<outfile xil_pn:name="tld_jace_spartan6.prj"/>
<outfile xil_pn:name="tld_jace_spartan6.stx"/>
<outfile xil_pn:name="tld_jace_spartan6.syr"/>
<outfile xil_pn:name="tld_jace_spartan6.xst"/>
<outfile xil_pn:name="tld_jace_spartan6_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1460482871" xil_pn:in_ck="8146865349285220654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3073422981912245990" xil_pn:start_ts="1460482871">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1460482887" xil_pn:in_ck="-8973030265980210664" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4306676935314038505" xil_pn:start_ts="1460482871">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="tld_jace_spartan6.bld"/>
<outfile xil_pn:name="tld_jace_spartan6.ngd"/>
<outfile xil_pn:name="tld_jace_spartan6_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1460482933" xil_pn:in_ck="-8973030265980210663" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1460482887">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="tld_jace_spartan6.pcf"/>
<outfile xil_pn:name="tld_jace_spartan6_map.map"/>
<outfile xil_pn:name="tld_jace_spartan6_map.mrp"/>
<outfile xil_pn:name="tld_jace_spartan6_map.ncd"/>
<outfile xil_pn:name="tld_jace_spartan6_map.ngm"/>
<outfile xil_pn:name="tld_jace_spartan6_map.xrpt"/>
<outfile xil_pn:name="tld_jace_spartan6_summary.xml"/>
<outfile xil_pn:name="tld_jace_spartan6_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1460482979" xil_pn:in_ck="-5559234896413727310" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1460482933">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="tld_jace_spartan6.ncd"/>
<outfile xil_pn:name="tld_jace_spartan6.pad"/>
<outfile xil_pn:name="tld_jace_spartan6.par"/>
<outfile xil_pn:name="tld_jace_spartan6.ptwx"/>
<outfile xil_pn:name="tld_jace_spartan6.unroutes"/>
<outfile xil_pn:name="tld_jace_spartan6.xpi"/>
<outfile xil_pn:name="tld_jace_spartan6_pad.csv"/>
<outfile xil_pn:name="tld_jace_spartan6_pad.txt"/>
<outfile xil_pn:name="tld_jace_spartan6_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1460483026" xil_pn:in_ck="-5273148268032026713" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1664592939731293453" xil_pn:start_ts="1460482979">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="tld_jace_spartan6.bgn"/>
<outfile xil_pn:name="tld_jace_spartan6.drc"/>
<outfile xil_pn:name="tld_jace_spartan6.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1460482979" xil_pn:in_ck="-8973030265980210795" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1460482966">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="tld_jace_spartan6.twr"/>
<outfile xil_pn:name="tld_jace_spartan6.twx"/>
</transform>
</transforms>
</generated_project>

45
cores/JupiterAce/jupiter_ace.xise
View File

@ -15,16 +15,6 @@
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="test_ace.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="cpldace.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="memorias.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
@ -53,22 +43,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="reloj_maestro.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="test_cpld_ace.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="rom8k.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="tld_jace_spartan6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="ps2_port.v" xil_pn:type="FILE_VERILOG">
@ -82,6 +57,18 @@
<file xil_pn:name="pines_zxuno.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="relojes.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="jace_logic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
</files>
<properties>
@ -96,7 +83,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -140,7 +127,7 @@
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@ -421,7 +408,9 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<bindings>
<binding xil_pn:location="/tld_jace_spartan6" xil_pn:name="pines_zxuno.ucf"/>
</bindings>
<libraries/>

26
cores/JupiterAce/keyboard_for_ace.v
View File

@ -407,34 +407,36 @@ module keyboard_for_ace(
`KEY_CORCHA:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[6][4] <= is_released; // ^
else
if (alt_pressed || shift_pressed)
matrix[5][4] <= is_released; // [
else
matrix[6][4] <= is_released; // ^
end
`KEY_CORCHC:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[6][2] <= is_released; // +
else
if (shift_pressed)
matrix[7][3] <= is_released; // *
else if (alt_pressed)
matrix[5][3] <= is_released; // ]
else
matrix[6][2] <= is_released; // +
end
`KEY_LLAVA:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[0][3] <= is_released; // pound
else
if (alt_pressed || shift_pressed)
matrix[1][3] <= is_released; // {
else
matrix[0][3] <= is_released; // pound
end
`KEY_LLAVC:
begin
matrix[0][1] <= is_released;
if (!shift_pressed)
matrix[5][2] <= is_released; // copyright
else
if (alt_pressed || shift_pressed)
matrix[1][4] <= is_released; // }
else
matrix[5][2] <= is_released; // copyright
end
`KEY_COMA:
begin

93
cores/JupiterAce/memorias.v
View File

@ -20,56 +20,73 @@
//
//////////////////////////////////////////////////////////////////////////////////
module ram1k(
module ram1k (
input wire clk,
input wire ce,
input wire [9:0] a,
input wire [7:0] din,
output wire [7:0] dout,
input wire ce_n,
input wire oe_n,
input wire we_n
output reg [7:0] dout,
input wire we
);
reg [7:0] dato;
reg [7:0] mem[0:1023];
wire ce = ~ce_n;
wire we = ~we_n;
assign dout = (oe_n | ce_n)? 8'bzzzzzzzz : dato;
always @(posedge clk) begin
if (ce == 1'b1) begin
if (we == 1'b0)
dato <= mem[a];
else
mem[a] <= din;
end
reg [7:0] mem[0:1023];
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
module ram16k(
module ram1k_dualport(
input wire clk,
input wire ce,
input wire [9:0] a1,
input wire [9:0] a2,
input wire [7:0] din,
output reg [7:0] dout1,
output reg [7:0] dout2,
input wire we
);
reg [7:0] mem[0:1023];
always @(posedge clk) begin
dout2 <= mem[a2];
dout1 <= mem[a1];
if (we == 1'b1 && ce == 1'b1)
mem[a1] <= din;
end
endmodule
module ram16k (
input wire clk,
input wire ce,
input wire [13:0] a,
input wire [7:0] din,
output wire [7:0] dout,
input wire ce_n,
input wire oe_n,
input wire we_n
output reg [7:0] dout,
input wire we
);
reg [7:0] dato;
reg [7:0] mem[0:16383];
wire ce = ~ce_n;
wire we = ~we_n;
assign dout = (oe_n | ce_n)? 8'bzzzzzzzz : dato;
always @(posedge clk) begin
if (ce == 1'b1) begin
if (we == 1'b0)
dato <= mem[a];
else
mem[a] <= din;
end
reg [7:0] mem[0:16383];
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule
module ram32k (
input wire clk,
input wire ce,
input wire [14:0] a,
input wire [7:0] din,
output reg [7:0] dout,
input wire we
);
reg [7:0] mem[0:32767];
always @(posedge clk) begin
dout <= mem[a];
if (we == 1'b1 && ce == 1'b1)
mem[a] <= din;
end
endmodule

44
cores/JupiterAce/par_usage_statistics.html
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@ -1,32 +1,32 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1987</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>9927</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>9927</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>2153</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>8.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>12.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>12.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>18.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>18.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>18.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>18.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>18.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>18.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>2.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>2039</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>10450</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>10450</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>10425</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>12.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>16.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>17.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>24.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>25.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>26.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>7.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>4.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>8.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>3.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>4.6416</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>6.0303</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>

96
cores/JupiterAce/pines_zxuno.ucf
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@ -1,34 +1,34 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
NET "clk50mhz" PERIOD=20 ns;
#NET "sysclk" PERIOD=35 ns;
#NET "clk12" PERIOD=83 ns;
# Video output
NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
@ -51,34 +51,32 @@ NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P99" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P104" | IOSTANDARD = LVCMOS33;
#
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
#
## SPI Flash
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
##NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
##NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
#
## SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
#
## JOYSTICK
#NET "joyup" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
#NET "joydown" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
#NET "joyleft" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
#NET "joyright" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
#NET "joyfire" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
# SD/MMC
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7

82
cores/JupiterAce/pines_zxuno_Ap.ucf Normal file
View File

@ -0,0 +1,82 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="2" | IOSTANDARD = LVCMOS33;
NET "clk50mhz" PERIOD=20 ns;
#NET "clk12" PERIOD=83 ns;
# Video output
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
#NET "joydown" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
#NET "joyleft" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
#NET "joyright" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
#NET "joyfire" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7

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@ -0,0 +1,85 @@
# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "clk50mhz" PERIOD=20 ns;
#NET "clk12" PERIOD=83 ns;
# Video output
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
# Sound input/output
NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 1 DIN
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 5 DIN
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 6 DIN
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP; # pin 2 DIN
# SRAM
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY6
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY4
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY3
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY2
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY7
#NET "btn2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP; #JOY5

36
cores/JupiterAce/rom.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:12:52 02/09/2014
// Design Name:
// Module Name: rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rom (
input wire clk,
input wire [12:0] a,
output reg [7:0] dout
);
reg [7:0] mem[0:8191];
integer i;
initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
$readmemh ("ace.hex", mem, 0);
end
always @(posedge clk) begin
dout <= mem[a[12:0]];
end
endmodule

19
cores/JupiterAce/tld_jace_spartan6.v
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@ -36,6 +36,7 @@ module tld_jace_spartan6 (
wire clkram; // 50MHz (maybe less if needed) to clock internal RAM/ROM
wire clk65; // 6.5MHz main frequency Jupiter ACE
wire clkcpu; // CPU CLK
wire kbd_reset;
wire [7:0] kbd_rows;
@ -61,19 +62,20 @@ module tld_jace_spartan6 (
always @(posedge clk65)
poweron_reset <= {poweron_reset[6:0],1'b1};
dcmclock reloj_maestro(
.CLKIN_IN(clk50mhz),
.CLKDV_OUT(clk65),
.CLKIN_IBUFG_OUT(clkram),
.CLK0_OUT(),
.LOCKED_OUT()
);
cuatro_relojes system_clocks_pll (
.CLK_IN1(clk50mhz),
.CLK_OUT1(clkram), // for driving synch RAM and ROM = 26.6666 MHz
.CLK_OUT2(clk65), // video clock = 6.66666 MHz
.CLK_OUT3(clkcpu), // CPU clock = 0.5 video clock
.CLK_OUT4() // Super CPU clock (just a test)
);
jupiter_ace the_core (
.clkram(clkram),
.clk65(clk65),
.clkcpu(clkcpu),
.reset(kbd_reset & poweron_reset[7]),
.ear(!ear),
.ear(ear),
.filas(kbd_rows),
.columnas(kbd_columns),
.video(video),
@ -92,5 +94,4 @@ module tld_jace_spartan6 (
.kbd_nmi()
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03:39:55 05/13/2012
// Design Name:
// Module Name: tv80_to_t80_wrapper
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tv80n_wrapper (
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
wire [7:0] d;
T80a TheCPU (
.RESET_n(reset_n),
.CLK_n(clk),
.WAIT_n(wait_n),
.INT_n(int_n),
.NMI_n(nmi_n),
.BUSRQ_n(busrq_n),
.M1_n(m1_n),
.MREQ_n(mreq_n),
.IORQ_n(iorq_n),
.RD_n(rd_n),
.WR_n(wr_n),
.RFSH_n(rfsh_n),
.HALT_n(halt_n),
.BUSAK_n(busak_n),
.A(A),
.D(d),
.SavePC(),
.SaveINT(),
.RestorePC(16'h0000),
.RestoreINT(8'h00),
.RestorePC_n(1'b1)
);
assign dout = d;
assign d = ( (!mreq_n || !iorq_n) && !rd_n)? di :
( (!mreq_n || !iorq_n) && !wr_n)? 8'hZZ :
8'hFF;
endmodule