Añado bootloader_core21_35.asm

firmware/bootloader_core21.hex

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+F3
+31
+00
+00
+EF
+03
+01
+EF
+03
+00
+EF
+02
+06
+EF
+03
+01
+EF
+03
+00
+EF
+02
+C5
+ED
+71
+EF
+FC
+09
+3E
+80
+ED
+79
+ED
+71
+EF
+FD
+01
+00
+00
+00
+00
+01
+3B
+FD
+E1
+ED
+A3
+06
+FE
+ED
+A3
+E9

firmware/bootloader_core21_35.asm

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+
+        include version.asm
+      macro wreg  dir, dato
+        rst     $28
+        defb    dir, dato
+      endm
+
+        output  bootloader.rom
+        define  zxuno_port      $fc3b
+        define  flash_spi       2
+        define  flash_cs        3
+        define  core_addr       $fc
+        define  core_boot       $fd
+
+        di
+        ld      sp, 0
+        wreg    flash_cs, 1     ; desactivamos spi, enviando un 0
+        wreg    flash_cs, 0     ; activamos spi, enviando un 0
+        wreg    flash_spi, 6    ; envío write enable
+        wreg    flash_cs, 1     ; desactivamos spi, enviando un 1
+        wreg    flash_cs, 0     ; activamos spi, enviando un 0
+        wreg    flash_spi, $c5  ; envío wrear
+        out     (c), 0
+      IF  version=2
+        wreg    core_addr, $09
+        ld      a, $80
+      ELSE
+        wreg    core_addr, $0b
+        xor     a
+      ENDIF
+        out     (c), a
+        out     (c), 0
+        wreg    core_boot, 1
+
+        block   $28 - $
+rst28   ld      bc, zxuno_port + $100
+        pop     hl
+        outi
+        ld      b, (zxuno_port >> 8)+2
+        outi
+        jp      (hl)
+

firmware/bootloader_core35.hex

@@ -0,0 +1,51 @@
+F3
+31
+00
+00
+EF
+03
+01
+EF
+03
+00
+EF
+02
+06
+EF
+03
+01
+EF
+03
+00
+EF
+02
+C5
+ED
+71
+EF
+FC
+0B
+AF
+ED
+79
+ED
+71
+EF
+FD
+01
+00
+00
+00
+00
+00
+01
+3B
+FD
+E1
+ED
+A3
+06
+FE
+ED
+A3
+E9