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Añado test_pal_interlaced_progressive

This commit is contained in:
antoniovillena 2016-07-10 16:32:58 +02:00
parent b6ed4d098d
commit f169216cc5
10 changed files with 727 additions and 0 deletions
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159
cores/test/test_pal_interlaced_progressive/genframe.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:59 06/28/2016
// Design Name:
// Module Name: genframe
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module genframe (
input wire clk, // 10 MHz
input wire mode, // 0: interlaced. 1: progressive
output reg [2:0] r,
output reg [2:0] g,
output reg [2:0] b,
output reg csync
);
reg [9:0] hc = 10'd0;
reg [9:0] vc = 10'd0;
reg intprog = 1'b0; // internal copy of mode
// Counters (horizontal and vertical).
// Horizontal counts tenths of microseconds. Vertical counts lines.
always @(posedge clk) begin
if (hc != 10'd639) begin
hc <= hc + 10'd1;
end
else begin
hc <= 10'd0;
if (intprog == 1'b0) begin
if (vc != 624) begin
vc <= vc + 10'd1;
end
else begin
vc <= 10'd0;
intprog <= mode;
end
end
else begin
if (vc != 311) begin
vc <= vc + 10'd1;
end
else begin
vc <= 10'd0;
intprog <= mode;
end
end
end
end
// Sync generation (info taken from http://martin.hinner.info/vga/pal.html )
reg videoen;
always @* begin
csync = 1'b1;
videoen = 1'b0;
if (vc == 10'd0 ||
vc == 10'd1 ||
vc == 10'd313 ||
vc == 10'd314) begin
if ((hc >= 10'd0 && hc < 10'd300) || (hc >= 10'd320 && hc < 10'd620)) begin
csync = 1'b0;
end
end
else if (vc == 10'd2) begin
if ((hc >= 10'd0 && hc < 10'd300) || (hc >= 10'd320 && hc < 10'd340)) begin
csync = 1'b0;
end
end
else if (vc == 10'd312) begin
if ((hc >= 10'd0 && hc < 10'd20) || (hc >= 10'd320 && hc < 10'd620)) begin
csync = 1'b0;
end
end
else if (vc == 10'd3 ||
vc == 10'd4 ||
vc == 10'd310 ||
vc == 10'd311 ||
vc == 10'd315 ||
vc == 10'd316 ||
vc == 10'd622 ||
vc == 10'd623 ||
vc == 10'd624 ||
(vc == 10'd309 && intprog == 1'b1)) begin
if ((hc >= 10'd0 && hc < 10'd20) || (hc >= 10'd320 && hc < 10'd340)) begin
csync = 1'b0;
end
end
else begin // we are in one visible scanline
if (hc >= 10'd0 && hc < 10'd40) begin
csync = 1'b0;
end
else if (hc >= 10'd120) begin
videoen = 1'b1;
end
end
end
// Color bars generation
always @* begin
r = 3'b000;
g = 3'b000;
b = 3'b000;
if (videoen == 1'b1) begin
if (hc >= 120+65*0 && hc < 120+65*1) begin
r = 3'b111;
g = 3'b111;
b = 3'b111;
end
else if (hc >= 120+65*1 && hc < 120+65*2) begin
r = 3'b111;
g = 3'b111;
b = 3'b000;
end
else if (hc >= 120+65*2 && hc < 120+65*3) begin
r = 3'b000;
g = 3'b111;
b = 3'b111;
end
else if (hc >= 120+65*3 && hc < 120+65*4) begin
r = 3'b000;
g = 3'b111;
b = 3'b000;
end
else if (hc >= 120+65*4 && hc < 120+65*5) begin
r = 3'b111;
g = 3'b000;
b = 3'b111;
end
else if (hc >= 120+65*5 && hc < 120+65*6) begin
r = 3'b111;
g = 3'b000;
b = 3'b000;
end
else if (hc >= 120+65*6 && hc < 120+65*7) begin
r = 3'b000;
g = 3'b000;
b = 3'b111;
end
else if (hc >= 120+65*7 && hc < 120+65*8) begin
r = 3'b000;
g = 3'b000;
b = 3'b000;
end
end
end
endmodule

8
cores/test/test_pal_interlaced_progressive/make.bat Normal file
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SET machine=tld_test_pal_intprog
SET speed=2
SET ruta_ucf=pines
SET ruta_bat=..\..\
rem call %ruta_bat%genxst.bat
rem call %ruta_bat%generar.bat v2_v3
call %ruta_bat%generar.bat v4
rem call %ruta_bat%generar.bat Ap

80
cores/test/test_pal_interlaced_progressive/master_clk.v Normal file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.4
// \ \ Application : xaw2verilog
// / / Filename : master_clk.v
// /___/ /\ Timestamp : 05/02/2013 05:55:56
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle C:/Users/rodriguj/Documents/proyectos_xilinx/ula_replacement_tests/test3/ipcore_dir/master_clk.xaw -st master_clk.v
//Design Name: master_clk
//Device: xc3s100e-4vq100
//
// Module master_clk
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.20 ns
`timescale 1ns / 1ps
module master_clk(CLKIN_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT);
input CLKIN_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(5.0), .CLKFX_DIVIDE(20),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule

90
cores/test/test_pal_interlaced_progressive/pines_zxuno_Ap.ucf Normal file
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# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P2" | IOSTANDARD = LVCMOS33;
# Video output
NET "r<2>" LOC="P97" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P95" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P94" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P87" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P93" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P51" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P50" | IOSTANDARD = LVCMOS33;
# Sound input/output
#NET "audio_out_left" LOC="P98" | IOSTANDARD = LVCMOS33;
#NET "audio_out_right" LOC="P99" | IOSTANDARD = LVCMOS33;
#NET "ear" LOC="P1" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P143" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "dataps2" LOC="P142" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P57" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P56" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P134" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P78" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P80" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P79" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P81" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P58" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P59" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P67" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P74" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P66" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P75" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros
NET "clk" PERIOD=100 ns;

90
cores/test/test_pal_interlaced_progressive/pines_zxuno_v2_v3.ucf Normal file
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# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P10" | IOSTANDARD = LVCMOS33;
# Video output
NET "r<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P67" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P66" | IOSTANDARD = LVCMOS33;
# Sound input/output
#NET "audio_out_left" LOC="P8" | IOSTANDARD = LVCMOS33;
#NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
#NET "ear" LOC="P105" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "dataps2" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P94" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P99" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P134" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P121" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P118" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros
NET "clk" PERIOD=100 ns;

90
cores/test/test_pal_interlaced_progressive/pines_zxuno_v4.ucf Normal file
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# Clocks & debug
NET "clk50mhz" LOC="P55" | IOSTANDARD = LVCMOS33 | PERIOD=20.0ns;
#NET "testled" LOC="P11" | IOSTANDARD = LVCMOS33;
# Video output
NET "r<2>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "r<1>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "r<0>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "g<2>" LOC="P84" | IOSTANDARD = LVCMOS33;
NET "g<1>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "g<0>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "b<2>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "b<1>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "b<0>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "csync" LOC="P87" | IOSTANDARD = LVCMOS33;
#NET "vsync" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "stdn" LOC="P66" | IOSTANDARD = LVCMOS33;
NET "stdnb" LOC="P67" | IOSTANDARD = LVCMOS33;
# Sound input/output
#NET "audio_out_left" LOC="P10" | IOSTANDARD = LVCMOS33;
#NET "audio_out_right" LOC="P9" | IOSTANDARD = LVCMOS33;
#NET "ear" LOC="P94" | IOSTANDARD = LVCMOS33;
# Keyboard and mouse
NET "clkps2" LOC="P99" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "dataps2" LOC="P98" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mouseclk" LOC="P95" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "mousedata" LOC="P97" | IOSTANDARD = LVCMOS33 | PULLUP;
# SRAM
#NET "sram_addr<0>" LOC="P141" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<1>" LOC="P139" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<2>" LOC="P137" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<3>" LOC="P134" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<4>" LOC="P133" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<5>" LOC="P120" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<6>" LOC="P118" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<7>" LOC="P116" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<8>" LOC="P114" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<9>" LOC="P112" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<10>" LOC="P104" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<11>" LOC="P102" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<12>" LOC="P101" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<13>" LOC="P100" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<14>" LOC="P111" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<15>" LOC="P131" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<16>" LOC="P138" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<17>" LOC="P140" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<18>" LOC="P142" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<19>" LOC="P105" | IOSTANDARD = LVCMOS33;
#NET "sram_addr<20>" LOC="P143" | IOSTANDARD = LVCMOS33;
#NET "sram_data<0>" LOC="P132" | IOSTANDARD = LVCMOS33;
#NET "sram_data<1>" LOC="P127" | IOSTANDARD = LVCMOS33;
#NET "sram_data<2>" LOC="P124" | IOSTANDARD = LVCMOS33;
#NET "sram_data<3>" LOC="P123" | IOSTANDARD = LVCMOS33;
#NET "sram_data<4>" LOC="P115" | IOSTANDARD = LVCMOS33;
#NET "sram_data<5>" LOC="P117" | IOSTANDARD = LVCMOS33;
#NET "sram_data<6>" LOC="P119" | IOSTANDARD = LVCMOS33;
#NET "sram_data<7>" LOC="P126" | IOSTANDARD = LVCMOS33;
#NET "sram_we_n" LOC="P121" | IOSTANDARD = LVCMOS33;
# SPI Flash
#NET "flash_cs_n" LOC="P38" | IOSTANDARD = LVCMOS33;
#NET "flash_clk" LOC="P70" | IOSTANDARD = LVCMOS33;
#NET "flash_mosi" LOC="P64" | IOSTANDARD = LVCMOS33;
#NET "flash_miso" LOC="P65" | IOSTANDARD = LVCMOS33;
#NET "flash_ext1" LOC="P62" | IOSTANDARD = LVCMOS33;
#NET "flash_ext2" LOC="P61" | IOSTANDARD = LVCMOS33;
# SD/MMC
#NET "sd_cs_n" LOC="P59" | IOSTANDARD = LVCMOS33;
#NET "sd_clk" LOC="P75" | IOSTANDARD = LVCMOS33;
#NET "sd_mosi" LOC="P74" | IOSTANDARD = LVCMOS33;
#NET "sd_miso" LOC="P78" | IOSTANDARD = LVCMOS33;
# JOYSTICK
#NET "joyup" LOC="P1" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joydown" LOC="P5" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyleft" LOC="P6" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyright" LOC="P7" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire" LOC="P2" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire2" LOC="P8" | IOSTANDARD = LVCMOS33 | PULLUP;
#NET "joyfire3" LOC="P39" | IOSTANDARD = LVCMOS33 | PULLUP;
# Otros
NET "clk" PERIOD=100 ns;

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`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:16:31 12/26/2014
// Design Name:
// Module Name: ps2_port
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_port (
input wire clk, // se recomienda 1 MHz <= clk <= 600 MHz
input wire enable_rcv, // habilitar la maquina de estados de recepcion
input wire ps2clk_ext,
input wire ps2data_ext,
output wire kb_interrupt, // a 1 durante 1 clk para indicar nueva tecla recibida
output reg [7:0] scancode, // make o breakcode de la tecla
output wire released, // soltada=1, pulsada=0
output wire extended // extendida=1, no extendida=0
);
`define RCVSTART 2'b00
`define RCVDATA 2'b01
`define RCVPARITY 2'b10
`define RCVSTOP 2'b11
reg [7:0] key = 8'h00;
// Fase de sincronizacion de señales externas con el reloj del sistema
reg [1:0] ps2clk_synchr;
reg [1:0] ps2dat_synchr;
wire ps2clk = ps2clk_synchr[1];
wire ps2data = ps2dat_synchr[1];
always @(posedge clk) begin
ps2clk_synchr[0] <= ps2clk_ext;
ps2clk_synchr[1] <= ps2clk_synchr[0];
ps2dat_synchr[0] <= ps2data_ext;
ps2dat_synchr[1] <= ps2dat_synchr[0];
end
// De-glitcher. Sólo detecto flanco de bajada
reg [15:0] negedgedetect = 16'h0000;
always @(posedge clk) begin
negedgedetect <= {negedgedetect[14:0], ps2clk};
end
wire ps2clkedge = (negedgedetect == 16'hF000)? 1'b1 : 1'b0;
// Paridad instantánea de los bits recibidos
wire paritycalculated = ^key;
// Contador de time-out. Al llegar a 65536 ciclos sin que ocurra
// un flanco de bajada en PS2CLK, volvemos al estado inicial
reg [15:0] timeoutcnt = 16'h0000;
reg [1:0] state = `RCVSTART;
reg [1:0] regextended = 2'b00;
reg [1:0] regreleased = 2'b00;
reg rkb_interrupt = 1'b0;
assign released = regreleased[1];
assign extended = regextended[1];
assign kb_interrupt = rkb_interrupt;
always @(posedge clk) begin
if (rkb_interrupt == 1'b1) begin
rkb_interrupt <= 1'b0;
end
if (ps2clkedge && enable_rcv) begin
timeoutcnt <= 16'h0000;
if (state == `RCVSTART && ps2data == 1'b0) begin
state <= `RCVDATA;
key <= 8'h80;
end
else if (state == `RCVDATA) begin
key <= {ps2data, key[7:1]};
if (key[0] == 1'b1) begin
state <= `RCVPARITY;
end
end
else if (state == `RCVPARITY) begin
if (ps2data^paritycalculated == 1'b1) begin
state <= `RCVSTOP;
end
else begin
state <= `RCVSTART;
end
end
else if (state == `RCVSTOP) begin
state <= `RCVSTART;
if (ps2data == 1'b1) begin
scancode <= key;
if (key == 8'hE0) begin
regextended <= 2'b01;
end
else if (key == 8'hF0) begin
regreleased <= 2'b01;
end
else begin
regextended <= {regextended[0], 1'b0};
regreleased <= {regreleased[0], 1'b0};
rkb_interrupt <= 1'b1;
end
end
end
end
else begin
timeoutcnt <= timeoutcnt + 1;
if (timeoutcnt == 16'hFFFF) begin
state <= `RCVSTART;
end
end
end
endmodule

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verilog work "ps2_port.v"
verilog work "master_clk.v"
verilog work "genframe.v"
verilog work "tld_test_pal_intprog.v"

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cores/test/test_pal_interlaced_progressive/tld_test_pal_intprog.ut Normal file
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-w
-g Binary:no
-g Compress
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

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cores/test/test_pal_interlaced_progressive/tld_test_pal_intprog.xst Normal file
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set -tmpdir "projnav.tmp"
set -xsthdpdir "xst"
run
-ifn tld_test_pal_intprog.prj
-ofn tld_test_pal_intprog
-ofmt NGC
-p xc6slx9-2-tqg144
-top tld_test_pal_intprog
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5