mirror of https://github.com/zxdos/zxuno.git
92 lines
4.0 KiB
Verilog
92 lines
4.0 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 01:22:22 2020-02-09 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module clk_enables (
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input wire clk,
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input wire CPUContention,
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input wire [3:0] cpu_speed,
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output wire clk14en,
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output wire clk7en,
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output wire clk7en_n,
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output wire clk35en,
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output wire clk35en_n,
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output wire clk175en,
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output reg clkcpu_enable
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);
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`include "config.vh"
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// 28 MHz master clock
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reg [15:0] divclk = 16'h00000001;
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always @(posedge clk)
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divclk <= {divclk[14:0], divclk[15]};
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assign clk14en = divclk[0] | divclk[2] | divclk[4] | divclk[6] | divclk[8] | divclk[10] | divclk[12] | divclk[14];
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assign clk7en = divclk[0] | divclk[4] | divclk[8] | divclk[12];
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assign clk7en_n = divclk[2] | divclk[6] | divclk[10] | divclk[14];
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assign clk35en = divclk[0] | divclk[8];
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assign clk35en_n = divclk[7] | divclk[15];
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assign clk175en = divclk[0];
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// This is to support 56 MHz master clock. Didn't meet timing closure on UNO
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// reg [31:0] divclk = 32'h00000001;
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// always @(posedge clk)
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// divclk <= {divclk[30:0], divclk[31]};
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// assign clk28en = divclk[0] | divclk[2] | divclk[4] | divclk[6] | divclk[8] | divclk[10] | divclk[12] | divclk[14] | divclk[16] | divclk[18] | divclk[20] | divclk[22] | divclk[24] | divclk[26] | divclk[28] | divclk[30];
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// assign clk14en = divclk[0] | divclk[4] | divclk[8] | divclk[12] | divclk[16] | divclk[20] | divclk[24] | divclk[28];
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// assign clk7en = divclk[0] | divclk[8] | divclk[16] | divclk[24];
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// assign clk7nen = divclk[4] | divclk[12] | divclk[20] | divclk[28];
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// assign clk35en = divclk[0] | divclk[16];
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// assign clk35en_n = divclk[15] | divclk[31];
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// assign clk175en = divclk[0];
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// This is to support 42 MHz master clock. Unfortunately, it looks ugly when VGA is used :(
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// reg [23:0] divclk = 24'h000001;
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// always @(posedge clk)
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// divclk <= {divclk[22:0], divclk[23]};
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// assign clk28en = divclk[0] | divclk[1] | divclk[3] | divclk[4] | divclk[6] | divclk[7] | divclk[9] | divclk[10] | divclk[12] | divclk[13] | divclk[15] | divclk[16] | divclk[18] | divclk[19] | divclk[21] | divclk[22];
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// assign clk14en = divclk[0] | divclk[3] | divclk[6] | divclk[9] | divclk[12] | divclk[15] | divclk[18] | divclk[21];
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// assign clk7en = divclk[0] | divclk[6] | divclk[12] | divclk[18];
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// assign clk7nen = divclk[3] | divclk[9] | divclk[15] | divclk[21];
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// assign clk35en = divclk[0] | divclk[12];
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// assign clk35en_n = divclk[23] | divclk[11];
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// assign clk175en = divclk[0];
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`ifdef CPU_TURBO_OPTION
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always @* begin
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casez (cpu_speed[2:0])
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3'b1?? : clkcpu_enable = 1'b1;
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3'b000 : clkcpu_enable = clk35en && !CPUContention;
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3'b001 : clkcpu_enable = clk7en;
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3'b010 : clkcpu_enable = clk14en;
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3'b011 : clkcpu_enable = 1'b1;
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endcase
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end
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`else
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always @*
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clkcpu_enable = clk35en && !CPUContention;
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`endif
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endmodule
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