mirror of https://github.com/zxdos/zxuno.git
127 lines
4.2 KiB
Verilog
127 lines
4.2 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 00:24:56 2016-05-08 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module control_enable_options(
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output reg oe,
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output wire disable_ay,
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output wire disable_turboay,
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output wire disable_7ffd,
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output wire disable_1ffd,
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output wire disable_romsel7f,
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output wire disable_romsel1f,
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output wire enable_timexmmu,
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output wire disable_spisd,
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output wire disable_timexscr,
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output wire disable_ulaplus,
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output wire disable_radas,
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output wire disable_specdrum,
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output wire disable_mixer,
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output wire joy_splitter
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);
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`include "config.vh"
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reg [7:0] devoptions = 8'b00101000; // initial value. Modo 128K
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reg [7:0] devopts2 = 8'h00; // initial value
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assign disable_ay = devoptions[0];
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`ifdef TURBOSUND_SUPPORT
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assign disable_turboay = devoptions[1];
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`else
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assign disable_turboay = 1'b1;
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`endif
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assign disable_7ffd = devoptions[2];
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assign disable_1ffd = devoptions[3];
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assign disable_romsel7f = devoptions[4];
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assign disable_romsel1f = devoptions[5];
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`ifdef ULA_TIMEX_SUPPORT
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assign enable_timexmmu = devoptions[6];
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`else
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assign enable_timexmmu = 1'b0;
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`endif
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`ifdef DIVMMC_SUPPORT
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assign disable_spisd = devoptions[7];
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`else
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assign disable_spisd = 1'b1;
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`endif
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`ifdef ULAPLUS_SUPPORT
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assign disable_ulaplus = devopts2[0];
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`else
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assign disable_ulaplus = 1'b1;
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`endif
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`ifdef ULA_TIMEX_SUPPORT
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assign disable_timexscr = devopts2[1];
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`else
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assign disable_timexscr = 1'b1;
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`endif
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`ifdef ULA_RADASTAN_SUPPORT
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assign disable_radas = devopts2[2];
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`else
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assign disable_radas = 1'b1;
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`endif
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`ifdef SPECDRUM_COVOX_SUPPORT
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assign disable_specdrum = devopts2[3];
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`else
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assign disable_specdrum = 1'b1;
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`endif
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assign disable_mixer = devopts2[4];
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`ifdef JOYSPLITTER_SUPPORT
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assign joy_splitter = devopts2[5];
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`else
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assign joy_splitter = 1'b0;
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`endif
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always @(posedge clk) begin
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if (rst_n == 1'b0) begin
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devoptions <= 8'h00; // or after a hardware reset (not implemented yet)
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devopts2 <= 8'h00;
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end
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else if (zxuno_addr == DEVOPTIONS && zxuno_regwr == 1'b1)
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devoptions <= din;
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else if (zxuno_addr == DEVOPTS2 && zxuno_regwr == 1'b1)
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devopts2 <= din;
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end
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always @* begin
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oe = 1'b0;
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dout = 8'hFF;
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if (zxuno_regrd == 1'b1)
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if (zxuno_addr == DEVOPTIONS) begin
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oe = 1'b1;
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dout = { disable_spisd, enable_timexmmu, devoptions[5:2], disable_turboay, devoptions[0] };
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end
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else if (zxuno_addr == DEVOPTS2) begin
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oe = 1'b1;
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dout = { devopts2[7:4], disable_specdrum, disable_radas, disable_timexscr, disable_ulaplus };
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end
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end
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endmodule
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