mirror of https://github.com/zxdos/zxuno.git
80 lines
2.8 KiB
Verilog
80 lines
2.8 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 19:24:57 2015-06-12 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module rasterint_ctrl (
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output reg oe,
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output wire rasterint_enable,
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output wire vretraceint_disable,
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output wire [8:0] raster_line,
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input wire raster_int_in_progress
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);
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`include "config.vh"
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reg [7:0] rasterline_reg = 8'hFF;
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reg raster_enable = 1'b0;
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reg vretrace_disable = 1'b0;
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reg raster_8th_bit = 1'b1;
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assign raster_line = {raster_8th_bit, rasterline_reg};
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assign rasterint_enable = raster_enable;
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assign vretraceint_disable = vretrace_disable;
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always @(posedge clk) begin
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if (rst_n == 1'b0) begin
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raster_enable <= 1'b0;
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vretrace_disable <= 1'b0;
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raster_8th_bit <= 1'b1;
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rasterline_reg <= 8'hFF;
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end
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else begin
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if (zxuno_addr == RASTERLINE && zxuno_regwr == 1'b1)
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rasterline_reg <= din;
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if (zxuno_addr == RASTERCTRL && zxuno_regwr == 1'b1)
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{vretrace_disable, raster_enable, raster_8th_bit} <= din[2:0];
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end
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end
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always @* begin
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dout = 8'hFF;
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oe = 1'b0;
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if (zxuno_addr == RASTERLINE && zxuno_regrd == 1'b1) begin
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dout = rasterline_reg;
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oe = 1'b1;
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end
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if (zxuno_addr == RASTERCTRL && zxuno_regrd == 1'b1) begin
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dout = {raster_int_in_progress, 4'b0000, vretrace_disable, raster_enable, raster_8th_bit};
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oe = 1'b1;
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end
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end
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endmodule
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