mirror of https://github.com/zxdos/zxuno.git
57 lines
2.1 KiB
Verilog
57 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 01:22:53 2017-06-20 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module control_ad724 (
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input wire clk,
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input wire poweron_rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output wire [7:0] dout,
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output wire oe,
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output wire ad724_xtal,
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output wire ad724_mode,
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output wire ad724_enable_gencolorclk
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);
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`include "config.vh"
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assign oe = (zxuno_addr == CTRLAD724 && zxuno_regrd == 1'b1);
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assign dout = ad724;
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reg [7:0] ad724 = 8'h00; // initial value
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assign ad724_xtal = ~ad724[0];
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assign ad724_mode = ad724[0];
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assign ad724_enable_gencolorclk = ad724[1];
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always @(posedge clk) begin
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if (poweron_rst_n == 1'b0)
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ad724 <= 8'h00; // or after a hardware reset (not implemented yet)
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else if (zxuno_addr == CTRLAD724 && zxuno_regwr == 1'b1)
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ad724 <= din;
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end
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endmodule
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