mirror of https://github.com/zxdos/zxuno.git
116 lines
4.1 KiB
Verilog
116 lines
4.1 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 00:52:19 2014-03-03 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module flash_and_sd (
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input wire clk, //
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input wire [15:0] a, //
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input wire iorq_n, // Señales de control de E/S estándar
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input wire rd_n, // para manejar los puertos ZXMMC y DIVMMC
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input wire wr_n, //
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input wire [7:0] addr, // numero de registro almacenado en puerto ZXUNOADDR. Este módulo atiende a $02 y $03
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input wire ior, // lectura a un registro ZXUNO
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input wire iow, // escritura a un registro ZXUNO
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input wire [7:0] din, // del bus de datos de salida de la CPU
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output wire [7:0] dout, // al bus de datos de entrada de la CPU
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output wire oe, // el dato en dout es válido
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output wire wait_n, // pausa para la CPU. Mejora estabilidad
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input wire in_boot_mode,// Esta interfaz sólo es válida en modo boot
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output wire flash_cs_n, //
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output wire flash_clk, // Interface SPI con la Flash
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output wire flash_di, //
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input wire flash_do, //
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input wire disable_spisd,
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output wire sd_cs_n, //
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output wire sd_clk, // Interface SPI con la SD/MMC
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output wire sd_mosi, //
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input wire sd_miso //
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);
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`include "config.vh"
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wire sclk,miso,mosi;
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wire spi_transfer_in_progress;
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assign wait_n = ~spi_transfer_in_progress;
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reg flashpincs = 1'b1;
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assign flash_cs_n = flashpincs;
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reg sdpincs = 1'b1;
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assign sd_cs_n = sdpincs;
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assign flash_clk = sclk;
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assign flash_di = mosi;
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assign sd_clk = sclk;
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assign sd_mosi = mosi;
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assign miso = (sd_cs_n == 1'b0)? sd_miso : flash_do;
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// Control del pin CS de la flash y de la SD
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always @(posedge clk) begin
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if (addr == CSPIN && iow && in_boot_mode) begin
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flashpincs <= din[0];
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sdpincs <= 1'b1; // si accedemos a la flash para cambiar su estado CS, automaticamente deshabilitamos la SD
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end
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else if (!disable_spisd && !iorq_n && (a[7:0]==SDCS || a[7:0]==DIVCS) && !wr_n) begin
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sdpincs <= din[0];
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flashpincs <= 1'b1; // y lo mismo hacemos si es la SD a la que estamos accediendo
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end
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end
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// Control del modulo SPI
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reg enviar_dato;
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reg recibir_dato;
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always @* begin
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if ((addr==SPIPORT && ior && in_boot_mode) || (!disable_spisd && !iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !rd_n))
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recibir_dato = 1'b1;
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else
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recibir_dato = 1'b0;
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if ((addr==SPIPORT && iow && in_boot_mode) || (!disable_spisd && !iorq_n && (a[7:0]==SDSPI || a[7:0]==DIVSPI) && !wr_n))
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enviar_dato = 1'b1;
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else
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enviar_dato = 1'b0;
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end
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// Instanciación del modulo SPI
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spi mi_spi (
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.clk(clk),
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.clken(1'b1),
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.enviar_dato(enviar_dato),
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.recibir_dato(recibir_dato),
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.din(din),
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.dout(dout),
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.oe(oe),
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.spi_transfer_in_progress(spi_transfer_in_progress),
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.sclk(sclk),
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.mosi(mosi),
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.miso(miso)
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);
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endmodule
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