mirror of https://github.com/zxdos/zxuno.git
67 lines
2.3 KiB
Verilog
67 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 08:50:32 2019-07-31 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module i2s_decoder (
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input wire clk,
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input wire sck,
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input wire ws,
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input wire sd,
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output reg [15:0] left_out,
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output reg [15:0] right_out
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);
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reg [1:0] sck_synch = 2'b00, ws_synch = 2'b00, sd_synch = 2'b00;
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wire scks = sck_synch[1], wss = ws_synch[1], sds = sd_synch[1];
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reg scks_prev = 1'b0, wss_prev = 1'b0;
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reg [17:0] sreg = 17'b0_0000_0000_0000_0001;
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always @(posedge clk) begin
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// sincronizar señales de entrada
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sck_synch[1] <= sck_synch[0];
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sck_synch[0] <= sck;
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ws_synch[1] <= ws_synch[0];
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ws_synch[0] <= ws;
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sd_synch[1] <= sd_synch[0];
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sd_synch[0] <= sd;
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scks_prev <= scks;
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if (scks_prev == 1'b0 && scks == 1'b1) begin // flanco positivo de SCK
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wss_prev <= wss;
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if (wss_prev != wss) begin // ha ocurrido flanco en WS ?
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if (wss_prev == 1'b0)
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left_out <= sreg[15:0];
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else
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right_out <= sreg[15:0];
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sreg <= 17'b0_0000_0000_0000_0001;
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end
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else begin
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if (sreg[16] == 1'b0) begin
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sreg <= {sreg[15:0], sds};
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end
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end
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end
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end
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endmodule
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