mirror of https://github.com/zxdos/zxuno.git
76 lines
2.8 KiB
Verilog
76 lines
2.8 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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// This file is part of the ZXUNO Spectrum core.
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// Creation date is 23:49:58 2020-02-27 by Miguel Angel Rodriguez Jodar
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// (c)2014-2020 ZXUNO association.
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// ZXUNO official repository: http://svn.zxuno.com/svn/zxuno
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// Username: guest Password: zxuno
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// Github repository for this core: https://github.com/mcleod-ideafix/zxuno_spectrum_core
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//
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// ZXUNO Spectrum core is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// ZXUNO Spectrum core is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with the ZXUNO Spectrum core. If not, see <https://www.gnu.org/licenses/>.
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//
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// Any distributed copy of this file must keep this notice intact.
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module spi (
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input wire clk, //
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input wire clken, //
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input wire enviar_dato, // a 1 para indicar que queremos enviar un dato por SPI
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input wire recibir_dato,// a 1 para indicar que queremos recibir un dato
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input wire [7:0] din, // del bus de datos de salida de la CPU
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output reg [7:0] dout, // al bus de datos de entrada de la CPU
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output wire oe, // el dato en dout es válido
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output wire spi_transfer_in_progress,
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output wire sclk, // Interface SPI
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output wire mosi, //
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input wire miso //
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);
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reg enviar_dato_bf = 1'b0;
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reg recibir_dato_bf = 1'b0;
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wire enviar = ~enviar_dato_bf & enviar_dato;
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wire recibir =~recibir_dato_bf & recibir_dato;
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always @(posedge clk) begin
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enviar_dato_bf <= enviar_dato;
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recibir_dato_bf <= recibir_dato;
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end
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reg [7:0] spireg = 8'hFF;
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reg [4:0] count = 5'b10000;
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assign mosi = spireg[7];
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assign sclk = count[0];
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assign spi_transfer_in_progress = ~count[4];
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assign oe = recibir_dato;
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always @(posedge clk) begin
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if (enviar == 1'b1) begin
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spireg <= din;
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count <= 5'b00000;
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end
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else if (recibir == 1'b1) begin
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dout <= spireg;
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spireg <= 8'hFF;
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count <= 5'b00000;
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end
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else if (clken == 1'b1) begin
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if (count[4] == 1'b0) begin
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count <= count + 5'd1;
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if (sclk == 1'b1) begin // tengo mis dudas sobre si usar 0 o 1 aquí. En principio, debería ser 0, pero funciona con 1 (???)
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spireg <= {spireg[6:0], miso};
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end
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end
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end
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end
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endmodule
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