mirror of https://github.com/zxdos/zxuno.git
95 lines
1.8 KiB
VHDL
95 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity io is
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Port(
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clk: in STD_LOGIC;
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WR_n: in STD_LOGIC;
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RD_n: in STD_LOGIC;
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A: in STD_LOGIC_VECTOR (7 downto 0);
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D_in: in STD_LOGIC_VECTOR (7 downto 0);
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D_out: out STD_LOGIC_VECTOR (7 downto 0);
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J1_up: in STD_LOGIC;
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J1_down: in STD_LOGIC;
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J1_left: in STD_LOGIC;
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J1_right:in STD_LOGIC;
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J1_tl: in STD_LOGIC;
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J1_tr: inout STD_LOGIC;
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J2_up: in STD_LOGIC;
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J2_down: in STD_LOGIC;
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J2_left: in STD_LOGIC;
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J2_right:in STD_LOGIC;
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J2_tl: in STD_LOGIC;
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J2_tr: inout STD_LOGIC;
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RESET: in STD_LOGIC);
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end io;
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architecture rtl of io is
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signal ctrl: std_logic_vector(7 downto 0) := (others=>'1');
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begin
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process (clk)
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begin
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if rising_edge(clk) then
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if WR_n='0' then
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ctrl <= D_in;
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end if;
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end if;
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end process;
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J1_tr <= ctrl(4) when ctrl(0)='0' else 'Z';
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J2_tr <= ctrl(6) when ctrl(2)='0' else 'Z';
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process (clk)
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begin
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if rising_edge(clk) then
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if RD_n='0' then
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if A(0)='0' then
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D_out(7) <= J2_down;
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D_out(6) <= J2_up;
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-- 5=j1_tr
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if ctrl(0)='0' then
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D_out(5) <= ctrl(4);
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else
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D_out(5) <= J1_tr;
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end if;
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D_out(4) <= J1_tl;
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D_out(3) <= J1_right;
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D_out(2) <= J1_left;
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D_out(1) <= J1_down;
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D_out(0) <= J1_up;
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else
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-- 7=j2_th
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if ctrl(3)='0' then
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D_out(7) <= ctrl(7);
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else
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D_out(7) <= '0';
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end if;
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-- 6=j1_th
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if ctrl(1)='0' then
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D_out(6) <= ctrl(5);
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else
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D_out(6) <= '0';
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end if;
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D_out(5) <= '1';
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D_out(4) <= RESET; --Q
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-- D_out(4) <= '1';
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-- 4=j2_tr
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if ctrl(2)='0' then
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D_out(3) <= ctrl(6);
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else
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D_out(3) <= J2_tr;
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end if;
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D_out(2) <= J2_tl;
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D_out(1) <= J2_right;
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D_out(0) <= J2_left;
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end if;
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end if;
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end if;
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end process;
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end rtl;
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