History

antoniovillena 3864d38abd Cambio lo settings de todos los cores con external clock a 50Mhz		2016-07-16 01:37:30 +02:00
..
src	Ya compilan los 9 cores	2016-07-08 10:53:36 +02:00
xilinx	Cambio lo settings de todos los cores con external clock a 50Mhz	2016-07-16 01:37:30 +02:00
LICENSE	Commit de test1	2016-04-28 14:00:26 +02:00
README.md	Commit de test1	2016-04-28 14:00:26 +02:00

fpganes port for ZXUNO 2016 DistWave

Original readme:

fpganes

This is the source code for my FPGA NES.

It's designed to run on the Nexys4 board and built with Xilinx ISE.

Use "loader" to download ROMS to it over the built-in UART.

"loader" also transmits joypad commands from my USB joypad to the FPGA across UART.