mirror of https://github.com/zxdos/zxuno.git
73 lines
1.5 KiB
VHDL
73 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity mixer is
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port
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(
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clock : in std_logic;
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reset : in std_logic;
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speaker : in std_logic;
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ear : in std_logic;
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mic : in std_logic;
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a : in std_logic_vector(7 downto 0);
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b : in std_logic_vector(7 downto 0);
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c : in std_logic_vector(7 downto 0);
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l : out std_logic;
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r : out std_logic
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);
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end;
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architecture behavioral of mixer is
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signal src : std_logic_vector(2 downto 0);
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signal ula : std_logic_vector(7 downto 0);
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signal mixl : std_logic_vector(7 downto 0);
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signal mixr : std_logic_vector(7 downto 0);
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begin
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src <= ear&mic&speaker;
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ula <= x"11" when src = "000"
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else x"24" when src = "010"
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else x"B8" when src = "001"
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else x"C0" when src = "011"
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else x"16" when src = "100"
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else x"30" when src = "110"
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else x"F4" when src = "101"
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else x"FF";
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process(clock)
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variable tmp : std_logic_vector(1 downto 0) := (others => '0');
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begin
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if falling_edge(clock)
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then
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case tmp is
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when "00" => mixl <= a; mixr <= b;
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when "01" => mixl <= c; mixr <= c;
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when "10" => mixl <= a; mixr <= b;
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when "11" => mixl <= ula; mixr <= ula;
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when others =>
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end case;
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tmp := tmp+1;
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end if;
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end process;
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UdacL: entity work.dac port map
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(
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clock => clock,
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reset => reset,
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i => mixl,
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o => l
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);
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UdacR: entity work.dac port map
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(
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clock => clock,
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reset => reset,
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i => mixr,
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o => r
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);
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end;
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