mirror of https://github.com/zxdos/zxuno.git
40 lines
904 B
Verilog
40 lines
904 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:12:52 02/09/2014
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// Design Name:
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// Module Name: rom
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rom (
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input wire clk,
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input wire [13:0] a,
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output reg [7:0] dout
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);
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reg [7:0] mem[0:8191];
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integer i;
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initial begin // usa $readmemb/$readmemh dependiendo del formato del fichero que contenga la ROM
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for (i=0;i<8192;i=i+1) begin
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mem[i] = 8'h00;
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end
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$readmemh ("bootloader_hex.txt", mem, 0);
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end
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always @(posedge clk) begin
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dout <= mem[a[12:0]];
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end
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endmodule
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