mirror of https://github.com/zxdos/zxuno.git
121 lines
2.8 KiB
Makefile
121 lines
2.8 KiB
Makefile
# Makefile for the Apple ][-on-an-FPGA project
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#
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# Mostly creates an archive, prepares the ROM images, and run test benches
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#
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# DOES NOT compile the VHDL for the FPGA. This is done within Quartus.
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#
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# Stephen A. Edwards, Columbia University, sedwards@cs.columbia.edu
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VERSION = 1.2
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NAME = apple2fpga-$(VERSION)
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ZIPFILES = \
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README \
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Makefile \
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DE1_TOP.qsf \
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DE2_TOP.qsf \
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apple2fpga_DE1.qpf \
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apple2fpga_DE2.qpf \
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apple2.vhd \
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character_rom.vhd \
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CLK28MPLL.vhd \
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CLK28MPLL.qip \
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cpu6502.vhd \
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DE1_TOP.vhd \
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DE2_TOP.vhd \
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disk_ii.vhd \
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i2c_controller.vhd \
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keyboard.vhd \
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PS2_Ctrl.vhd \
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spi_controller.vhd \
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timing_generator.vhd \
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vga_controller.vhd \
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video_generator.vhd \
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wm8731_audio.vhd \
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disk_ii_rom.vhd \
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main_roms.vhd \
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i2c_testbench.vhd \
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timing_testbench.vhd \
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dos33master.nib \
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dsk2nib.c \
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dsk2nib.sln \
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dsk2nib.vcproj \
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rom2vhdl \
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makenibs \
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bios.a65 \
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bios.rom \
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DE1_TOP.sof \
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DE2_TOP.sof \
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apple_II.rom \
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slot6.rom
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##############################
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# Create the .zip file archive
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$(NAME).zip : $(ZIPFILES)
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zip $(NAME).zip $(ZIPFILES)
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##############################
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# Create the two VHDL files for the actual ROMS
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# apple_II.rom should be a 12287-byte file that represents the contents
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# of the Apple II's ROMS, i.e., memory from 0xd000 to 0xffff
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main_roms.vhd : apple_II.rom
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./rom2vhdl main_roms 13 12287 < apple_II.rom > main_roms.vhd
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# slot6.rom should be a 256-byte file that represents the contents of the
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# Disk II controller card. When in slot 6, it appears in memory from
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# 0xc600 to 0xc6FF
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disk_ii_rom.vhd : slot6.rom
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./rom2vhdl disk_ii_rom 7 255 < slot6.rom > disk_ii_rom.vhd
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##############################
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# Assemble the "fake BIOS" using the xa65 cross-assembler
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bios.rom : bios.a65
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xa -bt 53248 -A 53248 -o bios.rom -l bios.labels bios.a65
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# Disassemble the "fake BIOS" to
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bios.dis : bios.rom
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dxa -g d000 -a dump -r d000 bios.rom > bios.dis
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##############################
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# Rules for running the various testbenches using ghdl, the GNU VHDL simulator
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VHDL_SRC = timing_generator.vhd \
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timing_testbench.vhd \
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i2c_controller.vhd \
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i2c_testbench.vhd
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TIMING = 10000000ns
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timing_testbench : $(VHDL_SRC:%.vhd=%.o)
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ghdl -e timing_testbench
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timing_testbench.o : timing_generator.o
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# Run the timing testbench to generate a .vcd file, which can be viewed with
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#
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# gtkwave timing_testbench.vcd timing_testbench.sav
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#
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timing_testbench.vcd : timing_testbench Makefile
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-./timing_testbench --vcd=timing_testbench.vcd --stop-time=$(TIMING) 2> timing_testbench.log
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i2c_testbench : $(VHDL_SRC:%.vhd=%.o)
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ghdl -e i2c_testbench
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i2c_testbench.o : i2c_controller.o
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# Run the i2c testbench to generate a .vcd file, which can be viewed with
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#
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# gtkwave i2c_testbench.vcd i2c_testbench.sav
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#
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i2c_testbench.vcd : i2c_testbench Makefile
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./i2c_testbench --vcd=i2c_testbench.vcd --stop-time=$(TIMING) 2> i2c_testbench.log
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%.o : %.vhd
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ghdl -a $<
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