mirror of https://github.com/zxdos/zxuno.git
160 lines
4.0 KiB
Verilog
160 lines
4.0 KiB
Verilog
`timescale 1ns / 1ns
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02:28:18 02/06/2014
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// Design Name:
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// Module Name: test1
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tld_zxuno (
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input wire clk50mhz,
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output wire [2:0] r,
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output wire [2:0] g,
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output wire [2:0] b,
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output wire csync,
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input wire ear,
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inout wire clkps2,
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inout wire dataps2,
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inout wire mouseclk,
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inout wire mousedata,
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output wire audio_out_left,
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output wire audio_out_right,
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output wire stdn,
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output wire stdnb,
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output wire [18:0] sram_addr,
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inout wire [7:0] sram_data,
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output wire sram_we_n,
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output wire flash_cs_n,
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output wire flash_clk,
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output wire flash_mosi,
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input wire flash_miso,
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output wire sd_cs_n,
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output wire sd_clk,
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output wire sd_mosi,
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input wire sd_miso,
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output wire testled, // nos servirá como testigo de uso de la SPI
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input wire joyup,
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input wire joydown,
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input wire joyleft,
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input wire joyright,
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input wire joyfire
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);
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wire wssclk,sysclk,clk14,clk7,clk3d5;
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// relojes los_relojes_del_sistema (
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// .CLKIN_IN(clk50mhz),
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// .CLKDV_OUT(wssclk), // 5MHz
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// .CLKFX_OUT(sysclk), // 28MHz
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// .CLKIN_IBUFG_OUT(),
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// .CLK0_OUT(),
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// .LOCKED_OUT()
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// );
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assign wssclk = 1'b0; // de momento, sin WSS
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assign stdn = 1'b0; // fijar norma PAL
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assign stdnb = 1'b1; // y conectamos reloj PAL
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// pll reloj_maestro
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// (// Clock in ports
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// .CLK_IN1 (clk50mhz), // IN
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// // Clock out ports
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// .CLK_OUT1 (sysclk), // OUT
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// // Dynamic reconfiguration ports
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// .PROGCLK (1'b0), // IN
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// .PROGDATA (1'b0), // IN
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// .PROGEN (1'b0), // IN
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// .PROGDONE ()); // OUT
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//
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// reg [2:0] divclk = 3'b000;
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// always @(posedge sysclk)
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// divclk <= divclk + 1;
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// assign clk14 = divclk[0];
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// assign clk7 = divclk[1];
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// assign clk3d5 = divclk[2];
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cuatro_relojes relojes_maestros
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(// Clock in ports
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.CLK_IN1 (clk50mhz), // IN
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// Clock out ports
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.CLK_OUT1 (sysclk) , // OUT
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.CLK_OUT2 (clk14), // OUT
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.CLK_OUT3 (clk7), // OUT
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.CLK_OUT4 (clk3d5)); // OUT
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wire audio_out;
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assign audio_out_left = audio_out;
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assign audio_out_right = audio_out;
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zxuno la_maquina (
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.clk(sysclk), // 28MHz, reloj base para la memoria de doble puerto, y de ahí, para el resto del circuito
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.wssclk(wssclk), // 5MHz, reloj para el WSS
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.clk14(clk14),
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.clk7(clk7),
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.clk3d5(clk3d5),
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.power_on_reset_n(1'b1), // sólo para simulación. Para implementacion, dejar a 1
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.r(r),
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.g(g),
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.b(b),
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.csync(csync),
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.clkps2(clkps2),
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.dataps2(dataps2),
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.ear(~ear), // negada porque el hardware tiene un transistor inversor
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.audio_out(audio_out),
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.sram_addr(sram_addr),
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.sram_data(sram_data),
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.sram_we_n(sram_we_n),
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.flash_cs_n(flash_cs_n),
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.flash_clk(flash_clk),
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.flash_di(flash_mosi),
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.flash_do(flash_miso),
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.sd_cs_n(sd_cs_n),
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.sd_clk(sd_clk),
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.sd_mosi(sd_mosi),
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.sd_miso(sd_miso),
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.joyup(joyup),
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.joydown(joydown),
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.joyleft(joyleft),
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.joyright(joyright),
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.joyfire(joyfire),
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.mouseclk(mouseclk),
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.mousedata(mousedata)
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);
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assign testled = (!flash_cs_n || !sd_cs_n);
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// reg [21:0] monoestable = 22'hFFFFFF;
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// always @(posedge sysclk) begin
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// if (!flash_cs_n || !sd_cs_n)
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// monoestable <= 0;
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// else if (monoestable[21] == 1'b0)
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// monoestable <= monoestable + 1;
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// end
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// assign testled = ~monoestable[21];
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endmodule
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