mirror of https://github.com/zxdos/zxuno.git
147 lines
3.2 KiB
Verilog
147 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01:35:26 02/07/2014
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// Design Name:
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// Module Name: dp_memory
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module dp_memory (
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input wire clk, // 28MHz
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input wire [18:0] a1,
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input wire [18:0] a2,
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input wire oe1_n,
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input wire oe2_n,
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input wire we1_n,
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input wire we2_n,
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input wire [7:0] din1,
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input wire [7:0] din2,
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output wire [7:0] dout1,
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output wire [7:0] dout2,
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output reg [18:0] a,
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inout wire [7:0] d,
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output reg ce_n,
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output reg oe_n,
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output reg we_n
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);
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parameter
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ACCESO_M1 = 1,
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READ_M1 = 2,
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WRITE_M1 = 3,
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ACCESO_M2 = 4,
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READ_M2 = 5,
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WRITE_M2 = 6;
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reg [7:0] data_to_write;
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reg enable_input_to_sram;
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reg [7:0] doutput1;
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reg [7:0] doutput2;
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reg write_in_dout1;
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reg write_in_dout2;
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reg [2:0] state = ACCESO_M1;
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reg [2:0] next_state;
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always @(posedge clk) begin
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state <= next_state;
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end
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always @* begin
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a = 0;
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oe_n = 0;
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we_n = 1;
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ce_n = 0;
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enable_input_to_sram = 0;
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next_state = ACCESO_M1;
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data_to_write = 8'h00;
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write_in_dout1 = 0;
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write_in_dout2 = 0;
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case (state)
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ACCESO_M1: begin
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a = a1;
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if (we1_n == 1) begin
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next_state = READ_M1;
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end
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else begin
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oe_n = 1;
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next_state = WRITE_M1;
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end
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end
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READ_M1: begin
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if (we1_n == 1) begin
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a = a1;
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write_in_dout1 = 1;
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end
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next_state = ACCESO_M2;
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end
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WRITE_M1: begin
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if (we1_n == 0) begin
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a = a1;
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enable_input_to_sram = 1;
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data_to_write = din1;
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oe_n = 1;
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we_n = 0;
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end
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next_state = ACCESO_M2;
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end
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ACCESO_M2: begin
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a = a2;
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if (we2_n == 1) begin
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next_state = READ_M2;
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end
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else begin
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oe_n = 1;
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next_state = WRITE_M2;
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end
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end
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READ_M2: begin
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if (we2_n == 1) begin
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a = a2;
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write_in_dout2 = 1;
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end
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next_state = ACCESO_M1;
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end
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WRITE_M2: begin
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if (we2_n == 0) begin
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a = a2;
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enable_input_to_sram = 1;
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data_to_write = din2;
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oe_n = 1;
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we_n = 0;
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end
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next_state = ACCESO_M1;
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end
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endcase
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end
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assign d = (enable_input_to_sram)? data_to_write : 8'hZZ;
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assign dout1 = (oe1_n)? 8'hZZ : doutput1;
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assign dout2 = (oe2_n)? 8'hZZ : doutput2;
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always @(posedge clk) begin
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if (write_in_dout1)
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doutput1 <= d;
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else if (write_in_dout2)
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doutput2 <= d;
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end
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endmodule
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