mirror of https://github.com/zxdos/zxuno.git
44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01:22:53 06/15/2015
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// Design Name:
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// Module Name: scratch_register
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module scratch_register(
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input wire clk,
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input wire poweron_rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output wire oe_n
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);
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parameter SCRATCH = 8'hFE;
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assign oe_n = ~(zxuno_addr == SCRATCH && zxuno_regrd == 1'b1);
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reg [7:0] scratch = 8'h00; // initial value
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always @(posedge clk) begin
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if (poweron_rst_n == 1'b0)
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scratch <= 8'h00; // or after a hardware reset (not implemented yet)
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else if (zxuno_addr == SCRATCH && zxuno_regwr == 1'b1)
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scratch <= din;
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dout <= scratch;
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end
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endmodule
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