mirror of https://github.com/zxdos/zxuno.git
102 lines
1.8 KiB
Verilog
102 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01:40:55 03/05/2014
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// Design Name: spi
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// Module Name: C:/Users/rodriguj/Documents/zxspectrum/zxuno/repositorio/cores/test11/tb_spi.v
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// Project Name: zxuno
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: spi
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tb_spi;
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// Inputs
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reg clk;
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reg enviar_dato;
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reg recibir_dato;
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reg [7:0] din;
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reg spi_do;
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// Outputs
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wire [7:0] dout;
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wire oe_n;
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wire spi_clk;
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wire spi_di;
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// Instantiate the Unit Under Test (UUT)
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spi uut (
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.clk(clk),
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.enviar_dato(enviar_dato),
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.recibir_dato(recibir_dato),
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.din(din),
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.dout(dout),
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.oe_n(oe_n),
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.spi_clk(spi_clk),
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.spi_di(spi_di),
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.spi_do(spi_do)
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);
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initial begin
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// Initialize Inputs
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clk = 0;
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enviar_dato = 0;
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recibir_dato = 0;
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din = 0;
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spi_do = 0;
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// Wait 100 ns for global reset to finish
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#300;
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din = 8'b11001011;
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enviar_dato = 1;
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#700;
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enviar_dato = 0;
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#2000;
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recibir_dato = 1;
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spi_do = 1;
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@(negedge spi_clk);
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spi_do = 0;
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@(negedge spi_clk);
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spi_do = 1;
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@(negedge spi_clk);
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spi_do = 1;
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@(negedge spi_clk);
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spi_do = 0;
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@(negedge spi_clk);
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spi_do = 0;
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@(negedge spi_clk);
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spi_do = 1;
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@(negedge spi_clk);
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spi_do = 1;
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@(negedge spi_clk);
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#200;
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recibir_dato = 0;
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#100;
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$finish;
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end
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always begin
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clk = #71.428571428571428571428571428571 ~clk;
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end
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endmodule
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