mirror of https://github.com/zxdos/zxuno.git
153 lines
4.2 KiB
VHDL
153 lines
4.2 KiB
VHDL
------------------------------------------------------------------------------
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-- Input Clock Input Freq (MHz) Input Jitter (UI)
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------------------------------------------------------------------------------
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-- primary 50.000 0.010
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-- Generador relojes PLL para el in de 50Mhz del ZX-UNO
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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entity clock is
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port
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(-- Clock in ports
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clk_in : in std_logic;
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sel_pclock : in std_logic;
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sel_cpu : in std_logic;
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-- Clock out ports
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clk8 : out std_logic;
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clk16 : out std_logic;
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clk_cpu : out std_logic;
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-- clk32 : out std_logic;
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pclock : out std_logic;
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cpu_pclock : out std_logic
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);
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end clock;
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architecture behavioral of clock is
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-- Input clock buffering / unused connectors
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signal clkin1 : std_logic;
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-- Output clock buffering / unused connectors
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signal clkfbout : std_logic;
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signal clkfbout_buf : std_logic;
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signal clkout0 : std_logic;
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signal clkout1 : std_logic;
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signal clkout2 : std_logic;
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signal clkout3 : std_logic;
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signal clkout4_unused : std_logic;
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signal clkout5_unused : std_logic;
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-- Unused status signals
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signal locked_unused : std_logic;
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signal clk357 : std_logic;
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begin
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-- Input buffering
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--------------------------------------
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clkin1_buf : IBUFG
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port map
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(O => clkin1,
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I => clk_in);
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-- Clocking primitive
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--------------------------------------
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-- Instantiation of the PLL primitive
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-- * Unused inputs are tied off
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-- * Unused outputs are labeled unused
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pll_base_inst : PLL_BASE
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generic map
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(BANDWIDTH => "OPTIMIZED",
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CLK_FEEDBACK => "CLKFBOUT",
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COMPENSATION => "SYSTEM_SYNCHRONOUS",
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DIVCLK_DIVIDE => 1,
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CLKFBOUT_MULT => 16,
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CLKFBOUT_PHASE => 0.000,
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CLKOUT0_DIVIDE => 100, --25 = 32Mhz, --100 = 8Mhz --1120 = 7,12Mhz (/2 = 3,57)
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CLKOUT0_PHASE => 0.000,
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CLKOUT0_DUTY_CYCLE => 0.500,
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CLKOUT1_DIVIDE => 50, --50 = 16MHz
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CLKOUT1_PHASE => 0.000,
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CLKOUT1_DUTY_CYCLE => 0.500,
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CLKOUT2_DIVIDE => 25, --27 ~29.5Mhz Z80 --100 = 8mhz --50 = 16mhz --32 = 25Mhz
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CLKOUT2_PHASE => 0.000,
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CLKOUT2_DUTY_CYCLE => 0.500,
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-- CLKOUT3_DIVIDE => 112, --25 = 32Mhz for HDMI clock
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-- CLKOUT3_PHASE => 0.000,
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-- CLKOUT3_DUTY_CYCLE => 0.500,
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CLKIN_PERIOD => 20.0,
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REF_JITTER => 0.010)
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port map
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-- Output clocks
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(CLKFBOUT => clkfbout,
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CLKOUT0 => clkout0,
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CLKOUT1 => clkout1,
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CLKOUT2 => clkout2,
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CLKOUT3 => clkout3,
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CLKOUT4 => clkout4_unused,
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CLKOUT5 => clkout5_unused,
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LOCKED => locked_unused,
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RST => '0',
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-- Input clock control
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CLKFBIN => clkfbout_buf,
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CLKIN => clkin1);
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-- Output buffering
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-------------------------------------
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clkf_buf : BUFG
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port map
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(O => clkfbout_buf,
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I => clkfbout);
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clkout1_buf : BUFG
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port map
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(O => clk8,
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I => clkout0);
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clkout2_buf : BUFG
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port map
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(O => clk16,
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I => clkout1);
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clkout3_buf : BUFG
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port map
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(O => clk_cpu,
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I => clkout2);
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-- clkout4_buf : BUFG
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-- port map
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-- (O => clk32,
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-- I => clkout3);
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pclock_sel : BUFGMUX --muxer del relojes 16 / 8 para el pixel clock del scandoubler on/off
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port map
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(O => pclock,
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I0 => clkout0, --el de 8
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I1 => clkout1, --el de 16
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S => sel_pclock);
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pclock_sel_cpu : BUFGMUX --muxer del relojes 32 / 8 para el cambio de cpu (32 = loader/SD)
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port map
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(O => cpu_pclock,
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I0 => clkout1,
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I1 => clkout2, --el de 32
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S => sel_cpu);
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-- process (clkout3)
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-- begin
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-- if rising_edge(clkout3) then
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-- clk357 <= not clk357;
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-- end if;
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-- end process;
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end behavioral;
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