mirror of https://github.com/zxdos/zxuno.git
171 lines
5.5 KiB
Verilog
171 lines
5.5 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 18:02:15 03/12/2015
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// Design Name:
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// Module Name: pal_generator
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module pal_sync_generator (
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input wire clk,
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input wire [1:0] mode, // 00: 48K, 01: 128K, 10: Pentagon, 11: Reserved
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input wire rasterint_enable,
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input wire vretraceint_disable,
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input wire [8:0] raster_line,
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output wire raster_int_in_progress,
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input wire [2:0] ri,
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input wire [2:0] gi,
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input wire [2:0] bi,
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output wire [8:0] hcnt,
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output wire [8:0] vcnt,
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output reg [2:0] ro,
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output reg [2:0] go,
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output reg [2:0] bo,
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output reg hsync,
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output reg vsync,
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output wire int_n
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);
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reg [8:0] hc = 9'h000;
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reg [8:0] vc = 9'h000;
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reg [8:0] end_count_h = 9'd447;
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reg [8:0] end_count_v = 9'd311;
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reg [8:0] begin_hblank = 9'd320;
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reg [8:0] end_hblank = 9'd415;
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reg [8:0] begin_hsync = 9'd344;
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reg [8:0] end_hsync = 9'd375;
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reg [8:0] begin_vblank = 9'd248;
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reg [8:0] end_vblank = 9'd255;
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reg [8:0] begin_vsync = 9'd248;
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reg [8:0] end_vsync = 9'd251;
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reg [8:0] begin_vcint = 9'd248;
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reg [8:0] end_vcint = 9'd248;
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reg [8:0] begin_hcint = 9'd2;
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reg [8:0] end_hcint = 9'd65;
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reg [1:0] old_mode = 2'b11;
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assign hcnt = hc;
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assign vcnt = vc;
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always @(posedge clk) begin
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if (hc == end_count_h) begin
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hc <= 0;
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if (vc == end_count_v) begin
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vc <= 0;
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if (mode != old_mode) begin
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old_mode <= mode;
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case (mode)
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2'b00: begin // timings for Sinclair 48K
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end_count_h <= 9'd447;
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end_count_v <= 9'd311;
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begin_hblank <= 9'd320;
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end_hblank <= 9'd415;
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begin_hsync <= 9'd344;
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end_hsync <= 9'd375;
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begin_vblank <= 9'd248;
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end_vblank <= 9'd255;
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begin_vsync <= 9'd248;
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end_vsync <= 9'd251;
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begin_vcint <= 9'd248;
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end_vcint <= 9'd248;
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begin_hcint <= 9'd2;
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end_hcint <= 9'd65;
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end
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2'b01: begin // timings for Sinclair 128K/+2 grey
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end_count_h <= 9'd455;
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end_count_v <= 9'd310;
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begin_hblank <= 9'd320;
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end_hblank <= 9'd415;
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begin_hsync <= 9'd344;
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end_hsync <= 9'd375;
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begin_vblank <= 9'd248;
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end_vblank <= 9'd255;
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begin_vsync <= 9'd248;
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end_vsync <= 9'd251;
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begin_vcint <= 9'd248;
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end_vcint <= 9'd248;
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begin_hcint <= 9'd2;
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end_hcint <= 9'd65;
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end
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2'b10,
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2'b11: begin // timings for Pentagon 128
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end_count_h <= 9'd447;
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end_count_v <= 9'd319;
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begin_hblank <= 9'd336; // 9'd328;
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end_hblank <= 9'd399; // 9'd391;
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begin_hsync <= 9'd336; // 9'd328;
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end_hsync <= 9'd367; // 9'd359;
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begin_vblank <= 9'd240;
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end_vblank <= 9'd271; // 9'd255;
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begin_vsync <= 9'd240;
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end_vsync <= 9'd255; // 9'd243;
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begin_vcint <= 9'd239;
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end_vcint <= 9'd239;
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begin_hcint <= 9'd320; // 9'd318;
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end_hcint <= 9'd391; //9'd389;
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end
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endcase
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end
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end
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else
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vc <= vc + 1;
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end
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else
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hc <= hc + 1;
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end
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// INT generation
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reg vretrace_int_n, raster_int_n;
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assign int_n = vretrace_int_n & raster_int_n;
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assign raster_int_in_progress = ~raster_int_n;
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always @* begin
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vretrace_int_n = 1'b1;
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if (vretraceint_disable == 1'b0 && (hc >= begin_hcint && vc == begin_vcint) && (hc <= end_hcint && vc == end_vcint))
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vretrace_int_n = 1'b0;
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raster_int_n = 1'b1;
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if (rasterint_enable == 1'b1 && hc >= 256 && hc <= 319) begin
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if (raster_line == 9'd0 && vc == end_count_v)
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raster_int_n = 1'b0;
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if (raster_line != 9'd0 && vc == (raster_line - 9'd1))
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raster_int_n = 1'b0;
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end
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end
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always @* begin
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ro = ri;
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go = gi;
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bo = bi;
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hsync = 1'b1;
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vsync = 1'b1;
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if ( (hc >= begin_hblank && hc <= end_hblank) || (vc >= begin_vblank && vc <= end_vblank) ) begin
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ro = 3'b000;
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go = 3'b000;
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bo = 3'b000;
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if (hc >= begin_hsync && hc <= end_hsync)
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hsync = 1'b0;
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if (vc >= begin_vsync && vc <= end_vsync)
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vsync = 1'b0;
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end
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end
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endmodule
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