mirror of https://github.com/zxdos/zxuno.git
79 lines
2.2 KiB
Verilog
79 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:24:57 12/06/2015
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// Design Name:
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// Module Name: control_rasterint
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rasterint_ctrl (
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output reg oe_n,
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output wire rasterint_enable,
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output wire vretraceint_disable,
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output wire [8:0] raster_line,
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input wire raster_int_in_progress
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);
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parameter RASTERLINE = 8'h0C;
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parameter RASTERCTRL = 8'h0D;
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reg [7:0] rasterline_reg = 8'hFF;
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reg raster_enable = 1'b0;
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reg vretrace_disable = 1'b0;
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reg raster_8th_bit = 1'b1;
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assign raster_line = {raster_8th_bit, rasterline_reg};
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assign rasterint_enable = raster_enable;
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assign vretraceint_disable = vretrace_disable;
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always @(posedge clk) begin
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if (rst_n == 1'b0) begin
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raster_enable <= 1'b0;
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vretrace_disable <= 1'b0;
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raster_8th_bit <= 1'b1;
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rasterline_reg <= 8'hFF;
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end
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else begin
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if (zxuno_addr == RASTERLINE && zxuno_regwr == 1'b1)
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rasterline_reg <= din;
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if (zxuno_addr == RASTERCTRL && zxuno_regwr == 1'b1)
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{vretrace_disable, raster_enable, raster_8th_bit} <= din[2:0];
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end
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end
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always @* begin
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dout = 8'hFF;
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oe_n = 1'b1;
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if (zxuno_addr == RASTERLINE && zxuno_regrd == 1'b1) begin
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dout = rasterline_reg;
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oe_n = 1'b0;
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end
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if (zxuno_addr == RASTERCTRL && zxuno_regrd == 1'b1) begin
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dout = {raster_int_in_progress, 4'b0000, vretrace_disable, raster_enable, raster_8th_bit};
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oe_n = 1'b0;
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end
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end
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endmodule
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