mirror of https://github.com/zxdos/zxuno.git
66 lines
1.6 KiB
VHDL
66 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.vcomponents.all;
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entity clock is
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port
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(
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clock50 : in std_logic;
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clock14 : out std_logic; -- 14.000 MHz
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clock700 : out std_logic; -- 7.000 MHz
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clock350 : out std_logic; -- 3.500 Mhz
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clock175 : out std_logic -- 1.750 Mhz
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);
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end;
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architecture behavioral of clock is
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signal cfb : std_logic;
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signal c50 : std_logic;
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signal c14 : std_logic;
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signal count : std_logic_vector(2 downto 0);
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begin
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Uibufg : ibufg port map(i => clock50, o => c50);
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Uclock14 : bufg port map(i => c14, o => clock14);
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Uclock700 : bufg port map(i => count(0), o => clock700);
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Uclock350 : bufg port map(i => count(1), o => clock350);
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clock175 <= count(2);
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-- Uclock175 : bufg port map(i => count(2), o => clock175);
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uclock : pll_base
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generic map
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(
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bandwidth => "optimized",
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clk_feedback => "clkfbout",
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compensation => "internal",
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clkin_period => 20.000,
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ref_jitter => 0.010,
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divclk_divide => 1,
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clkfbout_mult => 14,
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clkfbout_phase => 0.000,
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clkout0_divide => 50,
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clkout0_phase => 0.000,
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clkout0_duty_cycle => 0.500
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)
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port map
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(
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rst => '0',
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clkfbin => cfb,
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clkfbout => cfb,
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clkin => c50,
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clkout0 => c14,
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clkout1 => open,
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clkout2 => open,
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clkout3 => open,
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clkout4 => open,
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clkout5 => open,
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locked => open
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);
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count <= count+1 when falling_edge(c14);
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end;
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