mirror of https://github.com/zxdos/zxuno.git
35 lines
1.0 KiB
Verilog
35 lines
1.0 KiB
Verilog
`define MSBI 9 // Most significant Bit of DAC input
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// this is a delta-sigma digital to analog converter
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module dac (o, i, clock, reset);
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output o; // this is the average output that feeds low pass filter
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input [`MSBI:0] i; // dac input (excess 2**msbi)
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input clock;
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input reset;
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reg o; // for optimum performance, ensure that this ff is in IOB
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reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
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reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
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reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
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reg [`MSBI+2:0] DeltaB; // B input of Delta adder
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always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
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always @(i or DeltaB) DeltaAdder = i + DeltaB;
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always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
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always @(posedge clock or posedge reset)
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begin
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if(reset)
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begin
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SigmaLatch <= #1 1'b1 << (`MSBI+1);
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o <= #1 1'b0;
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end
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else
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begin
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SigmaLatch <= #1 SigmaAdder;
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o <= #1 SigmaLatch[`MSBI+2];
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end
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end
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endmodule
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