mirror of https://github.com/zxdos/zxuno.git
68 lines
1.4 KiB
VHDL
68 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity div is
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port
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(
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clock : in std_logic;
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reset : in std_logic;
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mreq : in std_logic;
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iorq : in std_logic;
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m1 : in std_logic;
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rd : in std_logic;
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wr : in std_logic;
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di : in std_logic_vector( 7 downto 0);
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a : in std_logic_vector(15 downto 0);
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--
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automap : out std_logic;
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conmem : out std_logic;
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mapram : out std_logic;
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page : out std_logic_vector( 3 downto 0)
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);
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end;
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architecture behavioral of div is
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signal m1on : std_logic := '0';
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begin
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process(clock)
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begin
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if rising_edge(clock)
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then
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if reset = '0'
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then
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m1on <= '0';
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automap <= '0';
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conmem <= '0';
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mapram <= '0';
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page <= (others => '0');
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else
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if iorq = '0' and wr = '0' and a(7 downto 0) = x"E3"
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then
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conmem <= di(7);
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mapram <= di(6);-- or mapram;
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page <= di(3 downto 0);
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end if;
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if mreq = '0' and m1 = '0'
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then
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if a = x"0000" or a = x"0008" or a = x"0038" or a = x"0066" or a = x"04C6" or a = x"0562"
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then
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m1on <= '1'; -- activate automapper after this cycle
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elsif a(15 downto 3) = x"1ff"&'1'
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then
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m1on <= '0'; -- deactivate automapper after this cycle
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elsif a(15 downto 8) = x"3D"
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then
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automap <= '1';
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m1on <= '1'; -- activate automapper immediately
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end if;
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end if;
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if m1 = '1' then automap <= m1on; end if;
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end if;
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end if;
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end process;
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end;
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