mirror of https://github.com/zxdos/zxuno.git
28 lines
549 B
VHDL
28 lines
549 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity ram is
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port
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(
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wr : in std_logic;
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di : in std_logic_vector( 7 downto 0);
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do : out std_logic_vector( 7 downto 0);
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a : in std_logic_vector(18 downto 0);
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--
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sramWr : out std_logic;
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sramData : inout std_logic_vector( 7 downto 0);
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sramAddr : out std_logic_vector(18 downto 0)
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);
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end;
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architecture structural of ram is
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begin
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sramWr <= wr;
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sramData <= di when wr = '0' else (others => 'Z');
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sramAddr <= a;
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do <= sramData;
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end;
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