mirror of https://github.com/zxdos/zxuno.git
78 lines
1.6 KiB
VHDL
78 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity spi is
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Port (
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clk : in STD_LOGIC;
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RD_n : in STD_LOGIC;
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WR_n : in STD_LOGIC;
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A : in STD_LOGIC_VECTOR (7 downto 0);
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D_in : in STD_LOGIC_VECTOR (7 downto 0);
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D_out : out STD_LOGIC_VECTOR (7 downto 0);
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cs_n : buffer STD_LOGIC;
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sclk : out STD_LOGIC;
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miso : in STD_LOGIC;
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mosi : out STD_LOGIC);
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end spi;
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architecture Behavioral of spi is
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signal ready : std_logic := '1';
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signal clk_div : unsigned(6 downto 0) := "0000000";
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signal clk_cnt : unsigned(6 downto 0) := "0000000";
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signal bit_cnt : unsigned(3 downto 0) := "0000";
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signal shift : std_logic_vector(7 downto 0);
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signal in_sclk : std_logic := '1';
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begin
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ready <= '1' when bit_cnt=0 else '0';
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process (clk,A,WR_n,RD_n,D_in,miso)
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begin
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if rising_edge(clk) then
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if ready='0' then
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case clk_cnt is
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when "0000000" =>
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if in_sclk='1' then
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mosi <= shift(7);
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elsif in_sclk='0' then
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shift <= shift(6 downto 0)&miso;
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bit_cnt <= bit_cnt-1;
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end if;
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clk_cnt <= clk_div;
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in_sclk <= not in_sclk;
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when others =>
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clk_cnt <= clk_cnt-1;
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end case;
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elsif WR_n='0' then
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if A(0)='0' then
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cs_n <= D_in(7);
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clk_div <= unsigned(D_in(6 downto 0));
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elsif ready='1' then
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shift <= D_in;
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bit_cnt <= "1000";
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clk_cnt <= "0000001";
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end if;
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end if;
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end if;
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end process;
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process (clk,A,WR_n,RD_n,D_in,miso)
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begin
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if rising_edge(clk) and RD_n='0' then
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if A(0)='0' then
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D_out <= ready&std_logic_vector(clk_div);
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else
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D_out <= shift;
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end if;
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end if;
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end process;
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sclk <= in_sclk;
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end Behavioral;
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