mirror of https://github.com/zxdos/zxuno.git
98 lines
2.6 KiB
Verilog
98 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:04:00 04/01/2012
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// Design Name:
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// Module Name: sigma_delta_dac
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`define MSBI 7 // Most significant Bit of DAC input
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//This is a Delta-Sigma Digital to Analog Converter
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module dac (DACout, DACin, Clk, Reset);
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output DACout; // This is the average output that feeds low pass filter
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input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
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input Clk;
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input Reset;
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reg DACout; // for optimum performance, ensure that this ff is in IOB
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reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
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reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
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reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
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reg [`MSBI+2:0] DeltaB; // B input of Delta adder
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always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
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always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
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always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
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always @(posedge Clk)
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begin
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if(Reset)
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begin
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SigmaLatch <= #1 1'b1 << (`MSBI+1);
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DACout <= #1 1'b0;
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end
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else
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begin
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SigmaLatch <= #1 SigmaAdder;
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DACout <= #1 SigmaLatch[`MSBI+2];
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end
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end
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endmodule
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module mixer (
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input wire clkdac,
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input wire reset,
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input wire ear,
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input wire mic,
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input wire spk,
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input wire [7:0] ay1,
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input wire [7:0] ay2,
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output wire audio
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);
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parameter
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SRC_BEEPER = 2'd0,
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SRC_AY1 = 2'd1,
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SRC_AY2 = 2'd2;
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wire [7:0] beeper = ({ear,spk,mic}==3'b000)? 8'd17 :
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({ear,spk,mic}==3'b001)? 8'd36 :
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({ear,spk,mic}==3'b010)? 8'd184 :
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({ear,spk,mic}==3'b011)? 8'd192 :
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({ear,spk,mic}==3'b100)? 8'd22 :
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({ear,spk,mic}==3'b101)? 8'd48 :
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({ear,spk,mic}==3'b110)? 8'd244 : 8'd255;
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reg [7:0] mezcla;
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reg [1:0] sndsource = 2'd0;
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always @(posedge clkdac) begin
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case (sndsource)
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SRC_BEEPER: mezcla <= beeper;
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SRC_AY1 : mezcla <= ay1;
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SRC_AY2 : mezcla <= ay2;
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endcase
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sndsource <= (sndsource == 2'd2)? 2'd0 : sndsource + 2'd1; // en lugar de sumar, multiplexamos en el tiempo las fuentes de sonido
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end
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dac audio_dac (
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.DACout(audio),
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.DACin(mezcla),
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.Clk(clkdac),
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.Reset(reset)
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);
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endmodule
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