mirror of https://github.com/zxdos/zxuno.git
71 lines
1.6 KiB
Verilog
71 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 18:22:21 06/07/2015
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// Design Name:
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// Module Name: coreid
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module coreid (
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input wire clk,
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input wire rst_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire regaddr_changed,
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output reg [7:0] dout,
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output wire oe_n
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);
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reg [7:0] text[0:15];
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integer i;
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initial begin
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for (i=0;i<16;i=i+1)
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text[i] = 8'h00;
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text[ 0] = "T";
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text[ 1] = "2";
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text[ 2] = "4";
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text[ 3] = "-";
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text[ 4] = "0";
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text[ 5] = "7";
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text[ 6] = "1";
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text[ 7] = "1";
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text[ 8] = "2";
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text[ 9] = "0";
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text[10] = "1";
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text[11] = "6";
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end
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reg [3:0] textindx = 4'h0;
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reg reading = 1'b0;
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assign oe_n = !(zxuno_addr == 8'hFF && zxuno_regrd==1'b1);
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always @(posedge clk) begin
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if (rst_n == 1'b0 || (regaddr_changed==1'b1 && zxuno_addr==8'hFF)) begin
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textindx <= 4'h0;
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reading <= 1'b0;
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end
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else if (oe_n==1'b0) begin
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reading <= 1'b1;
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end
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else if (reading == 1'b1 && oe_n==1'b1) begin
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reading <= 1'b0;
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textindx <= textindx + 1;
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end
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dout <= text[textindx];
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end
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endmodule
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