mirror of https://github.com/zxdos/zxuno.git
100 lines
2.1 KiB
Verilog
100 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11:33:13 04/27/2014
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// Design Name:
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// Module Name: turbosound
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module turbosound (
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input wire clk,
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input wire clkay,
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input wire reset_n,
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input wire disable_ay,
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input wire disable_turboay,
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input wire bdir,
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input wire bc1,
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input wire [7:0] din,
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output wire [7:0] dout,
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output wire oe_n,
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output wire [7:0] audio_out_ay1,
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output wire [7:0] audio_out_ay2
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);
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reg ay_select = 1'b1;
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always @(posedge clk) begin
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if (reset_n==1'b0)
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ay_select <= 1'b1;
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else if (disable_ay == 1'b0 && disable_turboay == 1'b0 && bdir && bc1 && din[7:1]==7'b1111111)
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ay_select <= din[0]; // 1: select first AY, 0: select second AY
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end
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wire oe_n_ay1, oe_n_ay2;
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wire [7:0] dout_ay1, dout_ay2;
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assign dout = (ay_select)? dout_ay1 : dout_ay2;
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assign oe_n = (ay_select && !disable_ay)? oe_n_ay1 :
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(!ay_select && !disable_ay && !disable_turboay)? oe_n_ay2 :
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1'b1;
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YM2149 ay1 (
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.I_DA(din),
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.O_DA(dout_ay1),
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.O_DA_OE_L(oe_n_ay1),
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.I_A9_L(1'b0),
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.I_A8(ay_select),
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.I_BDIR(bdir),
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.I_BC2(1'b1),
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.I_BC1(bc1),
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.I_SEL_L(1'b0),
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.O_AUDIO(audio_out_ay1),
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.I_IOA(8'h00),
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.O_IOA(),
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.O_IOA_OE_L(),
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.I_IOB(8'h00),
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.O_IOB(),
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.O_IOB_OE_L(),
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.ENA(~disable_ay),
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.RESET_L(reset_n),
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.CLK(clkay),
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.CLK28(clk)
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);
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YM2149 ay2 (
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.I_DA(din),
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.O_DA(dout_ay2),
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.O_DA_OE_L(oe_n_ay2),
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.I_A9_L(1'b0),
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.I_A8(~ay_select),
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.I_BDIR(bdir),
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.I_BC2(1'b1),
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.I_BC1(bc1),
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.I_SEL_L(1'b0),
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.O_AUDIO(audio_out_ay2),
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.I_IOA(8'h00),
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.O_IOA(),
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.O_IOA_OE_L(),
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.I_IOB(8'h00),
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.O_IOB(),
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.O_IOB_OE_L(),
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.ENA(~disable_ay & ~disable_turboay),
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.RESET_L(reset_n),
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.CLK(clkay),
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.CLK28(clk)
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);
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endmodule
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