mirror of https://github.com/zxdos/zxuno.git
36 lines
715 B
VHDL
36 lines
715 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity dac is
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Port (
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clk : in STD_LOGIC;
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input : in STD_LOGIC_VECTOR (5 downto 0);
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output: out STD_LOGIC);
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end dac;
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architecture rtl of dac is
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signal delta_adder: unsigned(7 downto 0);
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signal sigma_adder: unsigned(7 downto 0);
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signal sigma_latch: unsigned(7 downto 0) := "01000000";
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signal delta_b : unsigned(7 downto 0);
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begin
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delta_b <= sigma_latch(7)&sigma_latch(7)&"000000";
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delta_adder <= unsigned(input) + delta_b;
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sigma_adder <= delta_adder + sigma_latch;
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process (clk, delta_adder)
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begin
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if rising_edge(clk) then
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sigma_latch <= sigma_adder;
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output <= sigma_adder(7);
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end if;
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end process;
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end rtl;
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