mirror of https://github.com/zxdos/zxuno.git
59 lines
1.6 KiB
Verilog
59 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01:22:53 06/15/2015
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// Design Name:
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// Module Name: scratch_register
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module scandoubler_ctrl (
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input wire clk,
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input wire [15:0] a,
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input wire iorq_n,
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input wire wr_n,
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input wire [7:0] zxuno_addr,
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input wire zxuno_regrd,
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input wire zxuno_regwr,
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input wire [7:0] din,
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output reg [7:0] dout,
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output wire oe_n,
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output wire vga_enable,
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output wire scanlines_enable,
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output wire [2:0] freq_option,
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output wire [1:0] turbo_enable
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);
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parameter SCANDBLCTRL = 8'h0B;
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parameter PRISMSPEEDCTRL = 16'h8e3b; // PRISM speed control: bits D0-D3. We use TURBO=1 if D0-D3>0
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assign oe_n = ~(zxuno_addr == SCANDBLCTRL && zxuno_regrd == 1'b1);
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assign vga_enable = scandblctrl[0];
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assign scanlines_enable = scandblctrl[1];
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assign freq_option = scandblctrl[4:2];
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assign turbo_enable = scandblctrl[7:6];
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reg [7:0] scandblctrl = 8'h00; // initial value
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always @(posedge clk) begin
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if (zxuno_addr == SCANDBLCTRL && zxuno_regwr == 1'b1)
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scandblctrl <= din;
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else if (iorq_n == 1'b0 && wr_n == 1'b0 && a == PRISMSPEEDCTRL)
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scandblctrl[7:6] <= din[1:0];
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dout <= scandblctrl;
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end
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endmodule
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