mirror of https://github.com/zxdos/zxuno.git
603 lines
17 KiB
Verilog
603 lines
17 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:54:55 02/16/2014
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// Design Name:
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// Module Name: ula
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ula_radas (
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// Clocks
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input wire clk28,
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input wire clkregs, // clock to load registers
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input wire clk14, // 14MHz master clock
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input wire clk7,
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input wire cpuclk,
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output wire CPUContention,
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input wire rst_n, // reset para volver al modo normal
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// CPU interface
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input wire [15:0] a,
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input wire mreq_n,
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input wire iorq_n,
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input wire rd_n,
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input wire wr_n,
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output wire int_n,
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input wire [7:0] din,
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output reg [7:0] dout,
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input wire rasterint_enable,
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input wire vretraceint_disable,
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input wire [8:0] raster_line,
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output wire raster_int_in_progress,
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// VRAM interface
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output reg [13:0] va, // 16KB videoram
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input wire [7:0] vramdata,
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// I/O ports
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input wire ear,
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input wire [4:0] kbd,
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output reg mic,
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output reg spk,
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input wire issue2_keyboard,
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input wire [1:0] mode,
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input wire disable_contention,
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input wire access_to_contmem,
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output wire doc_ext_option,
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input wire enable_timexmmu,
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// Video
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output wire [2:0] r,
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output wire [2:0] g,
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output wire [2:0] b,
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output wire hsync,
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output wire vsync,
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output wire y_n
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);
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parameter
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BHPIXEL = 0,
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EHPIXEL = 255,
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BVPIXEL = 0,
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EVPIXEL = 191,
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BVSYNC = 248;
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// RGB inputs to sync module
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reg [2:0] ri;
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reg [2:0] gi;
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reg [2:0] bi;
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// Counters from sync module
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wire [8:0] hc;
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wire [8:0] vc;
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// Signal when the vertical counter is in the line that we use to make the INT signal
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wire in_int_line;
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reg clkhalf14 = 1'b0;
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always @(posedge clk14)
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clkhalf14 <= ~clkhalf14;
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pal_sync_generator syncs (
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.clk(clk7),
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.mode(mode),
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.rasterint_enable(rasterint_enable),
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.vretraceint_disable(vretraceint_disable),
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.raster_line(raster_line),
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.raster_int_in_progress(raster_int_in_progress),
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.ri(ri),
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.gi(gi),
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.bi(bi),
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.hcnt(hc),
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.vcnt(vc),
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.ro(r),
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.go(g),
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.bo(b),
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.hsync(hsync),
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.vsync(vsync),
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.int_n(int_n)
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);
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///////////////////////////////////////////////
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// ULA datapath
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///////////////////////////////////////////////
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// Control signals generated from the control unit
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// or the rest of modules
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reg BitmapDataLoad;
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reg AttrDataLoad;
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reg WriteToPortFE;
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reg SerializerLoad;
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reg TimexConfigLoad;
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reg AttrOutputLoad;
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reg PaletteRegLoad;
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reg ConfigRegLoad;
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reg PaletteLoad;
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reg BitmapAddr;
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reg AttrAddr;
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reg CALoad;
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reg VideoEnable;
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wire RadasEnabled; // =1 is el modo radastaniano est<73> habilitado
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// BitmapData register
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reg [7:0] BitmapData = 8'h00;
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always @(posedge clk7) begin
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if (BitmapDataLoad)
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BitmapData <= vramdata;
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end
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// AttrData register
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reg [7:0] AttrData = 8'h00;
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always @(posedge clk7) begin
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if (AttrDataLoad)
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AttrData <= vramdata;
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end
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// Border register
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reg [2:0] Border = 3'b010; // initial border colour is red
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always @(posedge clkregs) begin
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if (WriteToPortFE)
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Border <= din[2:0];
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end
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// BitmapSerializer register
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reg [7:0] BitmapSerializer = 8'h00;
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wire SerialOutput = BitmapSerializer[7];
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always @(posedge clk7) begin
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if (SerializerLoad)
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BitmapSerializer <= BitmapData;
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else
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BitmapSerializer <= {BitmapSerializer[6:0],1'b0};
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end
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// BitmapSerializerHR register
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reg [15:0] BitmapSerializerHR = 8'h00;
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wire SerialOutputHR = BitmapSerializerHR[15];
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always @(posedge clk14) begin
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if (SerializerLoad && clkhalf14) // load enable only for a single 14MHz cycle
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BitmapSerializerHR <= {BitmapData,AttrData};
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else
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BitmapSerializerHR <= {BitmapSerializerHR[14:0],1'b0};
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end
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// Timex config register
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reg [7:0] TimexConfigReg = 8'h00;
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wire PG = TimexConfigReg[0];
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wire HCL = TimexConfigReg[1];
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wire HR = TimexConfigReg[2];
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assign doc_ext_option = enable_timexmmu & TimexConfigReg[7];
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wire [2:0] HRInk = TimexConfigReg[5:3];
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always @(posedge clkregs) begin
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if (rst_n == 1'b0)
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TimexConfigReg <= 8'h00;
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else if (TimexConfigLoad)
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TimexConfigReg <= din;
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end
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// Combinational logic between AttrData and AttrOutput
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reg [7:0] InputToAttrOutput;
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always @* begin
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InputToAttrOutput = AttrData;
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case ({VideoEnable,HR})
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2'b00 : InputToAttrOutput = (RadasEnabled)? {1'b0,Border,1'b0,Border} : {2'b00,Border,3'b000};
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2'b01,
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2'b11 : InputToAttrOutput = {2'b01,~HRInk,HRInk};
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2'b10 : InputToAttrOutput = AttrData;
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endcase
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end
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// AttrOutput register
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reg [7:0] AttrOutput = 8'h00;
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wire [2:0] StdPaperColour = AttrOutput[5:3];
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wire [2:0] StdInkColour = AttrOutput[2:0];
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wire Bright = AttrOutput[6];
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wire Flash = AttrOutput[7];
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always @(posedge clk7) begin
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if (AttrOutputLoad)
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AttrOutput <= InputToAttrOutput;
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end
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// Combinational logic to generate pixel bit
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reg Pixel;
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always @* begin
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if (HR)
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Pixel = SerialOutputHR;
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else
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Pixel = SerialOutput;
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end
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// Flash!
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reg [4:0] FlashCounter = 5'h00;
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wire FlashFF = FlashCounter[4];
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wire PixelWFlash = Pixel ^ (Flash & FlashFF);
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always @(posedge clk7) begin
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if (vc==BVSYNC && hc==0)
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FlashCounter <= FlashCounter + 1;
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end
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// Standard ULA final 4-bit IGRB colour
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reg [3:0] StdPixelColour;
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always @* begin
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if (PixelWFlash)
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StdPixelColour = {Bright,StdInkColour};
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else
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StdPixelColour = {Bright,StdPaperColour};
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end
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// LUT-based translatator from IGRB to 9-bit GRB
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`define none 3'b000
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`define half 3'b101
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`define full 3'b111
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reg [8:0] Std9bitColour;
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always @* begin
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case (StdPixelColour) // speccy colour to GGGRRRBBB colour. If you want to alter the standard palette,
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// this is what you need to touch ;)
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0,8: Std9bitColour = {`none,`none,`none};
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1: Std9bitColour = {`none,`none,`half};
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2: Std9bitColour = {`none,`half,`none};
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3: Std9bitColour = {`none,`half,`half};
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4: Std9bitColour = {`half,`none,`none};
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5: Std9bitColour = {`half,`none,`half};
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6: Std9bitColour = {`half,`half,`none};
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7: Std9bitColour = {`half,`half,`half};
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9: Std9bitColour = {`none,`none,`full};
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10: Std9bitColour = {`none,`full,`none};
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11: Std9bitColour = {`none,`full,`full};
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12: Std9bitColour = {`full,`none,`none};
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13: Std9bitColour = {`full,`none,`full};
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14: Std9bitColour = {`full,`full,`none};
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15: Std9bitColour = {`full,`full,`full};
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default: Std9bitColour = {`none,`none,`none};
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endcase
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end
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// PaletteReg register (ULAplus)
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reg [6:0] PaletteReg = 7'h00;
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always @(posedge clkregs) begin
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if (PaletteRegLoad)
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PaletteReg <= din[6:0];
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end
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// ConfigReg register (ULAplus)
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reg [1:0] ConfigReg = 2'b00;
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wire ULAplusEnabled = ConfigReg[0];
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assign RadasEnabled = ConfigReg[1];
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always @(posedge clkregs) begin
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if (rst_n == 1'b0)
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ConfigReg <= 2'b00;
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else if (ConfigRegLoad)
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ConfigReg <= din[1:0];
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end
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// Palette LUT
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wire [7:0] PaletteEntryToCPU;
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wire [7:0] ULAplusPaperColour;
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wire [7:0] ULAplusInkColour;
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wire [5:0] AddressA1 = (RadasEnabled)? {2'b00,InputToAttrOutput[7:4]} :
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{InputToAttrOutput[7:6],1'b1,InputToAttrOutput[5:3]};
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wire [5:0] AddressA2 = (RadasEnabled)? {2'b00,InputToAttrOutput[3:0]} :
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{InputToAttrOutput[7:6],1'b0,InputToAttrOutput[2:0]};
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lut palette (
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.clk(clk28),
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.load(PaletteLoad),
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.din(din),
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.a1(AddressA1),
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.a2(AddressA2),
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.a3(PaletteReg[5:0]),
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.do1(ULAplusPaperColour),
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.do2(ULAplusInkColour),
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.do3(PaletteEntryToCPU)
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);
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// AttrPlusOutput register
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reg [15:0] AttrPlusOutput = 16'h0000;
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always @(posedge clk7) begin
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if (AttrOutputLoad)
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AttrPlusOutput <= {ULAplusPaperColour,ULAplusInkColour};
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end
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// ULAplus final 8-bit GGGRRRBB colour
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reg [7:0] ULAplusPixelColour;
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always @* begin
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case ({RadasEnabled,hc[1],Pixel})
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3'b000,
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3'b010 : ULAplusPixelColour = AttrPlusOutput[15:8];
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3'b001,
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3'b011 : ULAplusPixelColour = AttrPlusOutput[7:0];
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3'b100,
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3'b101 : ULAplusPixelColour = AttrPlusOutput[15:8]; // pixel izquierdo del par
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3'b110,
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3'b111 : ULAplusPixelColour = AttrPlusOutput[7:0]; // pixel derecho del par
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default : ULAplusPixelColour = AttrPlusOutput[15:8];
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endcase
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end
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// 332-GRB to 333-GRB (blue turns from B1 B0 into B1 B0 B1)
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wire [8:0] ULAplus9bitColour = {ULAplusPixelColour,ULAplusPixelColour[1]};
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// Final stage. Final colour is connected to PAL generator
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always @* begin
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if (ULAplusEnabled) begin
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gi = ULAplus9bitColour[8:6];
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ri = ULAplus9bitColour[5:3];
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bi = ULAplus9bitColour[2:0];
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end
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else begin
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gi = Std9bitColour[8:6];
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ri = Std9bitColour[5:3];
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bi = Std9bitColour[2:0];
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end
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end
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// Column address register (CA)
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reg [4:0] CA = 5'h00;
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always @(posedge clk7) begin
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if (CALoad)
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CA <= hc[7:3];
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end
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// VRAM Address generation
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wire [8:0] hcd = hc + 9'hFF8; // hc delayed 8 ticks
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always @* begin
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if (!RadasEnabled) begin
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if (BitmapAddr) begin
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va = {PG,vc[7:6],vc[2:0],vc[5:3],CA};
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end
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else if (AttrAddr) begin
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if (HCL==1'b0)
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va = {PG,3'b110,vc[7:3],CA};
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else
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va = {1'b1,vc[7:6],vc[2:0],vc[5:3],CA};
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end
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else
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va = 14'hZZZZ;
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end
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else begin
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va = {PG,vc[7:1],hcd[7:2]};
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end
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end
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///////////////////////////////////////////////
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// ULA control unit
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///////////////////////////////////////////////
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// control data flow from VRAM to RGB output
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always @* begin
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BitmapDataLoad = 1'b0;
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AttrDataLoad = 1'b0;
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SerializerLoad = 1'b0;
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VideoEnable = 1'b0;
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AttrOutputLoad = 1'b0;
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BitmapAddr = 1'b0;
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AttrAddr = 1'b0;
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CALoad = 1'b0;
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if (!RadasEnabled) begin // Control para los modos est<73>ndar
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if (hc[2:0]==3'd4) begin // hc=4,12,20,28,etc
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AttrOutputLoad = 1'b1; // updated every 8 pixel clocks
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end
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if (hc[2:0]==3'd3) begin
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CALoad = 1'b1;
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end
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if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area
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VideoEnable = 1'b1;
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if (hc[2:0]==3'd4) begin
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SerializerLoad = 1'b1; // updated every 8 pixel clocks, if we are in paper area
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end
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end
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if (hc>=BHPIXEL && hc<=EHPIXEL && vc>=BVPIXEL && vc<=EVPIXEL) begin
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if (hc[3:0]==4'd8 || hc[3:0]==4'd12) begin
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BitmapAddr = 1'b1;
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end
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if (hc[3:0]==4'd9 || hc[3:0]==4'd13) begin
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BitmapAddr = 1'b1;
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BitmapDataLoad = 1'b1;
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end
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if (hc[3:0]==4'd10 || hc[3:0]==4'd14) begin
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AttrAddr = 1'b1;
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end
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if (hc[3:0]==4'd11 || hc[3:0]==4'd15) begin
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AttrAddr = 1'b1;
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AttrDataLoad = 1'b1;
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end
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end
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end
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else begin // Control para el modo radastaniano
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if (hc[1:0]==2'b11) begin // trasladamos dos p<>xeles a la salida
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AttrOutputLoad = 1'b1;
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end
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if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area
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VideoEnable = 1'b1;
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if (hc[1:0]==2'b01) begin // s<>lo durante video activo: se lee la memoria de pantalla
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AttrDataLoad = 1'b1;
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end
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end
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end
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end
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///////////////////////////////////////////////
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// ULA interface with CPU
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///////////////////////////////////////////////
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parameter
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TIMEXPORT = 8'hFF,
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TIMEXMMU = 8'hF4,
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ULAPLUSADDR = 16'hBF3B,
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ULAPLUSDATA = 16'hFF3B;
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// Z80 writes values into registers
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// Port 0xFE
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always @(posedge clkregs) begin
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if (WriteToPortFE) begin
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{spk,mic} <= din[4:3];
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end
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end
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// TIMEX and ULAplus ports
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always @* begin
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TimexConfigLoad = 1'b0;
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PaletteRegLoad = 1'b0;
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ConfigRegLoad = 1'b0;
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PaletteLoad = 1'b0;
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WriteToPortFE = 1'b0;
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if (iorq_n==1'b0 && wr_n==1'b0) begin
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if (a[0]==1'b0 && a[7:0]!=TIMEXMMU)
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WriteToPortFE = 1'b1;
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else if (a[7:0]==TIMEXPORT)
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TimexConfigLoad = 1'b1;
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else if (a==ULAPLUSADDR)
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PaletteRegLoad = 1'b1;
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else if (a==ULAPLUSDATA) begin
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if (PaletteReg[6]==1'b0) // writting a new value into palette LUT
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PaletteLoad = 1'b1;
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else
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ConfigRegLoad = 1'b1; // writting a new value into ULAplus config register
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end
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end
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end
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reg post_processed_ear; // EAR signal after being altered by the keyboard current issue
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always @* begin
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if (issue2_keyboard)
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post_processed_ear = ear ^ (spk | mic);
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else
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post_processed_ear = ear ^ spk;
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end
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// Z80 gets values from registers (or floating bus)
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always @* begin
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dout = 8'hFF;
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if (iorq_n==1'b0 && rd_n==1'b0) begin
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if (a[0]==1'b0 && a[7:0]!=8'hF4)
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dout = {1'b1,post_processed_ear,1'b1,kbd};
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else if (a==ULAPLUSADDR)
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dout = {1'b0,PaletteReg};
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else if (a==ULAPLUSDATA && PaletteReg[6]==1'b0)
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dout = PaletteEntryToCPU;
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else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1)
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dout = {7'b0000000,ConfigReg};
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else if (a[7:0]==TIMEXPORT && enable_timexmmu)
|
||
dout = TimexConfigReg;
|
||
else begin
|
||
if (BitmapAddr || AttrAddr)
|
||
dout = vramdata;
|
||
else
|
||
dout = 8'hFF;
|
||
end
|
||
end
|
||
end
|
||
|
||
///////////////////////////////////
|
||
// AUXILIARY SIGNALS FOR CONTENTION CONTROL
|
||
///////////////////////////////////
|
||
wire iorequla = !iorq_n && (a[0]==0);
|
||
wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA);
|
||
wire ioreqall_n = !(iorequlaplus || iorequla);
|
||
|
||
reg Border_n;
|
||
always @* begin
|
||
if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
|
||
Border_n = 1;
|
||
else
|
||
Border_n = 0;
|
||
end
|
||
|
||
///////////////////////////////////
|
||
// CPU CLOCK GENERATION (Altwasser method)
|
||
///////////////////////////////////
|
||
|
||
//`define MASTERCPUCLK clk7
|
||
// reg ioreqtw3 = 0;
|
||
// reg mreqt23 = 0;
|
||
// wire N1y2 = ~access_to_contmem | ioreqall_n;
|
||
// wire N3 = hc[3:0]>=4'd4;
|
||
// wire N4 = ~Border_n | ~ioreqtw3 | ~mreqt23 | ~cpuclk;
|
||
// wire N5 = ~(N1y2 | N3 | N4);
|
||
// wire N6 = ~(hc[3:0]>=4'd4 | ~Border_n | ~cpuclk | ioreqall_n | ~ioreqtw3);
|
||
// assign cpuclk = (hc[0] | N5 | N6);
|
||
//
|
||
// always @(posedge cpuclk) begin
|
||
// ioreqtw3 <= ioreqall_n;
|
||
// mreqt23 <= mreq_n;
|
||
// end
|
||
|
||
// wire Nor1 = (~access_to_contmem & ioreqall_n) | (hc[3:0]<4'd12) |
|
||
// (~Border_n | ~ioreqtw3 | ~cpuclk | ~mreqt23);
|
||
// wire Nor2 = (hc[3:0]<4'd4) | ~Border_n | ~cpuclk | ioreqall_n | ~ioreqtw3;
|
||
// wire CLKContention = ~Nor1 | ~Nor2;
|
||
//
|
||
// always @(posedge cpuclk) begin
|
||
// if (!CLKContention) begin
|
||
// ioreqtw3 <= ioreqall_n;
|
||
// mreqt23 <= mreq_n;
|
||
// end
|
||
// end
|
||
//
|
||
// assign cpuclk = (!CLKContention || RadasEnabled || disable_contention)? hc[0] : 1'b1;
|
||
//
|
||
// reg CPUInternalClock = 0;
|
||
// always @(posedge `MASTERCPUCLK) begin
|
||
// if (!CLKContention || RadasEnabled || disable_contention)
|
||
// CPUInternalClock <= ~CPUInternalClock;
|
||
// else
|
||
// CPUInternalClock <= 1'b1;
|
||
// end
|
||
//
|
||
// assign cpuclk = CPUInternalClock;
|
||
|
||
|
||
|
||
///////////////////////////////////
|
||
// CPU CLOCK GENERATION (CSmith method)
|
||
///////////////////////////////////
|
||
|
||
reg MayContend_n;
|
||
always @* begin // esto era negedge clk7 en el esquem<65>tico
|
||
if (hc[3:0]>4'd3 && Border_n==1'b1)
|
||
MayContend_n <= 1'b0;
|
||
else
|
||
MayContend_n <= 1'b1;
|
||
end
|
||
|
||
reg CauseContention_n;
|
||
always @* begin
|
||
if ((access_to_contmem || !ioreqall_n) && !RadasEnabled && !disable_contention)
|
||
CauseContention_n = 1'b0;
|
||
else
|
||
CauseContention_n = 1'b1;
|
||
end
|
||
|
||
reg CancelContention = 1'b1;
|
||
always @(posedge cpuclk) begin
|
||
if (!mreq_n || !ioreqall_n)
|
||
CancelContention <= 1'b1;
|
||
else
|
||
CancelContention <= 1'b0;
|
||
end
|
||
|
||
//assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0];
|
||
|
||
assign CPUContention = (~(MayContend_n | CauseContention_n | CancelContention));
|
||
|
||
endmodule
|