mirror of https://github.com/zxdos/zxuno.git
58 lines
1.2 KiB
VHDL
58 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity sd is
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port
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(
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clock : in std_logic;
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pause : out std_logic;
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iorq : in std_logic;
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rd : in std_logic;
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wr : in std_logic;
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oe : out std_logic;
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di : in std_logic_vector( 7 downto 0);
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do : out std_logic_vector( 7 downto 0);
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a : in std_logic_vector(15 downto 0);
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--
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sdClock : out std_logic;
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sdCs : out std_logic;
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sdDi : out std_logic;
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sdDo : in std_logic
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);
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end;
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architecture behavioral of sd is
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signal rx : std_logic;
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signal tx : std_logic;
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begin
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process(clock)
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begin
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if rising_edge(clock)
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then
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if iorq = '0' and wr = '0' and (a(7 downto 0) = x"1F" or a(7 downto 0) = x"E7") then sdCs <= di(0); end if;
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end if;
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end process;
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rx <= '1' when iorq = '0' and rd = '0' and (a(7 downto 0) = x"3F" or a(7 downto 0) = x"EB") else '0';
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tx <= '1' when iorq = '0' and wr = '0' and (a(7 downto 0) = x"3F" or a(7 downto 0) = x"EB") else '0';
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Uspi : entity work.spi port map
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(
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clk => clock,
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enviar_dato => tx,
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recibir_dato => rx,
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din => di,
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dout => do,
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oe_n => oe,
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wait_n => pause,
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--
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spi_clk => sdClock,
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spi_di => sdDi,
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spi_do => sdDo
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);
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end;
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