mirror of https://github.com/zxdos/zxuno.git
139 lines
3.5 KiB
Verilog
139 lines
3.5 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:39:25 07/25/2015
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// Design Name:
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// Module Name: tld_sam
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tld_sam (
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input wire clk50mhz,
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// Audio I/O
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input wire ear,
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output wire audio_out_left,
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output wire audio_out_right,
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// Video output
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inout wire [2:0] r,
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inout wire [2:0] g,
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inout wire [2:0] b,
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inout wire hsync,
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inout wire vsync,
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output wire [2:0] dr,
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output wire [2:0] dg,
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output wire [2:0] db,
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output wire dhsync,
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output wire dvsync,
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output wire stdn,
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output wire stdnb,
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// SRAM interface
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output wire [20:0] sram_addr,
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inout wire [7:0] sram_data,
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output wire sram_we_n,
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// PS/2 keyoard interface
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inout wire clkps2,
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inout wire dataps2
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);
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// Interface with RAM
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wire [18:0] sram_addr_from_sam;
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wire sram_we_n_from_sam;
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// Audio and video
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wire [1:0] sam_r, sam_g, sam_b;
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wire sam_bright;
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// scandoubler
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wire hsync_pal, vsync_pal;
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wire [2:0] ri = {sam_r, sam_bright};
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wire [2:0] gi = {sam_g, sam_bright};
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wire [2:0] bi = {sam_b, sam_bright};
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assign dr = r;
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assign dg = g;
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assign db = b;
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assign dhsync = hsync;
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assign dvsync = vsync;
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assign stdn = 1'b0; // fijar norma PAL
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assign stdnb = 1'b1; // y conectamos reloj PAL
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wire clk24, clk12, clk6, clk8;
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reg [7:0] poweron_reset = 8'h00;
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reg [1:0] scandoubler_ctrl = 2'b00;
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always @(posedge clk6) begin
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poweron_reset <= {poweron_reset[6:0], 1'b1};
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if (poweron_reset[6] == 1'b0)
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scandoubler_ctrl <= sram_data[1:0];
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end
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assign sram_addr = (poweron_reset[7] == 1'b0)? 21'h008FD5 : {2'b00, sram_addr_from_sam};
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assign sram_we_n = (poweron_reset[7] == 1'b0)? 1'b1 : sram_we_n_from_sam;
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relojes los_relojes (
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.CLK_IN1 (clk50mhz), // IN
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// Clock out ports
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.CLK_OUT1 (clk24), // modulo multiplexor de SRAM
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.CLK_OUT2 (clk12), // ASIC
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.CLK_OUT3 (clk6), // CPU y teclado PS/2
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.CLK_OUT4 (clk8) // SAA1099 y DAC
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);
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samcoupe maquina (
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.clk24(clk24),
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.clk12(clk12),
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.clk6(clk6),
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.clk8(clk8),
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.master_reset_n(poweron_reset[7]),
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// Video output
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.r(sam_r),
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.g(sam_g),
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.b(sam_b),
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.bright(sam_bright),
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.hsync_pal(hsync_pal),
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.vsync_pal(vsync_pal),
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// Audio output
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.ear(~ear),
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.audio_out_left(audio_out_left),
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.audio_out_right(audio_out_right),
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// PS/2 keyboard
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.clkps2(clkps2),
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.dataps2(dataps2),
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// SRAM external interface
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.sram_addr(sram_addr_from_sam),
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.sram_data(sram_data),
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.sram_we_n(sram_we_n_from_sam)
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);
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vga_scandoubler #(.CLKVIDEO(12000)) salida_vga (
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.clkvideo(clk12),
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.clkvga(clk24),
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.enable_scandoubling(scandoubler_ctrl[0]),
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.disable_scaneffect(~scandoubler_ctrl[1]),
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.ri(ri),
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.gi(gi),
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.bi(bi),
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.hsync_ext_n(hsync_pal),
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.vsync_ext_n(vsync_pal),
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.ro(r),
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.go(g),
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.bo(b),
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.hsync(hsync),
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.vsync(vsync)
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);
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endmodule
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