mirror of https://github.com/zxdos/zxuno.git
45 lines
916 B
Verilog
45 lines
916 B
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 03:40:28 02/17/2014
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// Design Name:
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// Module Name: lut
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module lut(
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input wire clk,
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input wire load,
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input wire [7:0] din,
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input wire [5:0] a1,
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input wire [5:0] a2,
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input wire [5:0] a3,
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output wire [7:0] do1,
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output wire [7:0] do2,
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output wire [7:0] do3
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);
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reg [7:0] lut[0:63];
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assign do1 = lut[a1];
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assign do2 = lut[a2];
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assign do3 = lut[a3];
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always @(posedge clk)
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if (load)
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lut[a3] <= din;
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endmodule
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