mirror of https://github.com/zxdos/zxuno.git
135 lines
2.2 KiB
Verilog
135 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:02:16 02/16/2014
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// Design Name: ula
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// Module Name: C:/Users/rodriguj/Documents/zxspectrum/zxuno/repositorio/cores/ula_reloaded/tb_ula.v
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// Project Name: ula_reloaded
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: ula
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tb_ula;
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// Inputs
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reg clk14;
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reg wssclk;
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reg rst_n;
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reg [15:0] a;
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reg mreq_n;
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reg iorq_n;
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reg rd_n;
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reg wr_n;
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reg [7:0] din;
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reg ear;
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reg [4:0] kbd;
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// Outputs
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wire cpuclk;
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wire int_n;
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wire [7:0] dout;
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wire [13:0] va;
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wire [7:0] vramdata;
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wire mic;
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wire spk;
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wire clkay;
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wire clkdac;
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wire clkkbd;
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wire [2:0] r;
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wire [2:0] g;
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wire [2:0] b;
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wire csync;
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wire y_n;
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// Instantiate the Unit Under Test (UUT)
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ula uut (
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.clk14(clk14),
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.wssclk(wssclk),
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.rst_n(rst_n),
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.a(a),
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.mreq_n(mreq_n),
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.iorq_n(iorq_n),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.cpuclk(cpuclk),
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.int_n(int_n),
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.din(din),
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.dout(dout),
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.va(va),
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.vramdata(vramdata),
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.ear(ear),
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.kbd(kbd),
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.mic(mic),
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.spk(spk),
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.clkay(clkay),
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.clkdac(clkdac),
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.clkkbd(clkkbd),
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.r(r),
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.g(g),
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.b(b),
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.csync(csync),
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.y_n(y_n)
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);
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ram videoram (
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.a(va),
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.dout(vramdata)
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);
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initial begin
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// Initialize Inputs
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clk14 = 0;
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wssclk = 0;
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rst_n = 0;
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a = 0;
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mreq_n = 1;
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iorq_n = 1;
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rd_n = 1;
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wr_n = 1;
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din = 0;
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ear = 0;
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kbd = 5'b11111;
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// Wait 100 ns for global reset to finish
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#200; rst_n = 1'b1;
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// Add stimulus here
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end
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always begin
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clk14 = #35.714285714285714285714285714286 ~clk14;
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end
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always begin
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wssclk = #100 ~wssclk;
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end
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endmodule
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module ram (
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input wire [13:0] a,
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output wire [7:0] dout
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);
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reg [7:0] mem[0:16383];
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initial begin
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$readmemh ("pantalla_ulatest3.hex", mem);
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end
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assign dout = mem[a];
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endmodule
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